Gas Annealing Research Articles

Effects of forming gas annealing on the doping of monolayer MoS2 crystals

Here we report the effects of forming gas (5% H2 in N2) annealing on the doping behavior of mechanically-exfoliated, natural n-type MoS2 monolayers. Although the fabricated MoS2 transistors exhibited an enhanced device performance because of the reduced contact resistance after annealing at 200 °C for 2 h, the corresponding Raman and photoluminescence spectra suggested that the forming gas annealing suppressed the n-type doping behavior of MoS2. X-ray photoelectron spectroscopy and Kelvin probe force microscopy measurements consistently suggested a downward movement of the Fermi level of the MoS2 monolayers after the forming gas annealing. These results demonstrate the importance of optimizing the process conditions during the forming gas annealing for the fabrication of MoS2 transistors and devices based on transition metal dichalcogenides.

Effects of High‐Pressure H2 and D2 Post‐Metallization Annealing on the Electrical Properties of HfO2/Si0.7Ge0.3

High‐pressure annealing (HPA) in both hydrogen (H2) and deuterium (D2) environments is attempted on HfO2/Si0.7Ge0.3 capacitors as a post‐metallization annealing (PMA) approach. As compared with conventional forming gas annealing (FGA), a dramatic reduction in the interface state density (Dit) is achieved after both H2‐ and D2‐HPA processes at the equivalent temperature (300 °C) and time (30 min) by effectively passivating the Ge‐induced dangling bonds at the interface region. Meanwhile, the stress‐induced leakage current characteristics are only improved by the D2‐HPA process, indicating that D‐passivation is more resistant to external electrical stress than H‐passivation. As the PMA temperature increases to 500 °C, both HPA further decreases the Dit, but a significant increase is observed for FGA. In addition, the PMA temperature‐dependent degradation of leakage current is less in HPA than in FGA.

Addressing separation and edge passivation challenges for high efficiency shingle heterojunction solar cells

We are reporting the fabrication of high efficiency Silicon heterojunction shingle solar cells with very limited performance losses related to the cell separation. A clean and innovative separation process was elaborated and optimized, based on 45° rotated silicon brick and wafers fabrication, allowing the alignment of the preferential cleavage plan (110) with the solar cells bus bars. Hence, a simple but efficient mechanical crack propagation was sufficient to insure a proper shingles cell cut. The smooth resulting solar cell edges were found to be sensitive to surface passivation technologies. Aluminum oxide layers fabricated by atomic layer deposition were specifically developed so that their activation process is fully compatible with heterojunction low temperature constraints (typically less than 220°C). Interestingly, we showed that the annealing temperature alone was not sufficient to activate such layers; alternative forming gas annealing and/or light soaking treatments were thus successfully applied instead with very high passivation values measured on bare samples. Such layers were then deposited and activated on 45° wafer based cleaved heterojunction solar cells edges. Applied for example on heterojunction shingle cell configuration, we managed to recover up to 80% of the initial efficiency loss due to the separation, limiting the overall efficiency losses to less than 0.2% absolute. • (110) edge oriented Si wafers for mechanical separation of shingle cells. • Low temperature ALD AlOx layers with high passivation properties. • Light soaking and hydrogen rich atmosphere for low temperature activation. • New separation and passivation protocol strongly reduces efficiency cut losses.

Hyperdoped Si nanocrystals embedded in silica for infrared plasmonics.

We present the experimental realization of plasmonic hyperdoped Si nanocrystals embedded in silica via a combination of sequential low energy ion implantation and rapid thermal annealing. We show that phosphorus dopants are incorporated into the nanocrystal cores at concentrations up to six times higher than P solid solubility in bulk Si by combining 3D mapping with atom probe tomography and analytical transmission electron microscopy. We shed light on the origin of nanocrystal growth at high P doses, which we attribute to Si recoiling atoms generated in the matrix by P implantation, which likely increase Si diffusivity and feed the Si nanocrystals. We show that dopant activation enables partial nanocrystal surface passivation that can be completed by forming gas annealing. Such surface passivation is a critical step in the formation of plasmon resonance, especially for small nanocrystals. We find that the activation rate in these small doped Si nanocrystals is the same as in bulk Si under the same doping conditions.

Development of Phosphorus-Doped Nanoscale Poly-Si Passivating Contacts via Inkjet Printing for Application in Silicon Solar Cells

Herein, high-quality localized phosphorus-doped polycrystalline silicon (poly-Si) passivating contacts containing nanoscale poly-Si film (∼100 nm) on an ultrathin SiOx layer (∼1.5 nm) were fabricated via an inkjet printing technique. A detailed study of the impacts of inkjet printer settings, dopant concentration, and annealing temperature on the poly-Si passivating contact performance (represented by implied open-circuit voltage iVoc and contact resistivity ρc) was carried out. By applying optimized process conditions on symmetrical industrially processed intrinsic poly-Si/SiOx/n-type crystalline Si (c-Si) substrates, good surface passivation was achieved with an iVoc of 699 mV, together with a low ρc of 6.4 mΩ·cm2, after annealing at 975 °C. After a hydrogenation treatment via the deposition of aluminum oxide (AlOx)/silicon nitride (SiNy) stack and subsequent forming gas annealing (FGA), the optimum annealing temperature shifted to 950 °C and the iVoc was further improved to an excellent value of 729 mV. Optical images reveal that a line width of 75 μm can be realized on a mechanically polished silicon wafer. Moreover, high-resolution micro-photoluminescence (μ-PL) maps clearly demonstrate the localization of the doped regions on the symmetrical substrate after annealing. These results show that inkjet printing is a promising technique for the fabrication of localized poly-Si/SiOx passivating contacts in high-efficiency solar cells with high flexibility and simplicity.

Effects of Hydrogen on Endurance Characteristics in NAND Flash Memories

This study comprehensively investigates the effect of hydrogen content in forming gas annealing (FGA) on the endurance of NAND flash memories by statistically analyzing the transconductance () characteristics. The degradation () worsened with higher cycling temperature, delayed time period from erasing to programming () operation, and higher word-line bias () during Moreover, these effects become more pronounced as the hydrogen content in FGA increases. Using the measured distributions and Monte -Carlo TCAD technology, the activation energy () of oxide damage creation can be extracted. The extracted values were 50 meV and 160 meV for the diluted (4%) and pure (100%) hydrogen samples, respectively. This suggests that a higher hydrogen concentration results in more ionized hydrogen atoms remaining in the oxide layer. During these hydrogen ions can drift near the Si/SiO2 surface, where they may react to form trap states. is revealed to have a linear relationship with respect to where the slope is independent of the hydrogen content in FGA.

Boron‐doped polysilicon using spin‐on doping for high‐efficiency both‐side passivating contact silicon solar cells

AbstractThis study focuses on boron‐doped p+polysilicon (poly‐Si) passivating contacts using spin‐on doping (SOD). Experimental conditions, including annealing conditions, SOD concentration, and poly‐Si thickness, were controlled to improve passivation. Based on the analysis results, the passivation quality mainly changes with indiffusion and doping concentration, causing Auger recombination and field effects. Meanwhile, grain size also influences the passivation quality but showed marginal characteristics. Through further optimization using an etch back and diffusion barrier, the efficiency of the flat reference solar cell was improved to 17.5% with an open‐circuit voltage of 695 mV using a p+ poly‐Si contact emitter, the highest reported efficiency using SOD on saw‐damage‐etched surfaces. This study includes a detailed analysis of SOD p+ poly‐Si and shows promising results with potential for application in tandem devices. Furthermore, the cell efficiency is expected to increase by controlling the doping profile and application of textured surfaces, selective emitters, and forming gas annealing (FGA).

A combinatorial study on ZnO-In2O3-SnO2 system: The effects of different postgrowth annealing conditions on optical and electrical properties

ZnO-In2O3-SnO2 (ZITO) thin film library was produced via the combinatorial approach. The films were deposited using a magnetron sputtering system. Varying ZITO compositions were obtained in a single deposition run by employing a custom-made triangular type of substrate carrier magazine. The effect of various postgrowth annealing atmospheres on the electrical and optical properties of the films were examined. Air, Ar, forming gas (Ar+4 vol% H2), and successive annealing under forming gas + argon atmospheres were studied. Room temperature (RT) deposited films were identified either crystalline or amorphous depending on the location of the substrate on the holder. All these samples exhibited average visible transmittance (Tvis) below 75 % and sheet resistance (RS) higher than 50 Ω/□. Annealing under air atmosphere improved the optical and electrical properties of the films significantly, but not simultaneously for the same composition. Although better optical improvement was achieved by annealing under Ar and increase in electrical conductivity after annealing under forming gas, optimum properties have been obtained with the latter condition. Tvis values above 85 % and RS values below 50 Ω/□ were attained. On the other hand, successive annealing did not provide any advantage in reaching optimal samples when compared to single gas atmosphere annealings. Further, increasing the annealing temperature were found to be beneficial particularly for the conductivity of many compositions. Finally, this study has introduced a systematic approach to produce transparent conductive oxide thin films with reduced indium content that can be suitable for many optoelectronic applications.

Low-temperature deuterium annealing to improve performance and reliability in a MOSFET

Low-temperature deuterium (D2) annealing (LTDA) is applied to improve performances and reliability of a MOSFET. The LTDA is performed at 300 °C, which is at least 100 °C lower than the widely used temperature of forming gas annealing (FGA) with H2, which contributes to reducing a thermal budget especially in the backend-of-the-line (BEOL). DC performances, such as subthreshold slope (SS), threshold voltage (VTH), and on-current (ION) were statistically compared in cases with and without the LTDA to evaluate their improvements. Profiling of D2 by secondary ion mass spectrometry (SIMS) supports that D2 can permeate a gate oxide and passivate dangling bonds and traps near the interface of the SiO2-Si channel. Therefore ION, SS, and VTH were improved, gate leakage current (IG) was reduced, and immunity to positive bias stress (PBS) became better.

A novel reduction approach for fabrication of transparent conducting fluorine and tin doped indium oxide thin film with low sheet resistance

Surface and interface engineering of fluorine and tin doped indium oxide thin film at mild conditions to modulate optoelectronic properties is of great significance. Herein, a simple, low-cost solgel-spin-coating method was used to create a reproducible, scalable, stable, transparent, and conducting tin fluorine doped indium oxide thin film (FTIO thin film). To improve the electrical and optical properties of the thin film, a novel chemical reduction process was developed that did not require any reducing gas, inert atmosphere, and high temperature annealing. The chemical reduction time and concentration of NaBH4-dependent analysis shows a big drop (∼83%) in sheet resistance, due to increased oxygen vacancy in thin film. This increased oxygen vacancy was confirmed from XPS analysis. The treated FTIO thin film show lower resistivity (ρ = 0.95 × 10−3 Ω cm), highest figure of merit (0.001 Ω-1), roughness of 19.53 Å, and sheet resistance of 193 ± 3 Ω/sq, when compared to all other the solgel-spin-coating thin film process testified to date. To test the general applicability of the proposed reduction technique, it was applied to commercially available ITO thin film, and found to reduce sheet resistance by more than 53% (≤7 ± 1 Ω/sq) of the initial sheet resistance. Compared to other common post-treatment approaches, the proposed methodology reduces sheet resistance and could satisfy the demands of most real applications.

Enhanced photo-carrier transportation at semiconductor/electrolyte interface of TiO2 photoanode by oxygen vacancy engineering

The practicality of photoanodes for photoelectrochemical (PEC) water splitting was severely hampered by poor bulk photo-carrier separation and slow surface reaction kinetics. Here, we report an oxygen vacancy-enriched TiO2 photoanode modified by a highly crystalline TiO2 layer with enhanced bulk photo-carrier separation and surface reaction kinetics through stepwise gas diffusion at elevated temperatures. Experimental studies reveal that the reduction treatment introduces oxygen vacancy to TiO2, thereby increasing the charge carrier concentration and shifting the Fermi level to conduction band. The oxidation treatment affects the oxygen vacancy distribution of TiO2 surface which forms a suitable Fermi energy difference with the bulk, thus accelerating the carriers’ drift near to semiconductor/electrolyte interface. The as-obtained TiO2 photoanode exhibits an enhanced photocurrent density of 2.26 mA cm−2 at +1.23 V vs. RHE which is 2.75 times higher than that of the pristine TiO2. Hence, the present work illustrates the great potential of oxygen vacancy engineering via simple gas annealing treatment for Fermi level manipulation that can be further explored to other metal oxide semiconductors to design highly efficient oxygen vacancy enriched crystalline PEC photoelectrodes and provides novel insights into contact interfaces between semiconductors and electrolytes in PEC water splitting.

Impact of Iterative Deuterium Annealing in Long-Channel MOSFET Performance.

In contrast to conventional forming gas annealing (FGA), high-pressure deuterium annealing (HPD) shows a superior passivation of dangling bonds on the Si/SiO2 interface. However, research detailing the process optimization for HPD has been modest. In this context, this paper demonstrates the iterative impact of HPD for the better fabrication of semiconductor devices. Long-channel gate-enclosed FETs are fabricated as a test vehicle. After each cycle of the annealing, device parameters are extracted and compared depending on the number of the HPD. Based on the results, an HPD condition that maximizes on-state current (ION) but minimizes off-state current (IOFF) can be provided.

Fixed-charge generation in SiO2/GaN MOS structures by forming gas annealing and its suppression by controlling Ga-oxide interlayer growth

A recent study has shown that anomalous positive fixed charge is generated at SiO2/GaN interfaces by forming gas annealing (FGA). Here, we conducted systematic physical and electrical characterizations of GaN-based metal-oxide-semiconductor (MOS) structures to gain insight into the charge generation mechanism and to design optimal interface structures. A distinct correlation between the amount of FGA-induced fixed charge and interface oxide growth indicated the physical origins of the fixed charge to be defect formation driven by the reduction of the Ga-oxide (GaO x ) interlayer. This finding implies that, although post-deposition annealing in oxygen compensates for oxygen deficiencies and FGA passivates defect in GaN MOS structures, excessive interlayer GaO x growth leads to instability in the subsequent FGA treatment. On the basis of this knowledge, SiO2/GaO x /GaN MOS devices with improved electrical properties were fabricated by precisely controlling the interfacial oxide growth while taking advantage of defect passivation with FGA.

Ge/Si multilayer epitaxy and removal of dislocations from Ge-nanosheet-channel MOSFETs

Horizontally stacked pure-Ge-nanosheet gate-all-around field-effect transistors (GAA FETs) were developed in this study. Large lattice mismatch Ge/Si multilayers were intentionally grown as the starting material rather than Ge/GeSi multilayers to acquire the benefits of the considerable difference in material properties of Ge and Si for realising selective etching. Flat Ge/Si multilayers were grown at a low temperature to preclude island growth. The shape of Ge nanosheets was almost retained after etching owing to the excellent selectivity. Additionally, dislocations were observed in suspended Ge nanosheets because of the absence of a Ge/Si interface and the disappearance of the dislocation-line tension force owing to the elongation of misfit dislocation at the interface. Forming gas annealing of the suspended Ge nanosheets resulted in a significant increase in the glide force compared to the dislocation-line tension force; the dislocations were easily removed because of this condition and the small size of the nanosheets. Based on this structure, a new mechanism of dislocation removal from suspended Ge nanosheet structures by annealing was described, which resulted in the structures exhibiting excellent gate control and electrical properties.

Effects of High-Pressure Annealing on the Low-Frequency Noise Characteristics in Ferroelectric FET

In this work, the low-frequency noise (LFN) characteristics of hafnium-zirconium oxide (HZO) ferroelectric field-effect transistors (FeFETs) with and without high-pressure forming gas annealing (HPA) treatment are investigated. The origin of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1/ {f}$ </tex-math></inline-formula> noise in the FeFET without HPA is changed from carrier number fluctuation to Hooge’s mobility fluctuation after wake-up due to the remote phonon scattering from the polarized HZO. Also, Hooge’s parameter is increased by the program/erase (P/E) cycling-induced stress. On the contrary, only the correlated mobility fluctuation is increased after the wake-up in the FeFET with HPA. Furthermore, the LFN of the FeFET with HPA shows robustness to P/E cycling-induced stress after the wake-up, showing superb endurance performance.

Effect of ALD Processes on Physical and Electrical Properties of HfO2 Dielectrics for the Surface Passivation of a CMOS Image Sensor Application

The surface passivation of a CMOS image sensor (CIS) is highly beneficial for the overall improvement of a device performance. We employed the thermal atomic layer deposition (T-ALD) and plasma enhanced (PE-ALD) techniques for the deposition of 20 nm HfO₂ as well as stacked with 3 and 5 nm Al₂O₃ thin films. The HfO₂/Si and Al₂O₃/HfO₂/Si metal-oxide-semiconductor structures were used to analyze the fixed charge density (Q_f) and interface trap density (D_it). The as-synthesized samples show high D_it and Q_f values (10¹² cm^-2eV^-1) and a minority carrier lifetime of 15-300 &#x03BC;s. The finite-difference time-domain simulation of high-k dielectrics confirmed that the Al₂O₃ (top)/HfO₂ stacked structures expected higher quantum efficiency for CIS application. The effect of vacuum annealing (VA) and forming gas annealing (FGA) treatments succeeded with the decomposition of the D_it and increase in carrier lifetime. The H₂ ambient FGA samples showed a remarkable decrease in the D_it values. To improve the overall performance of the device after passivation, we employed an Al₂O₃/HfO₂ bilayer structure, which showed a low D_it of 10¹¹ cm^-2eV^-1 and a minority carrier lifetime of &#x007E;3,700 &#x03BC;s after 400 &#x00B0;C and 30 min FGA. We believe that this surface passivation strategy will pave way for future CIS technology regarding the development of lower defective surface and superior performance.

Investigation of Gallium–Boron Spin‐On Codoping for poly‐Si/SiOx Passivating Contacts

A doping technique for p‐type poly‐Si/SiOx passivating contacts using a spin‐on method for different mixtures of Ga and B glass solutions is presented. Effects of solution mixing ratios on the contact performance (implied open circuit voltage iVoc, contact resistivity ρc) are investigated. For all as‐annealed samples at different drive‐in temperatures, increasing the percentage of Ga in the solution shows a decrement in iVoc (from ∼680 to ∼610 mV) and increment in ρc (from ∼3 to ∼800 mΩ cm2). After a hydrogenation treatment by depositing a SiNx/AlOx stack followed by forming gas annealing, all samples show improved iVoc (∼700 mV with Ga‐B co‐doped, and ∼720 mV with all Ga). Interestingly, when co‐doping Ga with B, even a small amount of B in the mixing solution shows negative effects on the surface passivation. Active and total dopant profiles obtained by electrical capacitance voltage and secondary‐ion mass spectrometry measurements, respectively, reveal a relatively low percentage of electrically‐active Ga and B in the poly‐Si and Si layers. These results help understand the different features of the two dopants: a low ρc with B, a good passivation with Ga, their degree of activation inside the poly‐Si and Si layers, and the annealing effects.

Optimization of Tunnel‐Junction for Perovskite/Tunnel Oxide Passivated Contact (TOPCon) Tandem Solar Cells

A systematic study of the formation of the tunnel‐junction for perovskite/TOPCon tandem solar cells is presented, which consists of a B‐doped poly‐Si (p+‐poly‐Si) and P‐doped poly‐Si (n+‐poly‐Si) double‐layer structure. The rear emitter double‐side TOPCon solar cell is selected as the bottom cell in tandem solar cells, where a p+‐poly‐Si/SiOx forms the rear emitter and an n+‐poly‐Si/SiOx forms the front field with the poly‐Si layer deposited by plasma‐enhanced vapor deposition (PECVD) and crystallized in a furnace. The tunnel‐junction is formed by depositing an additional B‐doped a‐Si:H (p+‐a‐Si:H) on the front n+‐poly‐Si and following a rapid thermal anneal (RTA) to partially crystallize the p+‐a‐Si:H with minimized interdiffusion of B and P. The tunnel‐junction is systematically optimized and it is found that the RTA process at 700 °C produces the optimized tunnel‐junction with the minimal contact resistivity of ≈16 mΩ cm2. The tunnel‐junction formation affects the passivation of the front field TOPCon, but the losses in the passivation quality can be recovered by a forming gas annealing. This process provides a simple and useful method for making the tunnel‐junction in perovskite/TOPCon tandem solar cells.

Effectiveness of UV-Ozone Treatment and Alneal Process for Si Surface Passivation with Sol-Gel Spray-Coated SiO2 Film

Passivated Emitter and Rear Contact (PERC) cell is dominating solar market over conventional Aluminum-Back Surface Field cells [1]. PERC structure uses dielectric passivation layer at the rear to overcome optical and electrical losses, enhancing the cell performance. Silicon dioxide (SiO2) film passivates both n- and p-type silicon (Si). Thermal oxidation provides excellent Si passivation but adds to the thermal budget. An alternative, spray-coating, is a low-temperature deposition technique which is industrially viable and has high throughput and therefore, substantiates its potential for implementation in solar industry.We achieved low surface recombination velocity (Seff) of 8.07 cmsec-1 with spray-coated SiO2 film on p-type Si and anticipated that good passivation is due to UV-Ozone treatment and alneal [2]. In this work, a thorough investigation is performed in terms of interface state density (Dit) and fixed oxide charge density (Qf), extracted from capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics of metal-oxide-semiconductor (MOS) capacitor.In this work, p-type Si wafers were RCA cleaned without final 2% HF dip. For MOS capacitor fabrication, samples were bifurcated into two sets. One set was processed as it is and another set was dipped in 2% HF and was UV-Ozone treated for 5 min. Sol-gel prepared using tetraethyl orthosilicate, iso-propyl alcohol, deionized water, and nitric acid was sprayed over these wafers using custom-designed spray-coater tool. Subsequently, wafers were baked at 150oC and subjected to Post Deposition Annealing (PDA) in O2 ambient for 30 min. Front and rear contacts were created by depositing Aluminum (Al) dots over the film and Al blanket at the back of Si, respectively. These were further divided into two. One set of each was not treated further and the other was subjected to Post Metallization Annealing (PMA) in Forming gas annealing (FGA; 4% H2 and 96% N2) ambient for 30 min. Lifetime structures were fabricated for RCA oxide and UV-Ozone treated samples with SiO2 deposited on both sides of wafer following the sequence discussed above and were subjected to PDA. Al was blanket deposited on both sides of the wafer. These structures were subjected to PMA in FG ambient for 30 min. Later, Al was etched.Effectiveness of UV-Ozone treatment is demonstrated by comparing Dit and Qf with RCA-oxide. Thickness of spray-coated SiO2 film is ∼17 nm and of RCA oxide and UV-Ozone oxide is ∼1.5 nm. Dit of 1.4-1.6×1012 cm-2eV-1 is obtained for RCA oxide and 3.0-4.1×1011 cm-2eV-1 for UV-Ozone oxide after PDA without PMA (Fig. 1(a)). Dit is an order of magnitude less for UV-Ozone oxide, providing better chemical passivation in comparison to the RCA oxide. UV-Ozone oxide gives lower Qf in comparison to the RCA oxide (Fig 1(b)). Qf values are 2.3-2.8×1012 and 0.92-1.5×1012 cm-2 for RCA oxide and UV-Ozone oxide, respectively. Therefore, UV-Ozone treatment prior to film deposition gives better interface quality than RCA oxide. This can be attributed to surface cleaning in addition to oxide formation during UV-Ozone treatment [3].Efficacy of alneal was studied by comparing PMA effect on films over RCA oxide and UV-Ozone oxide. Dit for film on RCA oxide and UV-Ozone oxide are 0.84-1.1×1011 cm-2eV-1 and 2.0-6.0×1010 cm-2eV-1, respectively after PDA and PMA. Dit has reduced by an order of magnitude after PMA. This is attributed to hydrogen passivation provided by PMA in FG ambient [4]. Process of annealing after Al deposition is termed as alneal. Qf has also reduced after alneal. Qf values are 6.2-7.0 × 1011 cm-2 and 3.8-6.5 × 1011 cm-2 for RCA oxide and UV-Ozone oxide, respectively. The trends in Qf and Dit can be correlated to the shift in C-V characteristics and G-V peak value, respectively (Fig. 2 (a) and (b)).Lifetime of 118.66 µsec and 459.52 µsec was measured using Sinton lifetime tester and corresponding Seff was calculated as 95.59 cms-1 and 8.07 cms-1 for film over RCA oxide and UV-Ozone oxide, respectively (Fig. 3). UV-Ozone oxide provides better passivation in comparison to the RCA oxide. Low Seff in case of UV-Ozone oxide is attributed to low Dit, as both these oxides show similar Qf.Therefore, it can be concluded that good passivation with low Seff for spray-coated SiO2 film is attributed to UV-Ozone treatment as well to the alneal process.

Effect of different types of substrate surface treatments on the graphene device performance

Graphene–substrate interface is very crucial for analyzing graphene device performance. In this article, we have shown how the graphene device performance got affected because of different types of substrate surface treatment techniques used before graphene transfer. For fabrication of graphene devices, monolayer chemical vapor deposition (CVD) graphene was transferred onto SiO2 grown thermally on Si substrate. Forming gas annealed SiO2/Si shows better device performance as compared with as‐grown SiO2 on Si substrate. A further effect of oxygen plasma and argon plasma cleaning of SiO2 surface before graphene transfer was investigated. Forming gas annealing improves the performance and plasma treatment degrade the graphene devices' performance.