Ge/Si multilayer epitaxy and removal of dislocations from Ge-nanosheet-channel MOSFETs

Chun-Lin Chu,Po-Yen Chen,Shu-Han Hsu,Jen-Yi Chang,Po-Yu Wang,Dean Chou

doi:10.1038/s41598-021-04514-y

Abstract

Horizontally stacked pure-Ge-nanosheet gate-all-around field-effect transistors (GAA FETs) were developed in this study. Large lattice mismatch Ge/Si multilayers were intentionally grown as the starting material rather than Ge/GeSi multilayers to acquire the benefits of the considerable difference in material properties of Ge and Si for realising selective etching. Flat Ge/Si multilayers were grown at a low temperature to preclude island growth. The shape of Ge nanosheets was almost retained after etching owing to the excellent selectivity. Additionally, dislocations were observed in suspended Ge nanosheets because of the absence of a Ge/Si interface and the disappearance of the dislocation-line tension force owing to the elongation of misfit dislocation at the interface. Forming gas annealing of the suspended Ge nanosheets resulted in a significant increase in the glide force compared to the dislocation-line tension force; the dislocations were easily removed because of this condition and the small size of the nanosheets. Based on this structure, a new mechanism of dislocation removal from suspended Ge nanosheet structures by annealing was described, which resulted in the structures exhibiting excellent gate control and electrical properties.

Highlights

Abbreviations gate-all-around field-effect transistors (GAAFETs) Gate-all-around field-effect transistors SOI Silicon-on-insulator SC1&SC2 Standard cleaning 1 & 2 low-pressure chemical vapour deposition (LPCVD) Low-pressure chemical vapour deposition transmission electron microscopy (TEM) Transmission electron microscopy PL Photoluminescence XRD X-ray diffraction transformer-coupled plasma (TCP) Transfer-coupled plasma buried oxide (BOX) Buried oxide reciprocal space mapping (RSM) Reciprocal space mapping tetramethylammonium hydroxide (TMAH) Tetramethylammonium hydroxide forming gas annealing (FGA) Forming gas annealing atomic layer deposition (ALD) Atomic layer deposition FD Net glide force C–V Capacitance–voltage curve capacitance equivalent thickness (CET) Capacitance equivalent thickness S/D Source/drain Id/Vg Drain current—gate voltage technology computer-aided design (TCAD) Technology computer-aided design equivalent oxide thickness (EOT) Equivalent oxide thickness
To prepare the starting material, three periods of Ge(40 nm)/Si(25 nm) epitaxial layers were grown on SOI(100) with a 40-nm Si layer using a low-pressure chemical vapour deposition (LPCVD) system with GeH4 and SiH4 gases
The thickness of the deposited Ge film was determined by transmission electron microscopy (TEM), and no dislocations were detected in the Ge nanosheets during TEM observations conducted in parallel with photoluminescence (PL) analysis

Summary

Introduction

Abbreviations GAAFETs Gate-all-around field-effect transistors SOI Silicon-on-insulator SC1&SC2 Standard cleaning 1 & 2 LPCVD Low-pressure chemical vapour deposition TEM Transmission electron microscopy PL Photoluminescence XRD X-ray diffraction TCP Transfer-coupled plasma BOX Buried oxide RSM Reciprocal space mapping TMAH Tetramethylammonium hydroxide FGA Forming gas annealing ALD Atomic layer deposition FD Net glide force C–V Capacitance–voltage curve CET Capacitance equivalent thickness S/D Source/drain Id/Vg Drain current—gate voltage TCAD Technology computer-aided design EOT Equivalent oxide thickness. It is essential to employ substrates and epitaxial materials with mismatched lattice constants.

Results

Conclusion