Garbage Outputs Research Articles

PDQRRFF: Poisson-distributed quantum random reversible flip flop generator for BIST

Reversible logic has gained popularity recently because it allows circuits to use significantly less power. Due to the inherent reversibility of quantum operation, there is enormous interest in designing and optimizing reversible circuits. In this work, a new gate named as transvidkan gate, Quantum Random Reversible Flip Flop, Sequence generator, and Build in Self-Test (BIST) has been proposed. Quantum Random Reversible Flip Flop (QRRFF) is an emerging technology that is used in a variety of apps that use modern security and encryption systems. For creating a random string, typical approaches combine an entropy source with an elimination or bit-generation system. Quantum computing reversible logic chips and Low-power design are emerging as intriguing research topics. A classical logic-based 8-bit reversible comparator is represented using existing reversible gates. This study provides a BIST-based architecture for a comparator design that reduces the garbage outputs, quantum cost, and constant inputs. According to simulation result, the proposed approach outperforms traditional methods in terms of hardware complexity and quantum cost.

Creating a Logic Divider Based on BCD and Utilizing the Vedic Direct Flag Method

Reversible logic has potential for a variety of applications demanding low energy usage since it prevents information loss and energy waste. The purpose of this work is to design a new Vedic divider circuit with reversible gates. Efficiency in quantum and ASIC parameters is demonstrated by the Reversible Direct Flag Vedic Division Method (RDFVDM), which has been devised. Block-level reversible gates are used in the RDFVDM to provide benefits including lower quantum costs and less trash outputs. The performance of Cadence EDA Tool is validated by simulation trials. Based on a comparative examination utilizing current methodologies, RDFVDM performs better than comparable designs. Interestingly, it improves energy usage by 26%. Moreover, RDFVDM performs exceptionally well in terms of quantum cost while employing the RSA cryptographic technique, efficiently managing 1276,293 constant inputs and 311 garbage outputs.

Qutrit representation of quantum images: new quantum ternary circuit design

Quantum computation is growing in significance and proving to be a powerful tool in meeting the high real-time computational demands of classical digital image processing. However, extensive research has been done on quantum image processing, mainly rooted in binary quantum systems. In this paper, we propose a new quantum ternary image circuit based on the analysis of the existing qutrit representation of quantum images. The proposed design utilizes ternary shift gates and ternary Muthukrishnan–Stroud gates, with the belief that this circuit can be used for ternary quantum image processing. This study makes a significant improvement compared to the existing counterpart in terms of quantum cost, the number of constant inputs, and garbage outputs, which are all essential parameters in quantum circuit design.

Design of Reversible Serial Adder Based on EPOE Expressions for Computational Applications

Considering the growing trend toward reducing the size of electronic devices, reducing power consumption has become one of the major concerns of circuit designers. One of the solutions to reduce power consumption is the design of reversible circuits. This paper proposed the design of a low-cost self-control serial adder system. In the proposed circuit, EPOE expressions have been used for the direct and compact design of sequential circuits to reduce the fixed inputs of sequential logic circuits. In addition, to reduce the quantum cost, common terms between the outputs are optimally used. Also, limiting the use of Tofoli gates with a size larger than three inputs in the implementation of the final circuit will reduce the quantum cost of the resulting circuit. The results and comparisons showed that the proposed design has improved efficiency measures including quantum cost, garbage outputs, and fixed inputs compared to existing works.

Design and Simulation of Reversible Logic Gate Using HCS Macro-Model

—Reversible Logic Gates have become very popular for their uninhibited merits like, low power consumption, low garbage output, decreasing the quantum cost, least propagation delay etc. Several circuits have been designed for reversible logic ICs using conventional CMOS technology. But, as the CMOS technology is suffering from scaling down problems, the researchers have moved themselves towards post CMOS devices for further fabrication of Reversible ICs. Among different post CMOS devices, in SET, electrons are tunnelling through the channel one by one, so it offers ultra-low power dissipation compared to the traditional CMOS though it has high speed, high gain like properties. So the hybridization of CMOS-SET can achieve a useful effect on VLSI design, and the new technology is known as Hybrid CMOS-SET (HCS). But as the Hybrid CMOS-SET requires two distinct software, the HCS macro model has become very useful, as it can be simulated by using a single software. In this present paper, the reversible logic gate has been designed using the HCS macro model and is also being simulated using a single software, MATLAB with SIMULINK, with low power consumption.

A New Approach to Design of Cost-Efficient Reversible Quantum Dual-Full Adder and Subtractor

This paper proposed the design and development of reversible cost-efficient innovative quantum dual-full adder and subtractor or QD-FAS circuit using quantum gate. The proposed circuit can be used as full adder and full subtractor simultaneously, which is designed using double Peres gate or DPG and Feynman gate or FG. The quantum cost, garbage output and constant input of the QD-FAS is 8, 1 and 1. Which is better w.r.t previously reported work. The QD-FAS circuit, as proposed, includes shared sum and difference terminals, as well as a carry-out and a borrow output terminal. Notably, this innovation showcases a remarkable 27.27% reduction in quantum cost. The improvement in garbage output is even more striking, showing a 50% enhancement. When assessing the overall advancement in quantum cost, it falls within the range of 27.27% to 66.66%. To confirm the viability of this design, extensive testing is carried out using the IBM Qiskit simulator. This design holds significant importance in a variety of applications, including quantum computing, cryptography, and the realm of reversible Arithmetic Logic Units (ALU).

Advancing nanoscale computing: Efficient reversible ALU in quantum-dot cellular automata

This paper presents a significant contribution to the field of nanoscale computing by proposing an innovative reversible Arithmetic and Logic Unit (ALU) implemented in Quantum-Dot Cellular Automata (QCA). Reversible logic and QCA technology offer promising alternatives to conventional CMOS technology, addressing the challenges of operating at nanoscale dimensions. The primary objective is to develop a highly efficient ALU capable of performing 26 distinct arithmetic and logical operations. The ALU design is based on a novel reversible full adder-subtractor optimized for minimal quantum cost, which is crucial for energy-efficient quantum computation. The evaluation encompasses various criteria related to reversibility, such as gate count, number of constant inputs, number of garbage outputs, and quantum cost. QCA-specific criteria, including cell count, occupied area, and clock cycles, are also considered. The outcomes of this research contribute to the advancement of cell-efficient nanoscale computing, with implications for quantum computation, emerging technologies, and future integrated circuit design.

Design and Optimization of Reversible Arithmetic Unit Using Modified Gate Diffusion Input Logic

ABSTRACTIncreasing integration levels and demand for portability have made minimising the power consumption of circuits increasingly important for wide range of applications. Reversible logic is a low-power, low-loss design that can be utilised in low power CMOS, optical computing, nanotechnology, and quantum computing. Quantum machine learning Research is an area examines combining ideas from quantum computing and machine learning. In this paper, a new design of reversible logic-based arithmetic unit is demonstrated with CMOS and modified-GDI (MGDI) methodology for nanoscales using reversible gates. We provide a design for an optimized arithmetic unit, as well as some proposed methodologies for designing a reversible arithmetic unit with novel reversible gates, and compare them to existing circuits in terms of garbage output, constant input, number of reversible gates, and quantum cost, in this work. It can also be employed in Quantum computers due to its lower Quantum Cost and Garbage Output. Transistor-level implementations of the proposed arithmetic units are accomplished using Cadence Virtuoso tool GPDK 90 nm technology in combination with CMOS and MGDI techniques. Due to the optimization, the proposed arithmetic unit shows better performance in worst-case delay and power consumption than a comparable non-optimized Arithmetic Unit. According to the design and analysis of proposed Arithmetic Units. The proposed −1 design of the 4-bit Arithmetic Unit achieves optimisation by incorporating a reduced number of reversible gates and exhibiting a low quantum cost (12&40) using MGDI-FS. Similarly, the proposed −2 and 3 designs minimizes the number of transistors required, with a count of 80 and 120, and proposed −3 design, it eliminates the presence of constant inputs entirely using MGDI-FS.

Enhancing Smart City Waste Management through LBBOA based RIAN Classification

Effective trash management has become a top environmental priority, especially in urban areas with significant population growth where garbage output is on the rise. As cities work to manage garbage properly, innovative waste management programmes have the potential to increase effectiveness, cut costs, and improve the aesthetic appeal of public places. This article introduces SCM-RIAN, a powerful "Smart City Management and Classification System" built on the Internet of Things (IoT) and deep learning (DL) technologies. Convolutional neural networks are used in the garbage classification model that is implemented within this smart city management and classification framework. This system for classifying waste is intended to categorise rubbish into several classes at waste collection sites, encouraging recycling. The Rotation-Invariant Attention Network (RIAN) is a unique approach presented for the categorization process to address a prevalent problem in smart city management (SCM). A Centre Spectral Attention (CSpeA) module built within RIAN isolates spectral bands from other categories of pixels' influence, reducing redundancy. As an alternative to the conventional 3 3 convolution, to obtain rotation-invariant spectral-spatial data contained in SCM patches, the Rectified Spatial Attention (RSpaA) module is also introduced. The suggested RIAN for SCM classification is built on the integration of the CSpeA, 11 convolution, and RSpaA modules. The Ladybird Beetle Optimisation Algorithm (LBBOA) is used to optimise hyperparameters. With improved results compared to other current models, this suggested SCM-RIAN achieved 98.12% accuracy (ACC) with high sensitivity (SEN), specificity (SPEC), and kappa index (KI) using the garbage classification dataset.

Effect of coconut shell ash substitute with cement on the mechanical properties of cement concrete

The production of ordinary portland cement results in a great amount of carbon dioxide emissions, which has serious consequences for the environment. The building industry has been urged to make use of soil waste from industries or secondary materials in order to cut down on the amount of natural raw materials needed to make cement and concrete. Increases in population, economic activity, and social progress have all contributed to a rise in global garbage output. The investigation of waste reduction and reuse is one of the most alluring possibilities for handling such waste. It is becoming increasingly unaffordable to use cement in concrete works, despite the fact that the demand for homes and other constructions that rely on this material continues to rise in combination with the expansion of the human population; as a result, it is necessary to identify and develop alternative binding materials that can be used either wholly or partially in place of cement. In order to produce coconut shell ash (CSA), an agricultural waste material and environmental pollutant that is used as pozzolana in partial replacement of cement in the production of concrete, coconut shells are collected, burned in the open air (uncontrolled combustion) for three hours, and then incinerated in a muffle furnace at 800oC for seven hours. On the order of 0%, 5%, 10%, 15%, 20%, and 25% OPC was replaced with CSA in the concrete used to cast the specimens. Coconut shell ash is a viable cement replacement. The impact of CSA on mechanical qualities was investigated using a range of coconut shell ash replacements.

Environmental Impact Analysis of Methane Gas from Landfill using LCA in Klotok landfill, Kediri, East Java

The effective management of municipal solid waste is a persistent challenge within emerging nations. The observed phenomenon can be attributed to a multitude of reasons, encompassing swift economic growth, urban population development, garbage output, the substantial costs associated with waste treatment, and the design and functionality of containment systems. Methane, being the second most significant greenhouse gas following carbon dioxide, is prominently emitted into the environment by municipal solid waste dumps. This study use the IPCC model to assess the methane emissions generated by landfills. Additionally, Simapro 9.5 software is utilised in conjunction with the ReCiPe 2016 Midpoint approach to evaluate the corresponding environmental consequences. The Klotok landfill was found to generate the maximum quantity of methane, specifically 3.518 Mg CO2 eq, as determined by the composition analysis of paper waste. Additionally, the largest environmental impact was observed in the category of human toxicity carcinogenicity, as indicated by the life cycle assessment (LCA) analysis with a value of 3733.057.

High-efficient reversible full adder realized by dynamic threshold-based gate diffusion input logics

A new 12-transistor reversible full adder (FA) is designed based on carbon-nanotube-field effect transistors (CNTFETs) with 32 nm channel length and an area of 0.2204 μm2, 1 constant input (CI), and 3 garbage outputs (GO). The FA has 3 reversible logic gates in two of its stages that are realized by the gate diffusion input (GDI) technique. In the FA, 2 Toffoli gates with 1 CI and 1 new GDI-reversible-multiplexer are used to generate Sum and Cout, respectively. The multiplexer is 3*3, with two GOs, and a significant area reduction by only two transistors. The inputs of the circuit prevent the excessive increase of GOs and CIs. The Monte Carlo analysis using the HSPICE simulator indicates a better sensitivity of the FA versus fabrication with 6.45%, 1.86%, and 8.01% improvements of maximum values of power, delay, and power-delay-product (PDP). The FA is implemented in a 4-bit, 8-bit, 16-bit, and 32-bit ripple carry adder (RCA), and its superior results are seen. Under 32-bit RCA, the proposed circuit with 4956.30 fJ shows more energy savings compared to most competitors. The extracted results, the different figure of merits (FoMs), and reversibility features represent the proposed circuit as a desirable procedure for future works.

Performance analysis of full adder and full subtractor using quantum-dot cellular automata

Quantum cellular automata (QCA), a nanotechnology application has shown to be a profoundly powerful computational environment when compared to CMOS. This article uses a quantum dot cellular automaton (QCA) to primarily project the implementation and simulation outcome of different regenerable full adders and full subtractors. The technique for changing irreversible functions into reversible ones is used to achieve the same. For improving the energy efficiency of the QCA based designs, the conversion of irreversible functions to reversible is quite desirous in recent era. A novel symmetric and planar design for a majority gate having five inputs whose fault tolerant is suggested. The designs outperform the best existing ones concerning complexity, size, and delay, the quantity of majority and invertible gates, garbage outputs, including control inputs.

Design of Multiplexers using Reversible Logic Technique

Reversible logic is promising as it can be applied to different applications in low power like nanocomputing especially in quantum computing. Reversible logic is a technioue for power reduction. Reversible circuits are similar to digital circuits but they work using reversible logic gates. This study focuses on reducing the garbage output and ancilla inputs in reversible multiplexers, thereby reducing the power consumption. In this study two designs of Multiplexers are given. Design1 is using TwinSJ gate and AJ gate. 2:1, 4:1 and 8:1 multiplexers are built. In Design 2, a new gate (SJ gate) is built which functions as 2:1 multiplexer. It has 4*4 configuration. The inputs are suitably configured so that it performs various logic functions. Using this SJ gate and other basic reversible logic gates, 2:1, 4:1 and 8:1 multiplexers are built. In 2:1 multiplexer, Ancilla inputs are improved to '0' from 5 and garbage output has been reduced to 2 against 7 in existing design. 4:1 multiplexers are built with ‘0’ ancilla inputs against 2 and 11 in existing designs. Garbage output of the proposed 4:1 multiplexer is 5 against 6 and 16 in existing designs. 8:1 multiplexer is built with 1 ancilla input and 11 garbage output against 2 and 12 respectively in existing design. This is designed using VHDL code - xilinx 14.7 for verification purpose and simulated on ISIM.

A Novel Spin Based Logic Circuitry Synthesis Using SS Gate

Abstract: Because of its perceived advantages, reversible logic has attracted a lot of study attention. It introduces commendable characteristics like low power consumption, minimized garbage output, and least propagation delay. Reversible logic integrated circuits (ICs) have been produced utilizing traditional CMOS topology in a number of published research endeavors up to this point. However, because CMOS technology is already experiencing a common scaling down issue, researchers are now focusing on post-CMOS devices for the manufacturing of reversible integrated circuits in the future. This particular research project is focused on related research projects that feature reversible IC design based on Spintronic. The authors first implemented spinoriented conventional reversible logic gates and evaluated their effectiveness in terms of generated garbage values, power consumption, device integrity, and size. Later, in order to understand the benefits of the suggested Single Spin Logic based SS gate, the authors come across an SS gate that is singular in its kind and stick to its spin realization.

Quantum Bilinear Interpolation Algorithms Based on Geometric Centers

Bilinear interpolation is widely used in classical signal and image processing. Quantum algorithms have been designed for efficiently realizing bilinear interpolation. However, these quantum algorithms have limitations in circuit width and garbage outputs, which block the quantum algorithms applied to noisy intermediate-scale quantum devices. In addition, the existing quantum bilinear interpolation algorithms cannot keep the consistency between the geometric centers of the original and target images. To save the above questions, we propose quantum bilinear interpolation algorithms based on geometric centers using fault-tolerant implementations of quantum arithmetic operators. Proposed algorithms include the scaling-up and scaling-down for signals (grayscale images) and signals with three channels (color images). Simulation results demonstrate that the proposed bilinear interpolation algorithms obtain the same results as their classical counterparts with an exponential speedup. Performance analysis reveals that the proposed bilinear interpolation algorithms keep the consistency of geometric centers and significantly reduce circuit width and garbage outputs compared to the existing works.

Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

AbstractMost error-resilient media processing applications use multipliers as their basic building blocks. These are power-consumption and computationally intensive modules. In the existing works, several types of the multipliers were used to improve the hardware capacity, but those methods did not provide sufficient results. Therefore, in this manuscript, a Baugh-Wooley Multiplier design using Multiple Control Toffoli (MCT) and Multiple Control Fredrick gate (MCF) Reversible Logic gate (BWM-MCT-MCF) will be analyzed. Initially, Reversible Full Adder (RFA) is designed using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates. Then the proposed Reversible Full Adder is used in Baugh-Wooley Multiplier. By this, it reduces the hardware complexity with higher speed, lower area, lower power consumption. The proposed BWM-MCT-MCF multiplier is implemented in MATLAB, its performance shows lower Garbage output 22.78%, 24.88%, 20.95% compared with the existing designs, like BWM-FG-FRG, BWM-RL-TG, BWM-TG-FG respectively. Then the designed BWM-MCT-MCF is implemented using Xilinx ISE tool with the Virtex 5 device. From this, the performance of the proposed FPGA-BWM-MCT-MCF method shows lower delay 23.77%, 16.86% compared with the existing designs, like FPGA-BWM-RL-TG, FPGA-BWM-TG-FG respectively.

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

AbstractReversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N1, N2, and N3, which are used to develop a novel effective 2‐bit PP reversible Vedic multiplier and 4‐bit ripples carry adders (RCAs). Moreover, 2‐bit Vedic multiplier and RCA are used to develop the 4‐bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state‐of‐the‐art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two‐bit and four‐bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder compressors. Compared with Vedic multipliers in the literature, the proposed design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters. DesignI has separate binary two’s complement (B2C) and MUX circuits, while DesignII combines binary two’s complement and MUX circuits in one circuit. DesignI shows the lowest quantum cost, 231, regarding state-of-the-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI. The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.

WITHDRAWN: DESIGN OF ADIABATIC CIRCUITS WITH REVERSIBLE LOGIC BASED FULL ADDER AND MULTIPLIER IN CURRENT-MODE LOGIC CIRCUITS FOR EFFICIENT POWER DISSIPATION

The widely used reversible full adder circuits are actualized in preceding research that optimizes design as well as speed of circuits.Theselogic gates that are reversible such as Peres, TSG, Toffoli, Feynman, and Fredkin are predominantly deployed in designing the reversible circuits. Nevertheless, its results are not promising in the context of dissipating static power. Power dissipation has turned out to be crucial issue in designing VLSI circuits. To overcome this problem, the energy recovery principle is introduced, and it is known as Adiabatic Logic. The famous adiabatic, low powered circuits work on reversible logic to store power and revert the same. Multiple Adiabatic Techniques (AT)is employed for dissipating the power in efficient manner. These ATs reduce power dissipation especially in VLSI circuits by performs both charging as well as discharging. The proposed research implements the Reversible Logic (RL) in Full Adder (FA) of Adiabatic Logic Reversible MOS Current-Mode Logic (MCML) FA generally termed Adiabatic Logic Reversible MCML Full Adder (FA) as well as on the Adiabatic Logic Reversible MCML multiplier. This is aimed to produce high speed circuits at reduced power. Reliable performance augmented with speedy operation is prominently exhibited in MCML than CMOS logic family. Coverage area along with improved power consumption may help in deployment of reversible logic in FA pertaining to MCML. Minimal quantity garbage output when given constant inputs is employed in reversible FA. The detailed experimental analysis portrays that proposed circuit can attain improved performance than existing RL like Feynman gate, Peres gate, TSG, Reversible MCML with Full Adder in the context of mean power, static power and current, and coverage area.