WITHDRAWN: DESIGN OF ADIABATIC CIRCUITS WITH REVERSIBLE LOGIC BASED FULL ADDER AND MULTIPLIER IN CURRENT-MODE LOGIC CIRCUITS FOR EFFICIENT POWER DISSIPATION

Abstract

The widely used reversible full adder circuits are actualized in preceding research that optimizes design as well as speed of circuits.Theselogic gates that are reversible such as Peres, TSG, Toffoli, Feynman, and Fredkin are predominantly deployed in designing the reversible circuits. Nevertheless, its results are not promising in the context of dissipating static power. Power dissipation has turned out to be crucial issue in designing VLSI circuits. To overcome this problem, the energy recovery principle is introduced, and it is known as Adiabatic Logic. The famous adiabatic, low powered circuits work on reversible logic to store power and revert the same. Multiple Adiabatic Techniques (AT)is employed for dissipating the power in efficient manner. These ATs reduce power dissipation especially in VLSI circuits by performs both charging as well as discharging. The proposed research implements the Reversible Logic (RL) in Full Adder (FA) of Adiabatic Logic Reversible MOS Current-Mode Logic (MCML) FA generally termed Adiabatic Logic Reversible MCML Full Adder (FA) as well as on the Adiabatic Logic Reversible MCML multiplier. This is aimed to produce high speed circuits at reduced power. Reliable performance augmented with speedy operation is prominently exhibited in MCML than CMOS logic family. Coverage area along with improved power consumption may help in deployment of reversible logic in FA pertaining to MCML. Minimal quantity garbage output when given constant inputs is employed in reversible FA. The detailed experimental analysis portrays that proposed circuit can attain improved performance than existing RL like Feynman gate, Peres gate, TSG, Reversible MCML with Full Adder in the context of mean power, static power and current, and coverage area.