GaN Layers Research Articles

Investigation of defect states in AlGaN/GaN high electron mobility transistors by small-signal admittance analysis

We have performed a small-signal admittance analysis to extract trap parameters in an AlGaN/GaN high electron mobility transistor-on-Si. Whereas the admittance in the accumulation- and depletion-bias regimes is primarily due to the interface traps, the admittance near the threshold voltage and below is due to mono-energetic traps inside GaN. The density extracted for threading dislocation-related 1D traps at ≈0.22 eV below the GaN conduction band edge is similar to that previously reported by reverse-biased gate leakage analysis of the analyzed device. Our analysis suggests additional 1D traps of comparatively lower density ≈4×1014cm−3 but considerably large capture cross section ≈8×10−14cm2 in the GaN layer at ≈0.31 eV below the conduction band. The AlGaN trap density is considerably larger near the AlGaN/GaN interface than in the bulk AlGaN. The AlGaN traps mainly contribute to the voltage stretch; their admittance contribution is negligible. Gate leakage dominates the conductance at lower frequencies.

Epitaxial growth of GaN on β-Ga2O3 via RF plasma nitridation

The lack of suitable p-type dopant for β-Ga2O3 remains a hurdle for vertical power device applications. Epitaxy of GaN on Ga2O3 substrates was demonstrated as an alternative. (–201)-oriented β-Ga2O3 was converted into (0001)-oriented hexagonal GaN via nitrogen plasma in a plasma-assisted molecular beam epitaxy chamber, as verified by XRD and RHEED. The resulting nitridated GaN layers were characterized by TEM, x-ray reflectivity, and AFM to relate the nitridation conditions to crystallinity, layer thickness, and surface roughness. The crystallinity of subsequently grown epitaxial GaN films was quantified via XRD rocking curves and related to the nitridation layer properties across varying nitridation conditions. Specifically, the effect of the grain size and nitridation layer thickness was investigated to determine their role in threading screw dislocation management.

Epitaxy of >7 μm Thick GaN Drift Layers on 150 mm Si(111) Substrates Realizing Vertical PN Diodes with 1200 V Breakdown Voltage

Metal‐organic chemical vapor deposition growth of vertical GaN PN structures on 6″ Si(111) substrates enabling a 1200 V breakdown voltage is demonstrated. Thanks to an optimized buffer structure utilizing island growth in an AlN/Al0.1Ga0.9N superlattice, the threading dislocation density is drastically reduced, and sufficient compressive stress is incorporated in active GaN layers to compensate for the thermal mismatch. Crack‐free PN structures with drift layer thicknesses up to 7.4 μm are realized with a threading dislocation density of ≈5 × 108 cm−2 and an absolute wafer bow <50 μm. Quasi‐vertical PN diodes reveal a linear increase in the breakdown voltage with the drift layer thickness with an average breakdown field of ≈1.6 MV cm−1. Additionally, the leakage current is shown to decrease monotonically as the drift layer thickness increases. For a 7.4 μm thick drift layer with a net ionized donor concentration of 0.9 × 1016 cm−3, a high breakdown voltage of 1200 V, a low specific on‐resistance of 0.4 mΩ cm−2, and a low leakage current of 10−4 A cm−2 (at a reverse bias of 650 V) are obtained. These results demonstrate the great potential of cost‐effective vertical GaN‐on‐Si power devices operating in the kilovolt range.

Simulation study on the effect of palladium layer thickness and temperature on the bonding properties of palladium coated copper wire

Palladium coated copper (PCC) wire is an emerging bonding wire. There are relatively few studies on the effect of palladium plating thickness and temperature on its bonding performance. In order to investigate the effects of three parameters, namely palladium plating thickness, chip preheating temperature and the free air ball (FAB) initial temperature, on the bonding performance of PCC wires, this paper establishes a transient nonlinear finite element analysis model of thermal coupling between bare copper wires and PCC wires, and simplifies the whole bonding process into two stages of impact and ultrasonic vibration to carry out the experimental simulation. Firstly, the Taguchi orthogonal test method was adopted to obtain the ranking of the degree of influence of the three factors on the bonding results, and the optimum palladium plating thickness and FAB initial temperature of 100 nm and 100 °C were derived, respectively. Then the PCC wires with 100 nm palladium plating thickness were selected, and the bare copper wires were used as the reference, and multiple one-factor simulation experiments were carried out under the condition of changing the chip preheating temperature only. The simulation results show that the FAB and pad stress levels in the bonding results of the PCC wires are significantly higher than those of the bare copper wires, but the GaN layer stress is less than that of the bare copper wires. Moreover, there is an approximate parabolic relationship between the maximum stresses of pad and GaN layer and the preheating temperature of the chip. In the bonding results of bare copper wire, there is also an approximate parabolic relationship between the maximum stress of FAB and the chip preheating temperature. This parabolic relationship allows a prediction of the optimum chip preheating temperature. Selecting the appropriate palladium plating thickness and controlling the appropriate FAB temperature and chip preheating temperature can improve the bonding quality, and this numerical simulation work can provide a reference for the selection of palladium plating thickness and temperature parameter regulation of PCC wires.

(10–13)-oriented semipolar GaN growth on (10–10) m-plane ScAlMgO4 substrate

Abstract We report the growth of a GaN layer on (10–10) m-plane ScAlMgO4 (SAM) substrate. The GaN layer demonstrated (10–13) preference growth orientation. The anisotropy of the crystalline quality was distinctly observed through X-ray rocking curve taken across the sample surface over various azimuths across the orthogonal directions [0001] and [1–210] of the SAM substrate. Notably, the crystalline quality exhibited gradual degradation as the substrate is rotated around its surface normal away from the c-direction [0001] of the SAM substrate toward the a-direction [11–20]. Additionally, basal stacking faults in the (10–13)-oriented GaN were observed along [0001] direction using scanning transmission electron microscopy. Moreover, the selected area electron diffraction analysis was utilized to confirm the (10–13) growth orientation that was found to be consistent with the X-ray diffraction result. The (10–13) GaN layer exhibited a metal face through integrated differential phase contrast imaging.

A Novel Isolation Approach for GaN-Based Power Integrated Devices.

This paper introduces a novel technology for the monolithic integration of GaN-based vertical and lateral devices. This approach is groundbreaking as it facilitates the drive of high-power GaN vertical switching devices through lateral GaN HEMTs with minimal losses and enhanced stability. A significant challenge in this technology is ensuring electrical isolation between the two types of devices. We propose a new isolation method designed to prevent any degradation of the lateral transistor's performance. Specifically, high voltage applied to the drain of the vertical GaN power FinFET can adversely affect the lateral GaN HEMT's performance, leading to a shift in the threshold voltage and potentially compromising device stability and driver performance. To address this issue, we introduce a highly doped n+ GaN layer positioned between the epitaxial layers of the two devices. This approach is validated using the TCAD-Sentaurus simulator, demonstrating that the n+ GaN layer effectively blocks the vertical electric field and prevents any depletion or enhancement of the 2D electron gas (2DEG) in the lateral GaN HEMT. To our knowledge, this represents the first publication of such an innovative isolation strategy between vertical and lateral GaN devices.

Optimization of Non-Alloyed Backside Ohmic Contacts to N-Face GaN for Fully Vertical GaN-on-Silicon-Based Power Devices.

In the framework of fully vertical GaN-on-Silicon device technology development, we report on the optimization of non-alloyed ohmic contacts on the N-polar n+-doped GaN face backside layer. This evaluation is made possible by using patterned TLMs (Transmission Line Model) through direct laser writing lithography after locally removing the substrate and buffer layers in order to access the n+-doped backside layer. As deposited non-alloyed metal stack on top of N-polar orientation GaN layer after buffer layers removal results in poor ohmic contact quality. To significantly reduce the related specific contact resistance, an HCl treatment is applied prior to metallization under various time and temperature conditions. A 3 min HCl treatment at 70 °C is found to be the optimum condition to achieve thermally stable high ohmic contact quality. To further understand the impact of the wet treatment, SEM (Scanning Electron Microscopy) and XPS (X-ray Photoelectron Spectroscopy) analyses were performed. XPS revealed a decrease in Ga-O concentration after applying the treatment, reflecting the higher oxidation susceptibility of the N-polar face compared to the Ga-polar face, which was used as a reference. SEM images of the treated samples show the formation of pyramids on the N-face after HCl treatment, suggesting specific wet etching planes of the GaN crystal from the N-face. The size of the pyramids is time-dependent; thus, increasing the treatment duration results in larger pyramids, which explains the degradation of ohmic contact quality after prolonged high-temperature HCl treatment.

Polarization-Doped InGaN LEDs and Laser Diodes for Broad Temperature Range Operation.

This work reports on the possibility of sustaining a stable operation of polarization-doped InGaN light emitters over a particularly broad temperature range. We obtained efficient emission from InGaN light-emitting diodes between 20 K and 295 K and from laser diodes between 77 K and 295 K under continuous wave operation. The main part of the p-type layers was fabricated from composition-graded AlGaN. To optimize injection efficiency and improve contact resistance, we introduced thin Mg-doped layers of GaN (subcontact) and AlGaN (electron blocking layer in the case of laser diodes). In the case of LEDs, the optical emission efficiency at low temperatures seems to be limited by electron overshooting through the quantum wells. For laser diodes, a limiting factor is the freeze-out of the magnesium-doped electron blocking layer for temperatures below 160 K. The GaN:Mg subcontact layer works satisfyingly even at the lowest operating temperature (20 K).

Metalorganic Vapor‐Phase Epitaxy of +c/−c GaN Polarity Inverted Bilayer for Transverse Quasi‐Phase‐Matched Wavelength Conversion Device

Photon‐pair generation based on optical parametric down‐conversion has attracted for the application as a light source for quantum information. Highly efficient wavelength‐conversion devices require a polarity‐inversion structure when using nitride semiconductors. A transverse quasi‐phase‐matching (QPM) polarity‐inverted GaN bilayer channel waveguide device is suitable for efficient wavelength conversion. This study designed a cross‐section device to satisfy the modal dispersion phase‐matching condition between the TM02 mode pump light and the TM00 mode signal/idler light. Moreover, an AlN oxidation interlayer fabricates the Ga‐polar/N‐polar (+c/−c) GaN layers via metalorganic vapor‐phase epitaxy (MOVPE). A 145 nm thick film layer with a macro‐step‐free surface is grown by optimizing the −c‐GaN growth conditions and reducing the substrate off‐angle to 0.2°. Next, the AlN layer is oxidized in an electric furnace and MOVPE is used to regrow a 1500 nm thick +c‐GaN layer. A macrosteps‐free surface can be achieved by reducing the off‐angle to 0.2° and optimizing the −c‐GaN growth conditions to avoid hillock formation. These results pave the way for improving the efficiency of GaN transverse QPM wavelength‐conversion devices.

Electrical Properties of GaN/Ga2O3 P-N Junction Diodes: A TCAD Study

Ga2O3 and GaN are promising candidates for the fabrication of high power semiconductor devices due to their wide band-gap range, deteremined from 3.0 eV to 4.9 eV. Among these materials, the GaN/Ga2O3 P-N junction diode has an excellent performance even at high temperatures, making it suitable for high-power applications. In this work, GaN/Ga2O3 P-N junction diodes are investigated using computer-aided design (TCAD) simulations. The properties of the diode were optimized in terms of the thickness of the p-type GaN layer and its doping concentration. It was found that the current-voltage (IV) characteristic of the diode decreases as the thickness of GaN layer increases. To achieve a high current output, the optimized thickness is determined to be 500 nm. Furthermore, the doping concentration within the diode strongly influences the output current. The highest current is obtained for an un-doped GaN sample, and the increase in the doping concentration leads to a decrease in the obtained current.

GaN thickness dependence of GaN/AlN superlattices on face-to-face-annealed sputter-deposited AlN templates

Recently, deep-ultraviolet (DUV) light-emitting devices have attracted attention for various applications. GaN/AlN superlattices have emerged as a promising alternative for achieving high-efficiency DUV emission. To fabricate superlattices with high crystal quality and abrupt interfaces, we have utilized face-to-face-annealed sputter-deposited AlN template substrates characterized by a flat surface and low dislocation density. Furthermore, radio-frequency plasma-assisted molecular beam epitaxy with in situ reflection high-energy electron diffraction monitoring was employed for the growth process. The growth of the superlattices follows a specific sequence. Step 1: AlN growth, Step 2: conversion of Al droplets to AlN, Step 3: GaN growth, and Step 4: evaporation of Ga droplets. This study explored the impact of GaN thickness on the GaN/AlN superlattice. The GaN thickness was linearly controlled by changing the duration of Step 3. This approach allowed for the growth of a flat GaN layer up to 1 monolayer (ML) and achieved superlattices with abrupt interfaces. Single-peak cathodoluminescence (CL) emission at 240–245 nm was observed from the superlattices, with the peak shift toward longer wavelengths as the GaN thickness increased. In contrast, quantum dot-like GaN islands were generated with a thickness of over 1 ML, induced by compressive strain. Superlattices with thicker GaN exhibited broad CL emission with multiple peaks. However, the AlN barrier layer reduced the surface roughness and maintained abrupt interfaces within the superlattices. Therefore, to obtain sharp single-peak UV emission from GaN/AlN superlattices, the growth sequence should be controlled to obtain flat GaN layers without dots.

Enhanced etching of GaN with N2 gas addition during CVD diamond growth

Diamond on GaN materials processing is not straight-forward, as GaN is susceptible to a quasi-pure hydrogen CVD plasma etching. 1%, 3% and 5% N2 gas was gradually added to the H2 gas with fixed 6% CH4 in the recipe to promote the growth of diamond nanocrystals. Different types of microstructures were produced, with addition of nitrogen to the precursor gas recipe. Nitrogen gas changes the diamond film microstructure from faceted to spherical grains, with signs of GaN etching. The FWHM of the sp3 carbon Raman peak was calculated to be 6.5 cm−1, when there was no nitrogen gas in the precursor recipe, which deteriorates to a large extent after successive addition of N2. Fourier transform infrared spectroscopy (FTIR) showed a strong presence of the nitrogen related defects (peak positions at 1190 and 1299 cm−1) inside the nanocrystalline diamond (NCD) films grown with N2 addition. GaN layer etching from the base substrate by the CVD plasma was clearly evidenced by energy dispersive X-ray spectra (EDS) of the deposited films. Al elemental EDS peaks from the base sapphire substrate were observed for the films grown with nitrogen addition, but no Ga EDS peaks were detected. X-ray diffraction (XRD) micrographs further supported the enhanced GaN etching phenomenon. The electrical resistivity of the uncoated GaN was initially measured to be 22.2 Ω-cm. However, the resistivity rose to 1.59 × 106 Ω-cm after the nitrogen assisted film deposition; due to the GaN etching - thereby exposing the underlying insulating sapphire substrate.

Super-Nernstian potentiometric response of InN/InGaN quantum dots by fractional electron transfer

The potentiometric response of InN/InGaN quantum dots (QDs) on Si (111) is experimentally studied and modeled as a function of the In content and morphology of the InGaN layer below the QDs due to the changing N flux in stationary plasma-assisted molecular beam epitaxy. For isolated core–shell InGaN nanowires formed for N-rich growth, sub-Nernstian response with Cl− anions as the test analyte is observed. For compact columnar InGaN layers formed in a very narrow range of N flux at the N-rich to metal-rich growth transition, a maximum super-Nernstian response of 100 mV/decade is achieved, provided the In content is high. With reducing N flux and In content, low super-Nernstian response and finally sub-Nernstian response are re-established for compact planar GaN layers. The maximum super-Nernstian response and the transition to sub-Nernstian response are quantitatively modeled by the quantum partition of electrons inside and outside of the QDs and consequent fractional electron transfer in the artificial chemical reaction of the QDs with the anions.

Formation of GaN mesas with reverse-tapered edge structures on a lattice-matched AlInN layer for a positive beveled edge termination

GaN mesas were fabricated by sequential dry and wet etching of a +c-oriented GaN layer onto a lattice-matched AlInN layer for future applications of positive beveled edge termination, which is desirable for preventing premature breakdown of power devices. The dry etching produced hexagonal AlInN/GaN mesas surrounded by m-plane sidewalls with six protrusions at the vertices. The subsequent hot phosphoric acid etching selectively etched the AlInN layer to expose and etch the chemically unstable −c surface of the GaN layer, which formed reverse-tapered { 101¯2¯ } facets. The protrusions were sacrificed during the wet etching to prevent undesirable positive tapering at the vertices.

Analysis of the mechanisms by which sputtered AlN nucleation layers enhance the performance of red InGaN-based LEDs

This work proposed to modulate the strain of underlying GaN layers using different thicknesses of sputtered AlN nucleation layer to achieve long-wavelength red InGaN mini-light-emitting diodes (mini-LEDs). The increase in thickness of sputtered AlN from 15 nm to 60 nm could reduce the compressive strain in epitaxial GaN layers, which led to a shift in the peak wavelength of InGaN LEDs ranging from 633 nm to 656 nm at 1 A/cm2. However, a significant decrease in external quantum efficiency (EQE) was observed when the sputtered AlN thickness was increased from 45 nm to 60 nm. We found that the EQE and peak wavelength (PW) of the red mini-LEDs with 45-nm sputtered AlN at 1 A/cm2 were 8.5% and 649 nm, respectively. The study revealed that varying the thickness of AlN nucleation layers could extend the emission of red InGaN mini-LEDs toward longer wavelengths with a slight EQE loss.

Directly Printable Flexible Optoelectronics through Surface Atomic Modification of Liquid Metals at Room Temperature.

Flexible optoelectronics have fully demonstrated their transformative roles in various fields, but their fabrication and application have been limited by complex processes. Liquid metals (LMs) are promising to be ideal raw materials for making flexible optoelectronics due to their extraordinary fluidity and printability. Herein, we propose a painting-modifying strategy based on solution processability for directly printing out fluorescent flexible optoelectronics from LMs via surface modification. The LMs of eGaIn, which were obtained by the mixing of gallium with indium metal spheres, were used as ink to paint high-finesse patterns on flexible substrates. Through introducing surface modification of LMs, the gallium atom on the surface of the LMs was directly transformed into the composite fluorescent functional layers of GaO(OH) and GaN after being modified with an ammonia aqueous solution. Owing to painting, this strategy is not limited by any curved surfaces, shapes, or facilities and has excellent adaptability. Particularly, the fluorescent layers were obtained through a spontaneous, instantaneous, and solution-processable process that is environmentally friendly, easy to administrate, recyclable, and adjustable. The present finding breaks through the limitations of LMs in making flexible optoelectronics and provides strategies for addressing severe challenges facing existing materials and flexible optoelectronics. This method is expected to be very useful for fabricating flexible lights, transformable displays, intelligent anticounterfeiting devices, skin-inspired optoelectronics, and chameleon-biomimetic soft robots in the coming time.

Synthesis of nano-diamond film on GaN surface with low thermal boundary resistance and high thermal conductivity

Joule self-heating is the main obstacle limiting the performance of GaN power devices. A nano-diamond (NCD) film for near-junction heat transfer has been approved as an effective approach to overcome this issue. In the present study, we developed a scheme to deposit a smooth NCD film with high thermal conductivity (TC) over the surface of GaN. First, a 10-nm Si3N4 was deposited as the protective layer of GaN, followed by electrostatic seeding to improve nucleation density and particle distribution uniformity. Second, argon and gradient methane gas were introduced to prepare the NCD film based on nucleation and the growth period. The resulting thickness of the NCD film was 150 nm with a roughness of about 20 nm. The thermal boundary resistance (TBReff) between GaN and NCD film was only 12.8 ± 0.64 m2K/GW, whereas the TC of the NCD film was 200 ± 40 W m−1 K−1, which was similar to the theoretical prediction. Thus, it could be inferred that the high crystallinity of the NCD film contributes to the low TBReff and high TC through the whole NCD layer.

Charge Trapping and Emission during Bias Temperature Stressing of Schottky Gate GaN-on-Silicon HEMT Structures Targeting RF/mm Wave Power Amplifiers.

For operation as power amplifiers in RF applications, high electron mobility transistor (HEMT) structures are subjected to a range of bias conditions, applied at both the gate and drain terminals, as the device is biased from the OFF- to ON-state conditions. The stability of the device threshold voltage (Vt) condition is imperative from a circuit-design perspective and is the focus of this study, where stresses in both the ON and OFF states are explored. We see rapid positive threshold voltage increases under negative bias stress and subsequent recovery (i.e., Vt reduces), whereas conversely, we see a negative Vt shift under positive stress and Vt increase during the subsequent relaxation phase. These effects are correlated with the thickness of the GaN layer and ultimately result from the deep carbon-acceptor levels in the C-GaN back barrier incorporated to screen the buffer between the silicon substrate and the epitaxially grown GaN layer. Methods to mitigate this effect are explored, and the consequences are discussed.

Correlation of heat transport mechanism and structural properties of GaN high electron mobility transistors

Grain sizes, impurities, and layer thicknesses in the nm-range affect the heat transport and, hence, hinder proper heat dissipation of GaN-based devices. To obtain a clear picture of heat dissipation, the mechanisms of heat transport must be linked to the structural properties of the nitride-based materials in the device. In this paper, a systematic investigation of the typical layers of GaN high-electron mobility transistor stacks was conducted by time-domain thermoreflectance analysis and Raman measurements. The analyzed layers are the AlN nucleation layer, the Al0.3Ga0.7N transition layer, the AlGaN/AlN superlattice, the C-doped GaN back-barrier, and the uid GaN layer. The results were interpreted using the Born–van Karman model, including the suppression function approach to describe the governing heat transport mechanisms. Investigation of this AlN nucleation layer showed that its phonon scattering is dominated by impurity and grain boundary scattering. The Al0.3Ga0.7N transition layer was shown to have a reduced thermal conductivity not only due to alloy scattering but also because of grain boundary scattering. The AlGaN/AlN superlattice showed a thermal conductivity lower than the Al0.3Ga0.7N transition layer, especially at higher temperatures (7.2 ± 0.2 W/mK vs 14.1 ± 0.4 W/mK at 300 °C). Caused by the enhanced AlGaN/AlN interface density, the thermal conductance was found to be 2 GW/m2 K. The AlGaN/AlN superlattice indicated an anisotropic thermal transport with a factor of ∼1.5. The C-doped GaN layers were analyzed in terms of their size-dictated thermal conductivity, resulting in a reduction of ∼66% from 1 μm to 250 nm at 30 °C. Raman spectroscopy revealed that the thicker the GaN layer, the higher the compressive stress in GaN, which additionally results in a higher thermal transport. The investigations of the heat transport depending on the structural properties enabled an accurate determination of the thermal conductivity of the layer stack. These thermal conductivities served as input parameters for 3D simulation to extract the temperature, in terms of the thermal resistance, of such high-electron mobility transistor stacks. This simulation shows the importance of the GaN layer in terms of thermal management. This work uncovers the thermal transport in GaN-based transistor stacks with the aim to improving the thermal design.

Microstructure and reflectance of porous GaN distributed Bragg reflectors on silicon substrates

Distributed Bragg reflectors (DBRs) based on alternating layers of porous and non-porous GaN have previously been fabricated at the wafer-scale in heteroepitaxial GaN layers grown on sapphire substrates. Porosification is achieved via the electrochemical etching of highly Si-doped layers, and the etchant accesses the n+-GaN layers through nanoscale channels arising at threading dislocations that are ubiquitous in the heteroepitaxial growth process. Here, we show that the same process applies to GaN multilayer structures grown on silicon substrates. The reflectance of the resulting DBRs depends on the voltage at which the porosification process is carried out. Etching at higher voltages yields higher porosities. However, while an increase in porosity is theoretically expected to lead to peak reflectance, in practice, the highest reflectance is achieved at a moderate etching voltage because etching at higher voltages leads to pore formation in the nominally non-porous layers, pore coarsening in the porous layers, and in the worst cases layer collapse. We also find that at the high threading dislocation densities present in these samples, not all dislocations participate in the etching process at low and moderate etching voltages. However, the number of dislocations involved in the process increases with etching voltage.