GaN HEMT Devices Research Articles

Scaling of E-mode power GaN-HEMTs for low voltage/low Ron applications: Implications on robustness

We analyze the impact of scaling on the off-state, three-terminal, lateral breakdown of 100 V E-mode p-GaN/AlGaN/GaN HEMTs for low-voltage/low on-resistance applications. To this aim, we compared device structures with different SiO2 dielectric thickness below the field plate, and varying gate-to-drain spacing and field-plate dimensions. The results indicate that: a) the breakdown voltage depends on the geometry and on the thickness of the dielectric under the field plate (tSiO2); b) scaling the dielectric thickness increases the sensitivity of breakdown voltage to the gate-drain distance, while preserving device robustness (breakdown voltages above 150 V for a 100 V technology); c) for the devices with thinner dielectric, breakdown voltage scales linearly with gate drain distance, and with field plate length. A further analysis of the data reveals that the critical parameter in terms of reliability is the distance between the field-plate edge and the drain contact; d) scaling of the dielectric thickness does not enhance charge trapping phenomena. In summary, the results provide guidelines for scaling GaN HEMT device dimensions, while preserving reliability and immunity to charge trapping phenomena.

Novel approach of combined planar and cross-sectional defect analysis of stressed normally-on HEMT devices with leaky Schottky gates

The clear correlation of defect localization by Electroluminescence to nanometer sized defects at Schottky gate contacts of GaN HEMTs are always challenging and limiting the root cause analysis of the stress related electrical degradation of the devices. In this paper a novel approach combining large area planar TEM defect screening followed by cross sectional preparation at identified defect sites is demonstrated to get access to relevant structural damages at the gate. The analysis flow is applied for normally-on GaN HEMT devices with an increased leakage at the Schottky gates observed after electrical stressing. To initiate electrical active degradation these devices were stressed up to significant changes in the electrical performance and then Electroluminescence spots were detected identifying possible defect positions. Metal intrusions into the AlGaN/ GaN stack underneath the Schottky gate contacts of only 20 nm size could be found by the newly combined planar/ cross-sectional analysis flow in good correlation to the EL spot positions. Analytical TEM investigations of the defects reveal Pt and Au inside the semiconductor reaching the 2DEG at a threading dislocation of the HEMT. These intrusions contribute to the gate leakage current and are causing the increased leakage current after electrical testing.

(Invited) Extraction of Trap Level in GaN Hemt from Transient Current upon Back Gate Voltage Application

Gallium nitride (GaN) have attracted attention as a high frequency and high voltage power device material because they have wide bandgap and high mobility [1]. However, large number of defects exists in the epitaxial layer. Current collapse originated from the traps at the surface and in the buffer layer is one of the results of the defects [2]. To distinguish the bulk traps from the whole current collapse, back-gate voltage application is commonly used [3]. In this study, we measured the bulk traps by measuring the drain transient current by back gate voltage application.TLM pattern (L/W=120/100 mm) was fabricated on an epitaxial wafer; GaN(2nm)/AlGaN(26nm)/ GaN(150/350nm)/C-GaN/buffer/Si sub. Fig. 1 shows the I d-V B characteristic of the TLM, where a threshold voltage (V th) of -300/-450 V can be extracted. A large clock-wise hysteresis suggests large amount of electron trapping in the epitaxial layer. Fig. 2(a) shows the voltage application sequence for measuring the transient I d 2DEG current. A negatively high V B below the V th was applied to clear all the traps initially exists in the epitaxial layers. Then, a step voltage was applied to a certain voltage, and the transient I d was monitored until the value saturates. Fig. 2(b) shows typical transient I d on V B. To analyze the time constant (t) of the transient, the differential of the I d on logarithm time was used, as the time at the peak signal corresponds to the time constant. Fig. 3(a) shows analysis result, and the peak of this graph correspond to t. On the other hand, the amplitude is related to trap density. Fig. 3(b) shows the Alenius plot of the extracted t, and activation energy from 0.2 to 0.3 eV was detected.In conclusion, we have measured the transient I d of GaN-HEMT device with a step voltage application to the substrate back gate. From analysis, we extracted defect levels with activation energy of 0.2 to 0.3 eV. The method is useful for characterizing the trap density in the epitaxial layers.[1] T. Mizutani, et al., IEEE Trans Electron Devices, 50, 10, 2015 (2003).[2] G. Meneghesso, et al., IEEE Trans Electron Devices, 53, 12, 2932 (2006).[3] X. Chen, et al., Appl. Phys. Lett., 117, 26, 263501 (2020). Figure 1

Knowledge‐based neural network with Bayesian optimization for efficient nonlinear RF device modeling

AbstractThis paper proposes a novel approach for modeling the nonlinear behavior of microwave devices, with a particular focus on addressing the challenging problem of modeling compound semiconductor transistors under large‐signal excitation. The approach utilizes a knowledge‐based neural network (KBNN) to construct a frequency‐domain behavioral model of the transistor, which maps incident and scattered waves from a coarse model to a fine model in cases where the coarse model fails to match the behavior of a new device. This neural network‐based method aims to achieve better alignment between the extracted model parameters obtained from the coarse model and the behavior of the fine model. To improve mapping efficiency and accuracy, Bayesian optimization techniques are employed to automatically adjust the hyper parameters in the KBNN within a custom‐defined hyper parameter space. The proposed method uses simulation and measurement of a 0.25 um GaN HEMT device operating at 8 GHz, with VGS at −2 V and VDS at 18 V. Furthermore, the proposed model exhibits good interpolation capability at different input power levels, indicating its broad applicability in the design of high‐speed device models. Specifically, the accuracy of the simulation data and test data reached −53.83 and −51.68 dB, respectively, with the test data used in model training being less than 7.5% of the simulation data.

A Thorough Evaluation of GaN HEMT Degradation under Realistic Power Amplifier Operation

In this paper, we experimentally investigate the effects of degradation observed on 0.15-µm GaN HEMT devices when operating under realistic power amplifier conditions. The latter will be applied to the devices under test (DUT) by exploiting a low-frequency load-pull characterization technique that provides information consistent with RF operation, with the advantage of revealing electrical quantities not directly detectable at high frequency. Quantities such as the resistive gate current, play a fundamental role in the analysis of technology reliability. The experiments will be carried out on DUTs of the same periphery considering two different power amplifier operations: a saturated class-AB condition, that emphasizes the degradation effects produced by high temperatures due to power dissipation, and a class-E condition, that enhances the effects of high electric fields. The experiments will be carried out at 30 °C and 100 °C, and the results will be compared to evaluate how a specific RF condition can impact on the device degradation. Such a kind of comparison, to the authors’ knowledge, has never been carried out and represents the main novelty of the present study.

Effect of Field Plate on Device Performance of Wide Bandgap HEMT

Background: Devices with field plates have gained much popularity in high power and high voltage applications. The work done in this paper is related to designing and studying the different DC and RF characteristics of a field plated GaN HEMT. The results obtained were compared with that of non-field plated GaN HEMT. This comparison and study reported the effect of field plate on device performance. Methods: A GaN HEMT device with and without a field plate was designed and simulated in the SILVACO ATLAS TCAD tool. The performance of both the devices was compared in terms of the exhibited DC and RF characteristics in order to study the effect of the field plate on the device. We have also studied the variation in the cut-off frequency and maximum frequency of both the field plate and without field plate GaN HEMT with respect to gate-source voltage. We have further investigated the device performance by varying the length of the field plate from 0 to 2.5 μm. Results: The study reflects the advantageous feature of GaN HEMT with field plate by exhibiting high breakdown voltage of 292 V in comparison to GaN HEMT without field plate which exhibits a breakdown voltage of 98 V. As a result of using field plate in the GaN HEMT structure, a rise in the Cgs and Cgd capacitances are witnessed. This in turn affects the other RF characteristics of the GaN HEMT with field plate even though the GaN HEMT with and without field plate exhibits nearly same DC characteristics. The field plated GaN HEMT exhibits a reduced cut-off frequency and maximum frequency of 7 GHz and 20 GHz, respectively, in comparison to the GaN HEMT without field plate’s cut-off frequency and maximum frequency of 10 GHz and 25 GHz, respectively. Conclusion: The study reports that using a field plate helps in enhancing the breakdown voltage but at the cost of reduced frequency performance. We have compared our proposed field plated device with different non-field plated devices and concluded that our device exhibits much higher breakdown voltage in spite of reduced device dimension. With the attainment of higher breakdown voltage our proposed GaN HEMT device can be used for high power applications. From the study, it is reported that while increasing the length of the field plate the breakdown voltage also increases. For a particular set of device dimensions, an optimum field plate length provides the highest breakdown voltage but increasing the length of the field plate beyond the optimum value results in reduction in breakdown voltage.

Design of a high‐efficiency bandwidth‐enhanced power amplifier based on dual‐paths impedance matching techniques

SummaryIn this brief, we propose a bandwidth‐enhanced dual‐paths impedance matching technique that can effectively match the four preset design frequency points in the operating frequency band to the optimal impedance region provided by a series of inverse continuous modes (SICMs), thus realizing the bandwidth expansion and efficiency improvement of the power amplifier (PA). To verify the proposed design theory, a multi‐octave PA component was designed, fabricated, and measured with a 10‐W GaN HEMT device. The implemented PA exhibits superior performance, with a relative bandwidth of 142.9% in the bandwidth range of 0.55–3.3 GHz. Moreover, the 39.1–42 dBm output power, 60.1%–76.2% drain efficiency (DE), and 9.1–12 dB gain are also achieved in the target band. Based on the simulated and measured results, the effectiveness of the proposed design theory is further confirmed.

Design of a highly efficient 0.6-4.5GHz multioctave bandwidth GaN-HEMT power amplifier

A methodology for designing multioctave high-efficiency power amplifiers (PA) is presented in this letter. The sequential load-pull technique (SLPT) considering the second and third harmonic characteristics is proposed and combined with the multiple frequency matching theory (MFMT) to achieve outstanding performance in terms of operating bandwidth as well as efficiency. To verify the proposed theory, a 10 W GaN HEMT device is used. The proposed PA achieves a fractional bandwidth of 152% from 0.6 to 4.5GHz. In such a wide frequency band, the drain efficiency (DE) is measured as 50%-68% with an output power of greater than 38dBm and a large signal gain greater than 8dB.

Thermal management of GaN HEMT devices using subcooled flow boiling in an embedded manifold microchannel heat sink

Ultra-high heat flux thermal management has been an urgent demand for high electrical performance and reliability of GaN HEMT electronic devices, and direct fabrication of embedded heat sinks have proven to be an effective approach for its thermal management. In this work, a self-developed solver based on OpenFOAM has been employed and verified for numerical investigations of three-dimensional two-phase flow coupled with conjugate heat transfer. An extremely uneven heat source distribution in GaN HEMT is accounted for in the numerical modeling with localized refined mesh. The thermal performance and pressure drop during subcooled flow boiling are investigated and presented considering parametric effects of heat flux, mass velocity, inlet/outlet width ratio, manifold thickness and channel aspect ratio as well as substrate materials. The results indicate that GaN-on-Diamond structure provides a lower thermal resistance and better temperature uniformity, and the superior performance of GaN-on-SiC and GaN-on-Diamond are augmented with increasing heat flux during subcooled flow boiling. Additionally, it can be concluded that maximum temperature and pressure drop decrease with increasing channel height firstly, and then flatten out as the height/width ratio reaches 8 and 6, respectively. The flatten-out relationship between increasing height/width ratio and thermal/hydraulic performance is partly attributed to the balance of decreasing convective heat transfer coefficient and increasing effective area. Besides, flow pattern analysis for high-aspect ratio microchannels shows that hotspots at the bottom of inlet manifold promote the bubble nucleation and bubbles tend to accumulate at the bottom of channels because of nonuniform velocity distribution along the microchannel height.

Highly efficient broadband continuous Class-F power amplifier with a novel harmonic matching network

In this letter, we propose a methodology for designing high efficiency broadband harmonic-controlled power amplifiers (PAs) with a novel harmonic matching network. This network consists of three second-harmonic open circuit microwave lines and three third-harmonic short circuit microwave lines, each corresponding to different wavelengths for different frequencies. It can improve the efficiency and bandwidth of PAs by controlling harmonic match impedance. Through the proposed network, we design and fabricate a highly efficient broadband continuous Class-F PA using a CGH40010F GaN HEMT device. The measurement results show that the drain efficiency of 71.4% to 82.4% (the average efficiency of 76.9%) and output power of 40.4dBm to 42.6dBm are achieved at 1.3GHz-2.5GHz, respectively.

Thermal property evaluation of a 2.5D integration method with device level microchannel direct cooling for a high-power GaN HEMT device

Gallium nitride high electron mobility transistor (GaN HEMT) devices have become critical components in the manufacturing of high-performance radio frequency (RF) or power electronic modules due to their superior characteristics, such as high electron saturation speeds and high power densities. However, the high heat characteristics of GaN HEMTs make device level cooling a critical problem to solve since performance degradation or even failure may occur under high temperatures. In this paper, we proposed a 2.5D integration method with device-level microchannel direct cooling for a high-power GaN HEMT device. To demonstrate this technological concept, a multigate GaN HEMT device featuring a gate length/width/source drain spacing of 0.5 μm/300 μm/6 μm that underwent in-house backside thinning and metallization was used as the test vehicle. A high-resistivity silicon (HR Si) interposer embedded with four-layer microchannels was designed, having widths/pitches of 30 μm/30 μm at the top microchannel. The high-power GaN HEMT device was soldered on a Si interposer embedded with open microchannels for heat dissipation. A pair of GSG Pad chips was soldered simultaneously to display the capacity for the heterogeneous integration of other chip types. Thermal property evaluation was conducted with experiments and simulations. The test results showed that the maximum surface temperature of the GaN HEMT device decreased to 93.8 °C when it experienced a heat dissipation density of 32 kW/cm2 in the gate finger area and an average heat dissipation density of 5 kW/cm2 was found in the active area with the DI water coolant at a flow rate of 3 mL/min. To our knowledge, among recently reported works, this finding was the best cooling capacity of heterogeneously integrated microchannels for GaN HEMT devices. In addition, this technology was scalable regarding the numbers of gate fingers or GaN HEMT devices.

Characterization and modeling of drain lag using a modified RC network in the ASM-HEMT framework

Gallium-Nitride High Electron Mobility Transistors (GaN-HEMTs) are susceptible to trapping effects, significantly degrading device performance. The degradation can be seen in the current–voltage characteristics and also manifests in the form of a shift in the dynamic on-resistance and threshold voltage. In this paper, we present pulsed characterization and empirical modeling of a 250 × 10 μm RF GaN HEMT device. To study the impact of drain-induced trapping, pulse I-V characterization is performed at a fixed quiescent gate voltage of −7 V with varying drain quiescent voltage. An empirical RC network approach is proposed to accurately model the trapping in the device. The model effectively captures the impact of trapping and takes into account the self-limiting behavior of traps. The model is implemented in Verilog-A within the Advanced SPICE Model for High Electron Mobility Transistors (ASM-HEMT) framework. Validation of the model is done with six different quiescent conditions of pulse measurement with on-state drain bias varying from 0 V to 20 V.

Unclamped inductive stressing of GaN and SiC Cascode power devices to failure at elevated temperatures

In this paper, the ruggedness performance of GaN HEMT and SiC JFET devices in cascode configuration with a low voltage silicon power MOSFET has been evaluated experimentally. The impact of the bus voltage on the drain current and avalanche energy are investigated as well as the temperature sweep to enable analysis of the alternation of these parameters on the Unclamped Inductive Switching (UIS) ruggedness of cascode devices. The experimental measurements show that the GaN cascode devices have lower avalanche energy rating when compared with the closely rated SiC cascode devices just before the failure. SiC cascode devices can also withstand higher bus voltage in comparison to GaN cascode devices when under electrothermal stress by unclamped inductive switching. The analysis of transfer characteristics and leakage current of SiC JFET & GaN HEMT cascode structures following UIS stress have also been performed together with Computed Tomography (CT) Scan imaging to determine the per-area avalanche energy density.

Improvement and Reduction of Self-Heating Effect in AlGaN/GaN HEMT Devices

GaN is one of the third-generation broadband semiconductor materials developed rapidly in recent years, and Algan/GanHEMT has a broad application prospect in the fields of high temperature, high power, high frequency and radiation resistance, etc. In recent years, gallium nitride based high electron mobility transistors have been widely used in emerging industries, such as 5G technology, new energy vehicles, unmanned aircraft and other fields, due to their high power and high voltage resistance. However, due to the high power density of HEMT devices, the self-heating effect will lead to a significant increase in the junction temperature of the device, which will seriously affect the performance, reliability, and lifetime of the device. In this paper, the temperature characteristics of GaN high electron mobility transistors (GaN HEMTs) are studied, and the effect of self-heating effect on GaN HEMT devices is analyzed. In order to reduce the device temperature and improve the reliability of the device, a new device structure is proposed in this paper. The new structure replaces the conventional silicon and Si3N4 with highly thermally conductive diamond and SiC as the substrate and passivation layer of the device, which facilitates the heat dissipation from the substrate and passivation layer. Also, the new structure employs a hybrid barrier layer and field plate. Simulation results show that the new structure has about 30% lower temperature peak, 47% higher output current, 28% higher transconductivity, and up to 18.22% higher current collapse rate compared to the conventional structure.

Ultra-Wideband Power Amplifier Design Strategy for 5G Sub-6-GHz Applications.

This paper presents a strategy to design ultrawideband power amplifiers with a fractional bandwidth of approximately 200%. It exploits a simple output matching network, which consists of a series transmission line together with a shunt stub, to compensate the output parasitic network of the device. Following this, a multisection transformer is implemented to obtain the optimal load at the intrinsic drain plane. As design examples, several output matching networks were designed for two different size GaN HEMT devices. One of these examples was implemented and characterized, and a drain efficiency from 52% to 70% and an output power between 40 dBm and 42.5 dBm were obtained, over 67% of the 5G sub-6-GHz band (i.e., 0.1 to 4 GHz). The aforementioned results, to the best of the authors’ knowledge, represent the state of the art in broadband power amplifiers.

Hybrid small-signal modeling of GaN HEMTs based on improved genetic algorithm

—In this paper, an improved genetic algorithm-based hybrid direct-optimal extraction method for small-signal model of GaN HEMT devices is proposed. Simulated annealing algorithm and fuzzy adaptive strategy are incorporated into genetic algorithm for model parameter optimization, to overcome the shortcoming of conventional genetic algorithm that tend to fall into local optimum solutions. The validity of proposed algorithm is verified by using a 20-element GaN HEMT small-signal equivalent circuit model under different operating conditions. The results show that the modeled S-parameters agree well with the measured S-parameters in the frequency range of 0.5–20.5 GHz.

Analysis and improvement of self-heating effect based on GaN HEMT devices

Gallium nitride high electron mobility transistor (GaN HEMT) applications in high-power and high-frequency environments can lead to high device temperatures due to the self-heating effect, thus limiting device performance and reliability. In order to address this problem, this paper changes the material and structure of the device. It successfully reduces the maximum temperature of the device to 335 K by using a new structure of the diamond substrate, diamond heat sink layer, and InGaN insertion layer. Simulation results show that the new structure has a 35% reduction in maximum temperature, a 61% increase in current, a 37% improvement in maximum transconductance, and a 35% improvement in current collapse. At the same time, the new structure also improves the electron mobility of the channel.

A Doherty Power Amplifier With Extended High-Efficiency Range Using Three-Port Harmonic Injection Network

In this paper, a Doherty power amplifier (DPA) using a novel three-port harmonic injection network (HIN) to extend its high-efficiency range is proposed. With the help of a part of the three-port HIN, which is placed between the carrier and peaking branches, the optimal drain fundamental frequency termination for the carrier device at back-off and saturation can be realized simultaneously thus enhancing the efficiency at back-off significantly. Meanwhile, this three-port HIN can also realize second harmonic drain terminations for the carrier and peaking device with the quasi-open and quasi-short circuit at the current plane, respectively. Consequently, the saturated power ratio between peaking and carrier devices is increased, which further extends the back-off range of the asymmetric drain-biased DPA. For demonstration purposes, an extended high efficiency range DPA was designed and fabricated using commercially available GaN HEMT (Cree CGH 40010F) devices. Measured results for this novel idea gave drain efficiencies better than 62.5% at 9-9.5 dB back-off point from 1.60 to 1.95 GHz.

Circuit Models of Power MOSFETs Leading the Way of GaN HEMT Modelling—A Review

Gallium nitride high-electron-mobility transistor (GaN HEMT) is a key enabling technology for obtaining high-efficient and compact power electronic systems. At the design stage of a power converter, the proper modelling of the GaN HEMT is essential to benefit from their good features and to account for the limits of the current technology. Circuit models of power MOSFETs have been deeply investigated by academia and industry for a long time. These models are able to emulate the datasheet information, and they are usually provided by device manufacturers as netlists that can be simulated in any kind of SPICE-like software. This paper firstly highlights the similarities and differences between MOSFETs and GaN HEMTs at the datasheet level. According to this analysis, the features of MOSFET circuit models that can be adopted for GaN HEMT modelling are discussed. This task has been accomplished by overviewing the literature on MOSFETs circuit models as well as analysing manufacturers netlists, thus highlighting the models MOSFETs valid or adaptable to GaN HEMTs. The study has revealed show that some models can be adapted for the GaN HEMT devices to emulate static characteristics at room temperature while the MOSFET models of dynamic characteristics can be used for GaN HEMT devices. This study enables the devices modellers to speed up the GaN HEMT modelling thanks to the use of some well-established MOSFET models. In this perspective, some suggestions to develop accurate GaN HEMT models are also provided.

Impact of Gamma Radiations on Static, Pulsed I–V, and RF Performance Parameters of AlGaN/GaN HEMT

In this article, the impact of gamma (<inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>) irradiation on passivated and unpassivated AlGaN/GaN HEMT is presented in detail. Passivated and unpassivated GaN-HEMT devices have been exposed to <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-radiations to a total dose of 10 kGy. Post-<inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-irradiation, a refinement in ohmic contact, which makes device source/drain, is recorded. Alteration in Schottky gate electrical characteristics (<inline-formula> <tex-math notation="LaTeX">${C} - {V}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${I}\!\!-\!\!{V}$ </tex-math></inline-formula>) along with advances in device drain current and transconductance has been observed in unpassivated HEMT, while it remained almost unaltered in passivated GaN-HEMT after <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-irradiation. The OFF-state gate leakage has deterioration in both types of HEMTs, suggesting a modification in trap concentration beneath the gate and near gate region during <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-exposure. This is confirmed via pulsed <inline-formula> <tex-math notation="LaTeX">${I}\!-\!{V}$ </tex-math></inline-formula> measurements. A strong upswing in drain current recovery after stress bias is recorded post-<inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-irradiation in both types of HEMTs. This confirms that the trapping sites have been altered during <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-exposure. Possible reasons causing this modification are improvement in gate metal barrier inhomogeneities and reduction/rearrangement of crystal defects during <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula> <i>-exposure</i>. The effect of <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-radiation on intrinsic/extrinsic device parameters has also been determined using S-parameters measurements. Intrinsic/extrinsic device parameters of passivated HEMT are observed to be less affected by <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-irradiation in comparison to unpassivated GaN-HEMT devices, and post-radiation, both the devices have similar device parameters values as it was prior radiation making it suitable for harsh environment applications.