GaN-based Heterostructure Field-effect Transistors Research Articles

Novel GaN-based double-channel p-heterostructure field-effect transistors with a p-GaN insertion layer

GaN-based p-channel heterostructure field-effect transistors (p-HFETs) face significant constraints on on-state currents compared with n-channel high electron mobility transistors. In this work, we propose a novel double heterostructure which introduces an additional p-GaN insertion layer into traditional p-HFETs. The impact of the device structure on the hole densities and valence band energies of both the upper and lower channels is analyzed by using Silvaco TACD simulations, including the thickness of the upper AlGaN layer and the doping impurities and concentration in the GaN buffer layer, as well as the thickness and Mg-doping concentration in the p-GaN insertion layer. With the help of the p-GaN insertion layer, the C-doping concentration in the GaN buffer layer can be reduced, while the density of the two-dimensional hole gas in the lower channel is enhanced at the same time. This work suggests that a double heterostructure with a p-GaN insertion layer is a better approach to improve p-HFETs compared with those devices with C-doped buffer layer alone.

Low specific on-resistance GaN-based vertical heterostructure field effect transistors with nonuniform doping superjunctions**Project supported by the National Natural Science Foundation of China (Grant Nos. 61574112, 61334002, 61474091, and 61574110) and the Natural Science Basic Research Plan in Shaanxi Province, China (Grant No. 605119425012).

A novel GaN-based vertical heterostructure field effect transistor (HFET) with nonuniform doping superjunctions (non-SJ HFET) is proposed and studied by Silvaco-ATLAS, for minimizing the specific on-resistance (RonA) at no expense of breakdown voltage (BV). The feature of non-SJ HFET lies in the nonuniform doping concentration from top to bottom in the n- and p-pillars, which is different from that of the conventional GaN-based vertical HFET with uniform doping superjunctions (un-SJ HFET). A physically intrinsic mechanism for the nonuniform doping superjunction (non-SJ) to further reduce RonA at no expense of BV is investigated and revealed in detail. The design, related to the structure parameters of non-SJ, is optimized to minimize the RonA on the basis of the same BV as that of un-SJ HFET. Optimized simulation results show that the reduction in RonA depends on the doping concentrations and thickness values of the light and heavy doping parts in non-SJ. The maximum reduction of more than 51% in RonA could be achieved with a BV of 1890 V. These results could demonstrate the superiority of non-SJ HFET in minimizing RonA and provide a useful reference for further developing the GaN-based vertical HFETs.

Formation mechanism of gold-based and gold-free ohmic contacts to AlGaN/GaN heterostructure field effect transistors

To better understand the formation mechanism of ohmic contacts to GaN-based heterostructure field effect transistors, we have compared in detail Ti/Al/Ti/Au and Ti/Al/Ti/TiN contacts. Transmission electron microscopy and electron dispersive X-ray spectroscopy revealed that following anneal, TiN islands penetrated through the AlGaN barrier, as already well known, in the gold-based ohmic contacts but not in the gold-free contacts. We hence conclude that gold facilitates the formation of the TiN islands and propose that the role of gold is extraction of gallium from the semiconductor, providing a gallium depleted region for TiN island formation. For the case of the gold-free contacts, a 8 nm thick semi continuous TiN layer was formed following 900 °C anneal. A 2 nm thick TiN layer was observed in the as deposited samples and remained intact after anneal up to 825 °C. The different ohmic contact formation mechanism of gold-based and gold-free contacts is also manifested by our finding that a discontinuous AlN nitride spacer layer between the barrier and the bulk may lead to non-uniformity in contact behavior across the wafer in the case of gold-free contacts. For gold-based contacts, ohmic contact behavior was uniform across the wafer.

Temperature-induced instability of the threshold voltage in GaN-based heterostructure field-effect transistors

Temperature-induced instability of the threshold voltage in GaN-based heterostructure field-effect transistors (HFETs) and Al2O3– and ZrO2–based metal-oxide-semiconductor (MOS) HFETs was investigated and their trapping effects were analyzed. A negative or positive threshold voltage shift was observed in the HFETs with a AlGaN or InAlN barrier, which indicates that electron or hole traps dominate in the barriers. A temperature dependence of the threshold voltage in the MOSHFETs exhibited two different regions. At lower temperatures, similarly as in the HFETs, traps in the barrier dominated. However, at temperatures above 100−150 °C the threshold voltage shift was more pronounced and connected with the oxide/insulator interface traps. The threshold voltage shift can be negative or positive if a Al2O3 or ZrO2 gate insulator, respectively, is used. The results show that the temperature dependence of the threshold voltage can be controlled by the barrier layer composition and/or the gate insulator type.

Novel GaN-based vertical heterostructure field effect transistor structures using crystallographic KOH etching and overgrowth

A novel V-groove vertical heterostructure field effect transistor structure is proposed using semi-polar (11-22) GaN. A crystallographic potassium hydroxide self-limiting wet etching technique was developed to enable a damage-free V-groove etching process. An AlGaN/GaN HFET structure was successfully regrown by molecular beam epitaxy on the V-groove surface. A smooth AlGaN/GaN interface was achieved which is an essential requirement for the formation of a high mobility channel.

Design optimization of a high-breakdown-voltage GaN-based vertical HFET with composite current-blocking layer

This work proposes a GaN-based vertical heterostructure field-effect transistor with composite insulated current-blocking layer (GaN CCBL-VHFET) to improve the breakdown voltage (BV) of the current aperture vertical electron transistor (CAVET) and obtain high CBL performance. When utilizing a composite current-blocking layer, the electric field (E-field) discontinuity at the CBL/low-k dielectric interface results in a more uniform E-field distribution along the GaN buffer layer, significantly improving the BV. Simulation results show that the BV and ON-resistance ($$R_{\mathrm{ON}}$$RON) of the device with two low-k dielectric layers are 1744 V and 0.91 m$$\Omega \,\mathrm{cm}^{2}$$Ωcm2, respectively. Furthermore, the average breakdown E-field is extremely high, reaching 291 V/$${\upmu }$$μm. Compared with the conventional GaN CAVET, the BV of the GaN CCBL-VHFET increases by about 94 % while retaining low $$R_{\mathrm{ON}}$$RON. Furthermore, the challenge of activating Mg in the CBL is avoided for this device structure.

Deep Trap Levels Responsible for Current Collapse in AlGaN/GaN MISHFET

GaN-based heterostructure field-effect transistors (HFETs) have been attracted considerably as candidates for next-generation devices for both high-power and high frequency applications, because of its excellent material properties such as high breakdown field, high polarization-induced two dimensional electron gas (2DEG) and high saturated electron velocity [1-3]. Despite the advantages, current collapse has been concerned for reliability of AlGaN/GaN HFETs. In this work, we investigated origins of the current collapse in AlGaN/GaN MISHFETs after negative gate bias by observing the spectral photo-responsive drain current and gate-drain spacing dependent effect. Schematic structure of the fabricated MISHFETs is shown in Fig. 1(a), in which the epitaxial layers were grown on the sapphire (0001) substrate by MOCVD. After mesa isolation by TCP-RIE, a 5 nm-thick Al2O3 layer was deposited using PAALD. Si/Ti/Al/Ni/Au (1/25/10/40/100 nm) were deposited for ohmic metal stacks by e-beam evaporator and rapid thermal annealing (RTA) was performed at 850 ˚C for 30 s in N2flow. Subsequently, Ni/Au (40/50 nm) was deposited as the schottky gate contacts. The defined gate length and width of the fabricated devices were 3 μm and 50 μm, respectively. Fig 1(b) shows typical output characteristics of the fabricated MISHFET. Fig. 2 shows the drain currents measured before and after the bias stress when the monochrome lights of different energy were illuminated. Under the illumination condition, it showed only slight collapses of drain current for 500 ~ 600 nm light after the negative bias stress, while showed serious collapse for the other wavelengths. It means that the photons with energy of 2.25 eV was effective to excite the electrons trapped by the deep level which was attributable to the current collapse due to the negative gate bias. This trap energy might be related to the Ga vacancy in GaN bulk layer as widely known as a culprit in previous researches in AlGaN/GaN HFET [4]. Fig. 3 shows a schematic band diagram for the current collapse caused by a negative bias stress. When a high negative bias stress is applied to the gate, the energy band near AlGaN/GaN junction will be bended and the electrons be released from crystal interface which have been trapped in acceptor like states such as Ga vacancy levels as shown in Fig. 3 (a). Fig. 4 shows the drain current suppression at a bias condition of Vgs=1 V and Vds=7V after negative bias stress of -20 V, in which the current decreases as the gate-drain spacing increases. For wide gate-drain spacing, even the electric field between gate and drain decreases, more states seemed to be exposed and contributed to the current collapse at the AlGaN or GaN layer. In conclusion, the current collapse in AlGaN/GaN MISHFET was significant for the wide gate-drain spacing. The photons with energy of 2.25 eV was effective to excite the electrons trapped by the deep levels which were attributed to the current collapse induced by the negative gate bias. This trap energy might be related to the Ga vacancy in GaN bulk layer. Reference [1] P. Waltereit, W. Bronner, R. Quay, M. Dammann, R. Kiefer, S. Müller, M. Musser, J. Kühn, F. van Raay, M. Seelmann, M. Mikulla, O. Ambacher, F. van Rijs, T. Rödle, and K. Riepe, “GaN HEMT and MMIC development at Fraunhofer IAF: performance and reliability,” phys. Status Solidi A, vol. 206, pp. 1215-1220, 2009. [2] D. S. Kim, K. S. Im, K. W. Kim, H. S. Kang, D. K. Kim, S. J. Chang, Y. Bae, S. H. Hahm, S. Cristoloveanu, and J. H. Lee, “Normally-off GaN MOSFETs on insulating substrate,” Solid-State Electron., vol. 90, pp. 79-85, 2013. [3] S. T. Sheppard, K. Doverspike, W. L. Probble, S. T. Allen, J. W. Palmour, L. T. Kehias, and T. J. Jenkins, “High-power microwave GaN/AlGaN HEMTs on semi-insulating silicon carbide substrates,” IEEE Electron Device Lett., vol. 20, pp. 161-163, 1999. [4] J. Neugebauer and C. G. Van de Walle, “Gallium vacancies and the yellow luminescence in GaN,” Appl. Phys. Lett., vol. 69, pp. 503-505, 1996. Figure 1

The III-Nitride Double Heterostructure Revisited: Benefits for Threshold Voltage Engineering of MIS Devices

GaN-based devices are seen as ideal candidates for power-switching applications. For the acceptance of GaN-based devices by module designers, obtaining enhancement-mode (e-mode) behavior in GaN-based heterostructure field-effect transistors (HFETs) has long been in the focus. Although the gate-injection approach appears to be the most promising one to achieve e-mode devices, using a double heterostructure in conjunction with a gate insulator has still its advantages, such as steeper turn-ON characteristics and lower leakage currents. An analytical expression to predict the threshold voltage $V_{\mathrm {th}}$ for a given double heterostructure device has not yet been derived. Moreover, neither an evaluation of the tradeoff between $V_{\mathrm {th}}$ and ON-state resistance $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}}$ has been performed to date. This paper addresses these two aspects. We will show an analytical expression for a metal–insulator–semiconductor double HFET (MIS-DHFET), which in certain cases is also valid for the gate-injection transistor. On the basis of this, we will discuss the actual influence of the Al concentration in the backbarrier on $V_{\mathrm {th}}$ . We will further employ technology computer aided design (TCAD) device simulations to evaluate the impact on $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}}$ when using MIS-DHFETs. It will be shown that by implementing a double heterostructure in MIS devices, it is possible to suppress the typically observed negative $V_{\mathrm {th}}$ –oxide thickness relationship while maintaining a constant $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}}$ .

Charge movement in a GaN-based hetero-structure field effect transistor structure with carbon doped buffer under applied substrate bias

Charge trapping and transport in the carbon doped GaN buffer of a GaN-based hetero-structure field effect transistor (HFET) has been investigated under both positive and negative substrate bias. Clear evidence of redistribution of charges in the carbon doped region by thermally generated holes is seen, with electron injection and capture observed during positive bias. Excellent agreement is found with simulations. It is shown that these effects are intrinsic to the carbon doped GaN and need to be controlled to provide reliable and efficient GaN-based power HFETs.

Design of high breakdown voltage GaN-based vertical HFETs with p-GaN island structure for power applications

In order to achieve higher breakdown voltage (BV) and low on-resistance (RON), a GaN-based vertical heterostructure field effect transistor with p-GaN islands (GaN PI-VHFET) is proposed in this paper. By introducing the p-GaN islands, the electric field distribution along the buffer layer could be optimized obviously and the breakdown voltage of the GaN-based PI-VHFETs could be improved significantly compared with the conventional GaN devices. Moreover, the GaN PI-VHFET shows greatly advantages of the trade-off between RON and BV. Simulation results show that the breakdown voltage and on-resistance of the device with a p-GaN island are 3188V and 2.79mΩcm2, respectively. And the average breakdown electric field reaches as high as 212.5V/μm. Compared with the typical GaN vertical heterostructure FETs without p-GaN islands, the breakdown voltage increases more than 50% while on-resistance keeps low.

Simulation study of GaN-based HFETs with graded AlGaN barrier

GaN-based heterostructure field-effect-transistors (HFETs) with graded AlGaN barrier, in which the Al mole fraction of AlxGa1−xN ranges from 0 to a certain value (e.g. 35%), demonstrated the potential for high-linearity applications. Based on the two-dimensional (2-D) device simulations, in this paper the trapping effects and current collapse in GaN-based HFETs with graded AlGaN barrier are investigated and analyzed. First, both the carrier profile and direct current (DC) characteristics of the device are obtained for calibration of the simulation model, and the simulation results matched the experimental measurement data very well. In addition, the transient responses of GaN-based HFETs with graded AlGaN barrier are simulated to study the trapping behaviors. As the time increases, two rising trends are observed for the transient current, which are caused by the bulk acceptor traps and surface donor traps, respectively. By comparing with the conventional GaN-based HEMT, the results show that the HFET with graded AlGaN barrier has better immunity to the surface traps, leading to smaller current collapse.

Novel high-current density GaN-based normally off transistor with tensile-strained quaternary InAlGaN barrier

A GaN-based normally off heterostructure field effect transistor (HFET) with high current density and with a quaternary InAlGaN barrier instead of an AlGaN barrier is investigated. It is difficult to obtain both high-current operation and normally off operation in the GaN-based HFET because of the need to control the polarization-induced charge. In order to obtain a normally off operation using quaternary InAlGaN barrier, the InAlGaN barrier is selectively removed and the p-AlGaN layer is formed as the gate electrode. The obtained threshold voltage of the InAlGaN-based HFET is +1.1 V. The maximum drain current reaches as high as 0.73 A/mm, which is almost twice that of a conventional AlGaN-based normally off gate injection transistor (GIT).

Charge balancing in GaN-based 2-D electron gas devices employing an additional 2-D hole gas and its influence on dynamic behaviour of GaN-based heterostructure field effect transistors

GaN-based heterostructure FETs (HFETs) featuring a 2-D electron gas (2DEG) can offer very attractive device performance for power-switching applications. This performance can be assessed by evaluation of the dynamic on-resistance Ron,dyn vs. the breakdown voltage Vbd. In literature, it has been shown that with a high Vbd, Ron,dyn is deteriorated. The impairment of Ron,dyn is mainly driven by electron injection into surface, barrier, and buffer traps. Electron injection itself depends on the electric field which typically peaks at the gate edge towards the drain. A concept suitable to circumvent this issue is the charge-balancing concept which employs a 2-D hole gas (2DHG) on top of the 2DEG allowing for the electric field peak to be suppressed. Furthermore, the 2DEG concentration in the active channel cannot decrease by a change of the surface potential. Hence, beside an improvement in breakdown voltage, also an improvement in dynamic behaviour can be expected. Whereas the first aspect has already been demonstrated, the second one has not been under investigation so far. Hence, in this report, the effect of charge-balancing is discussed and its impact on the dynamic characteristics of HFETs is evaluated. It will be shown that with appropriate device design, the dynamic behaviour of HFETs can be improved by inserting an additional 2DHG.

First Small-Signal Data of GaN-Based p-Channel Heterostructure Field Effect Transistors

p-Channel heterostructure field effect transistors (HFETs) have recently attracted increasing interest. They open up the possibility of fabricating nitride-based low-power complementary logic for operation in environments not accessible to other semiconductors. To date, several publications have dealt with DC data of p-channel GaN-based HFETs. However, small-signal data, which is important in terms of accessible operation frequencies, is missing. In this brief note, we report for the first time the small-signal characteristics and cut-off frequencies of a p-channel device.

AlN barrier HFETs with AlGaN channels to shift the threshold voltage to higher positive values: a proposal

The need for efficient power converters is currently a major driver of GaN-on-Si research activities. Among several areas, a large research field is the engineering of enhancement mode devices. Several solutions have been provided in the past. Yet, almost all solutions either lack the compatibility with epitaxy on Si substrates (which is a necessity in terms of cost) or suffer from low positive threshold voltages (Vth) below +1 V. In power applications, there is definitely a need for higher values of Vth. In this paper, we propose the utilization of AlN barriers in conjunction with AlGaN channels to obtain Vth values of more than +3 V while still maintaining the low power-switching losses obtained in GaN-based heterostructure field-effect transistors.

Electron density window for best frequency performance, lowest phase noise and slowest degradation of GaN heterostructure field-effect transistors

The problems in the realm of nitride heterostructure field-effect transistors (HFETs) are discussed in terms of a novel fluctuation–dissipation-based approach impelled by a recent demonstration of strong correlation of hot-electron fluctuations with frequency performance and degradation of the devices. The correlation has its genesis in the dissipation of the LO-mode heat accumulated by the non-equilibrium longitudinal optical phonons (hot phonons) confined in the channel that hosts the high-density hot-electron gas subjected to a high electric field. The LO-mode heat causes additional scattering of hot electrons and facilitates defect formation in a different manner than the conventional heat contained mainly in the acoustic phonon mode. We treat the heat dissipation problem in terms of the hot-phonon lifetime responsible for the conversion of the non-migrant hot phonons into migrant acoustic modes and other vibrations. The lifetime is measured over a wide range of electron density and supplied electric power. The optimal conditions for the dissipation of the LO-mode heat are associated with the plasmon-assisted disintegration of hot phonons. Signatures of plasmons are experimentally resolved in fluctuations, dissipation, hot-electron transport, transistor frequency performance, transistor phase noise and transistor reliability. In particular, a slower degradation and a faster operation of GaN-based HFETs take place inside the electron density window where the resonant plasmon-assisted ultrafast dissipation of the LO-mode heat comes into play. A novel heterostructure design for the possible improvement of HFET performance is proposed, implemented and tested.

Gate leakage current in GaN-based mesa- and planar-type heterostructure field-effect transistors

The excessive gate leakage current of the planar- and mesa-type InAlN/GaN heterostructure field-effect transistors (HFETs) is evaluated. It is found that the gate current of the mesa-type HFETs is higher than that of the planar devices, particularly at low biases. Analyses of the gate current considering different transport mechanisms yielded identical thermionic currents (i.e., an identical Schottky barrier height) but a significantly higher leakage component in the mesa-type HFETs than in the planar devices. This additional current component observed in the mesa-type devices shows a nearly ohmic behavior. Mapping by the electron-beam induced current technique confirms an enhanced current located under the expanded gate contact and on the part of the mesa-sidewall, where the gate contact is placed. Two-dimensional simulation of the device structure shows that considerable part of the gate leakage current flows through the GaN buffer layer. These results underline the importance of a proper design of the device structure and layout (i.e., the use of planar structure with device insulation prepared by ion implantation rather than by mesa technique), and of the preparation of the GaN buffer (it should be semi-insulating) in order to fabricate reliable, low leakage current GaN-based HFETs.

Ultrafast decay of hot phonons in an AlGaN/AlN/AlGaN/GaN camelback channel

A bottleneck for heat dissipation from the channel of a GaN-based heterostructure field-effect transistor is treated in terms of the lifetime of nonequilibrium (hot) longitudinal optical phonons, which are responsible for additional scattering of electrons in the voltage-biased quasi-two-dimensional channel. The hot-phonon lifetime is measured for an Al0.33Ga0.67N/AlN/Al0.1Ga0.9N/GaN heterostructure where the mobile electrons are spread in a composite Al0.1Ga0.9N/GaN channel and form a camelback electron density profile at high electric fields. In accordance with plasmon-assisted hot-phonon decay, the parameter of importance for the lifetime is not the total charge in the channel (the electron sheet density) but rather the electron density profile. This is demonstrated by comparing two structures with equal sheet densities (1 × 1013 cm−2), but with different density profiles. The camelback channel profile exhibits a shorter hot-phonon lifetime of ∼270 fs as compared with ∼500 fs reported for a standard Al0.33Ga0.67N/AlN/GaN channel at low supplied power levels. When supplied power is sufficient to heat the electrons > 600 K, ultrafast decay of hot phonons is observed in the case of the composite channel structure. In this case, the electron density profile spreads to form a camelback profile, and hot-phonon lifetime reduces to ∼50 fs.

AlGaN/GaN/GaN:C Back-Barrier HFETs With Breakdown Voltage of Over 1 kV and Low $R_{\scriptscriptstyle{\rm ON}} \times A$

A systematic study of GaN-based heterostructure field-effect transistors with an insulating carbon-doped GaN back barrier for high-voltage operation is presented. The impact of variations of carbon doping concentration, GaN channel thickness, and substrates is evaluated. Tradeoff considerations in on-state resistance versus current collapse are addressed. Suppression of the off-state subthreshold drain-leakage currents enables a breakdown voltage enhancement of over 1000 V with a low on-state resistance. Devices with a 5-μm gate-drain separation on semi-insulating SiC and a 7-μm gate-drain separation on n-SiC exhibit 938 V and 0.39 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 942 V and 0.39 m Ω·cmcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. A power device figure of merit of ~ 2.3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Ω·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was calculated for these devices.

Analytical Modeling of Current Collapse in AlGaN/GaN HFETs According to the Virtual Gate Concept

GaN-based heterostructure field effect transistors (HFETs) have gained considerable attention in high-power microwave applications. So far, unsurpassed current levels and high output power at microwave frequencies have been achieved. However, the dominant factors limiting the reliability of these devices under high-power operation are still unsettled. Drain current collapse is one of the major encumbrances in the development of reliable high-power devices in this technology. In this paper, an accurate and versatile analytical model based on the concept of virtual gate formation due to the existence of acceptor-type surface states is developed to model the current-collapse phenomenon. The presented model is considerably simple, and at the same time, it is more precise than the other analytical models previously proposed in literature. The implementation of this analytical model demonstrates superb agreement with the experimental observations of permanent/semipermanent current collapse in AlGaN/GaN HFETs. To demonstrate the versatility, results of this model are also compared with an existing recently developed analytical model of comparable degree of complexity.