Gallium Zinc Oxide Thin-film Transistors Research Articles

Illuminating Trap Density Trends in Amorphous Oxide Semiconductors with Ultrabroadband Photoconduction

AbstractUnder varying growth and device processing conditions, ultrabroadband photoconduction (UBPC) reveals strongly evolving trends in the defect density of states (DoS) for amorphous oxide semiconductor thin‐film transistors (TFTs). Spanning the wide bandgap of amorphous InGaZnOx (a‐IGZO), UBPC identifies seven oxygen deep donor vacancy peaks that are independently confirmed by energetically matching to photoluminescence emission peaks. The subgap DoS from 15 different types of a‐IGZO TFTs all yield similar DoS, except only back‐channel etch TFTs can have a deep acceptor peak seen at 2.2 eV below the conduction band mobility edge. This deep acceptor is likely a zinc vacancy, evidenced by trap density which becomes 5‐6× larger when TFT wet‐etch methods are employed. Certain DoS peaks are strongly enhanced for TFTs with active channel processing damage caused from plasma exposure. While Ar implantation and He plasma processing damage are similar, Ar plasma yields more disorder showing a ≈2 × larger valence‐band Urbach energy, and two orders of magnitude increase in the deep oxygen vacancy trap density. Changing the growth conditions of a‐IGZO also impacts the DoS, with zinc‐rich TFTs showing much poorer electrical performance compared to 1:1:1 molar ratio a‐IGZO TFTs owing to the former having a ∼10 × larger oxygen vacancy trap density. Finally, hydrogen is found to behave as a donor in amorphous indium tin gallium zinc oxide TFTs.

Performance of Transparent Indium–Gallium–Zinc Oxide Thin Film Transistor Prepared by All Plasma Enhanced Atomic Layer Deposition

Transparent indium–gallium–zinc oxide thin film transistor (IGZO-TFT) prepared by all plasma enhanced atomic layer deposition (PEALD) has been firstly investigated. As the chemical composition has a considerable impact on the performance of IGZO TFTs, the properties of IGZO film and IGZO-TFT based on different In2O3 cycle ratios are investigated. The IGZO film prepared by PEALD shows amorphous state with excellent conformity and uniformity. Moreover, the a-IGZO films with different In2O3 cycle ratios are applied to TFT fabrication. When the a-IGZO thin film with 35% In2O3 cycle ratios, the transistor presents satisfactory electrical performance with a threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula> ) of 1.7 V, a saturation mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {sat}}$ </tex-math></inline-formula> ) of 8.8 cm2/Vs, a subthreshold swing (SS) of 0.2 V/decade and an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{ON}/\text{I}_{OFF}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.2\times 10^{{8}}$ </tex-math></inline-formula> . This work provides a new way to achieve transparent TFT which better for practical commercial applications.

Fully Transparent and Highly Sensitive pH Sensor Based on an a-IGZO Thin-Film Transistor with Coplanar Dual-Gate on Flexible Polyimide Substrates

In this paper, we propose a fully transparent and flexible high-performance pH sensor based on an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) transducer with a coplanar dual-gate structure on polyimide substrates. The proposed pH sensor system features a transducer unit consisting of a floating gate (FG), sensing gate (SG), and control gate (CG) on a polyimide (PI), and an extended gate (EG) sensing unit on a separate glass substrate. We designed a capacitive coupling between (SG) and (CG) through the FG of an a-IGZO TFT transducer to contribute to sensitivity amplification. The capacitance ratio (CSG/CCG) increases linearly with the area ratio; therefore, the amplification ratio of the pH sensitivity was easily controlled using the area ratio of SG/CG. The proposed sensor system improved the pH sensitivity by up to 359.28 mV/pH (CSG/CCG = 6.16) at room temperature (300 K), which is significantly larger than the Nernstian limit of 59.14 mV/pH. In addition, the non-ideal behavior, including hysteresis and drift effects, was evaluated to ensure stability and reliability. The amplification of sensitivity based on capacitive coupling was much higher than the increase in the hysteresis voltage and drift rate. Furthermore, we verified the flexibility of the a-IGZO coplanar dual-gate TFT transducer through a bending test, and the electrical properties were maintained without mechanical damage, even after repeated bending. Therefore, the proposed fully transparent and highly sensitive a-IGZO coplanar dual-gate TFT-based pH sensor could be a promising wearable and portable high-performance chemical sensor platform.

A-IGZO thin-film transistors with transparent ultrathin Al/Ag bilayer source and drain for active neural interfaces

Electro-optical neural interface technologies based on transparent electronics have been developed to take advantage of both high spatial resolution of optical cellular imaging by microscopes and high temporal resolution of electrical neural recordings. Recently, active-matrix systems based on amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) have been suggested for high-density electrical neural recordings owing to the high mobility and optical transparency of the IGZO. However, conventional metallic source and drain electrodes forming ohmic contacts with the a-IGZO are the limiting factors of the overall system transparency because the electrodes have substantial portions in the TFT structures. In this work, we propose an ultrathin metal bilayer as the transparent source and drain electrodes of the a-IGZO TFTs for fully transparent TFT-based electro-optical neural interfaces. The ultrathin metal bilayer electrodes consist of 2.5–4.5 nm-thick aluminum as a seed layer and 8 nm-thick silver. The ultrathin Al/Ag bilayer suppressed localized surface plasmonic resonance, showing 40–70% of transmittance in the range of 350–700 nm and thus allowing us to observe cultured neurons through the transparent electrodes. We also confirmed that the ultrathin Al/Ag electrodes form decent ohmic contacts to the IGZO, showing width-normalized contact resistance of 2.9 kΩ-cm which is similar to the previously reported other transparent S/D electrodes. The a-IGZO TFTs with the ultrathin Al/Ag showed the highest linear mobility of 3.9 cm2/Vs of in long channels and 0.2–0.64 cm2/Vs in short channels. The gate-bias normalized cut-off frequency was 8–26 kHz/V at Lch = 20 μm, which would be sufficient for recording a wide range of neural signals.

Physics-based 2D analytical potential model with disorder effects for scaling a-IGZO TFT via dual material gate engineering

A dual material gate (DMG) amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) is proposed, which has a gate structure of lateral-contact-metals with two work functions. In view of multiple gate materials and localized/delocalized states, the potential calculations using Poisson’s equation are complicated and without analytical solution, which complicates the gate controllability analysis and future compact modeling methodology. Therefore, we have developed an analytical 2D potential model, that shows a great agreement with the numerical solution, taking into account asymmetry effects and scaling behavior. It can be used to tune potential or electric-field profiles by DMG engineering, increase the average channel electric-field, reduce the electric-field at the Drain side, and thus improve the performance of short-channel a-IGZO TFT with immunity to drain-induced-barrier-lowing (DIBL) and hot carrier effect (HCE).

Machine Learning–Assisted Thin-Film Transistor Characterization: A Case Study of Amorphous Indium Gallium Zinc Oxide (IGZO) Thin-Film Transistors

Machine learning was applied to classify the device characteristics of indium gallium zinc oxide (IGZO) thin-film transistors (TFTs). A K-means approach was employed for initial clustering of IGZO transfer curves into three of four grades (high, medium-high, medium, and low) of TFT performance according to qualitative features. A 2-layered artificial neural network (ANN) and 4-layered deep neural network (DNN) were used to extract mobility, threshold voltage, on/off current ratio, and sub-threshold slope device parameters from high-grade and medium-high-grade oxide TFTs. Ground-truth device parameters were calculated using in-house codes based on a rules-based approach consistent with the definitions employed to train the ANN and DNN. The DNN-predicted parameters were in closer agreement with manual and macro-based calculations than were those obtained from the ANN. Synergistic integration of K-means clustering and DNN effectively extracted TFT device parameters encountered in processing high volumes of data in industrial and academic domains of the microelectronics field.

Performance Improvement of Self-Aligned Coplanar Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors by Boron Implantation

The electrical properties and device stability of a self-aligned (SA) coplanar amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) were investigated by implanting boron (B) into the source/drain (SD) n+ region. To evaluate the effect according to the depth profile of B in the a-IGZO film, various implantation energies were applied. The electrical properties were optimized when the projection range of B was in the central vertical region of the a-IGZO film. B implantation decreased the resistivity of the a-IGZO film from 3.1 × 102 to 2.1 × 10–3 Ω·cm compared to an untreated a-IGZO film, while the field-effect mobility (μfe) improved from 2.96 to 17.22 cm2/(V·s). Moreover, the fabricated SA coplanar a-IGZO TFTs with a B-doped n+ region exhibited excellent stability, with a threshold voltage shift (ΔVth) of <0.2 V during a 3000 s thermal stability test performed at 200 °C and a bias stress test under a gate voltage of ±20 V. During the implantation process, B ions with high kinetic energy collide with IGZO atoms, resulting in the formation of an oxygen vacancy (VO) and an oxygen interstitial (Oi) simultaneously. The implanted B ions and Oi are bonded such that the VO sites are maintained by the B–O reaction and can contribute to an increase in the carrier concentration in a-IGZO films, thereby increasing the conductivity of the n+ region.

High-performance hysteresis-free perovskite transistors through anion engineering

Despite the impressive development of metal halide perovskites in diverse optoelectronics, progress on high-performance transistors employing state-of-the-art perovskite channels has been limited due to ion migration and large organic spacer isolation. Herein, we report high-performance hysteresis-free p-channel perovskite thin-film transistors (TFTs) based on methylammonium tin iodide (MASnI3) and rationalise the effects of halide (I/Br/Cl) anion engineering on film quality improvement and tin/iodine vacancy suppression, realising high hole mobilities of 20 cm2 V−1 s−1, current on/off ratios exceeding 107, and threshold voltages of 0 V along with high operational stabilities and reproducibilities. We reveal ion migration has a negligible contribution to the hysteresis of Sn-based perovskite TFTs; instead, minority carrier trapping is the primary cause. Finally, we integrate the perovskite TFTs with commercialised n-channel indium gallium zinc oxide TFTs on a single chip to construct high-gain complementary inverters, facilitating the development of halide perovskite semiconductors for printable electronics and circuits.

Hydrogen incorporation into amorphous indium gallium zinc oxide thin-film transistors

An experimental study is conducted in which the subgap trap density of states (DoS) is measured by ultrabroadband photoconduction (UBPC) to examine hydrogen incorporation into the channel layer of top-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). UBPC reveals that hydrogen incorporation leads to the creation of a spectrally broad (∼0.3 eV FWHM) distribution of electronic states in the bandgap centered at 0.4 eV above the valence band mobility edge and to an increase in valence band tail state density. Concomitantly, drain current–gate voltage transfer curves demonstrate that hydrogen incorporation results in a negative shift in the turn-on voltage. Quantitatively, electronic state densities estimated by UBPC and the turn-on voltage shift are identical. These experimental findings imply that hydrogen acts as a donor in a-IGZO, but that its donor ionization energy is extraordinarily large, i.e., ∼2.8 eV, inconsistent with that of a normal donor. It is proposed that this anomalous donor behavior is a consequence of the negative-U property of hydrogen in a-IGZO in which hydrogen ionization precedes its incorporation into the lattice network.

Highly Reliable Flexible Device with a Charge Compensation Layer.

Flexible devices fabricated with a polyimide (PI) substrate are essential for foldable, rollable, and stretchable products and various applications. However, inherent technical challenges remain in mobile charge-induced device instabilities and image retention, significantly hindering future technologies. Here, we introduce a new barrier material, SiCOH, into the backplane of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) and applied it to production-level flexible panels. We found that the SiCOH layer effectively compensates for the surface charging induced by fluorine ions at the interface between the PI substrate and the barrier layer under bias stress, thereby preventing abnormal positive shifts in threshold voltage (Vth) and image disturbance. The a-IGZO TFTs and metal-insulator-metal and metal-insulator-semiconductor capacitors with a SiCOH layer demonstrate reliable device performance, Vth shifts, and capacitance changes with an increase in gate bias stress. A flexible device with SiCOH enables the suppression of abnormal Vth shifts associated with PIs and plays a vital role in image sticking. This work provides new insights into process integrity and paves the way for expediting versatile form factors.

Bias-stress stability of top-gate coplanar a-ITGZO TFTs with HfO2 and HfAlO gate dielectrics

In this study, we investigated the electrical characteristics of amorphous indium–tin–gallium–zinc-oxide thin-film transistors (TFTs) (a-ITGZO TFTs) with HfO2 and HfAlO gate dielectrics. The mobilities of the a-ITGZO TFTs with HfO2 and HfAlO were 32.3 and 26.4 cm2/V &·s, respectively. The TFT with HfO2 showed a subthreshold swing (SS) of 206 mV/dec and a hysteresis window of 0.60 V, and the TFT with HfAlO showed an SS of 160 mV/dec and a hysteresis window of 0.12 V. The hysteresis windows were related to the interface trap density. The TFT with HfO2 was more vulnerable to positive bias stress; in contrast, the TFT with HfAlO operated stably even after it experienced positive and negative bias stresses for 3000 s.

Fluorinated Metal-Oxide Thin-Film Transistors for Circuit Implementation on a Flexible Substrate

The effects of fluorination on amorphous indium gallium zinc oxide thin-film transistors and circuits fabricated on a polyimide flexible substrate were studied. Attributed to more effective passivation of donor defects for a given thermal budget, fluorination resulted in suppressed apparent short-channel effects and better uniformity of turn-on voltage with reduced negative shift after laser lift-off from a glass carrier substrate. As representative digital circuits, two-input four-output (2-4) decoders were fabricated and characterized to demonstrate the advantages of incorporating fluorination in the construction of circuit building blocks, leading to higher gain, wider noise margins, more tightly distributed transition voltage, and larger output swing.

High-Performance a-IGZO TFT Fabricated With Ultralow Thermal Budget via Microwave Annealing

In this work, we report high-performance amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with atomic layer deposited Al₂O₃ dielectric processed at a minimal temperature of 189.6 &#x00B0;C via microwave annealing (MWA). The a-IGZO TFT with MWA exhibits an improvement of 57&#x0025; in subthreshold swing (SS) compared with the unannealed device; meanwhile, it retains high field-effect mobility of up to 29.2 cm²/(V <inline-formula> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> s) and large switching ratio of &#x003E;10⁸. Moreover, the SS of the device was further reduced through a two-step MWA treatment. It is believed that MWA treatment effectively reduces the density of trap states associated with oxygen vacancies, promotes the formation of lattice oxygen, and thus improves the quality of IGZO film. MWA with low thermal budget shows great potential in applications of the back-end of line (BEOL)-compatible oxide devices.

Amorphous IGZO Thin-Film Transistor Gate Driver in Array for Ultra-Narrow Border Displays

A gate driver in array (GIA) design based on the amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) is developed for narrow border displays. In the design, each TFT in the gate driver circuits is divided into a certain number of smaller size devices, which can be placed in different subpixels. Therefore, the pixel aperture ratio loss is minimized, and uniform placement of the gate driver circuits over the pixel array area is able to be achieved. The proposed step-like repeating block structure further reduces the occupied area of the signal interconnects. A 12.4-inch fringe field switching (FFS) liquid crystal display (LCD) panel of ultra-narrow border (0.5 mm) is demonstrated with reliable operation based on this GIA design, proving its potential for practical applications.

Improving Device Characteristics of Dual-Gate IGZO Thin-Film Transistors with Ar-O2 Mixed Plasma Treatment and Rapid Thermal Annealing.

In this study, high-performance indium–gallium–zinc oxide thin-film transistors (IGZO TFTs) with a dual-gate (DG) structure were manufactured using plasma treatment and rapid thermal annealing (RTA). Atomic force microscopy measurements showed that the surface roughness decreased upon increasing the O2 ratio from 16% to 33% in the argon–oxygen plasma treatment mixture. Hall measurement results showed that both the thin-film resistivity and carrier Hall mobility of the Ar–O2 plasma–treated IGZO thin films increased with the reduction of the carrier concentration caused by the decrease in the oxygen vacancy density; this was also verified using X-ray photoelectron spectroscopy measurements. IGZO thin films treated with Ar–O2 plasma were used as channel layers for fabricating DG TFT devices. These DG IGZO TFT devices were subjected to RTA at 100 °C–300 °C for improving the device characteristics; the field-effect mobility, subthreshold swing, and ION/IOFF current ratio of the 33% O2 plasma–treated DG TFT devices improved to 58.8 cm2/V·s, 0.12 V/decade, and 5.46 × 108, respectively. Long-term device stability reliability tests of the DG IGZO TFTs revealed that the threshold voltage was highly stable.

Effects of polyimide curing on image sticking behaviors of flexible displays

Flexible displays on a polyimide (PI) substrate are widely regarded as a promising next-generation display technology due to their versatility in various applications. Among other bendable materials used as display panel substrates, PI is especially suitable for flexible displays for its high glass transition temperature and low coefficient of thermal expansion. PI cured under various temperatures (260 °C, 360 °C, and 460 °C) was implemented in metal–insulator–metal (MIM) capacitors, amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFT), and actual display panels to analyze device stability and panel product characteristics. Through electrical analysis of the MIM capacitor, it was confirmed that the charging effect in the PI substrates intensified as the PI curing temperature increased. The threshold voltage shift (ΔVth) of the samples was found to increase with rising curing temperature under negative bias temperature stress (NBTS) due to the charging effect. Our analyses also show that increasing ΔVth exacerbates the image sticking phenomenon observed in display panels. These findings ultimately present a direct correlation between the curing temperature of polyimide substrates and the panel image sticking phenomenon, which could provide an insight into the improvement of future PI-substrate-based displays.

Passivation of Solution-Processed a-IGZO Thin-Film Transistor by Solution Processable Zinc Porphyrin Self-Assembled Monolayer

Bottom-gate bottom contact amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) were fabricated using solution processing. The nonpassivated a-IGZO-TFTs exhibited a significant threshold voltage shift, large hysteresis in the current–voltage characteristics, and degradation in the subthreshold swing. TFTs’ performance degradation is due to the interaction of its back channel with adsorbed oxygen and water molecules in the ambient air. The hydroxy-phenyl zinc porphyrin (ZnP) self-assembled monolayer (SAM) was formed on TFTs’ back channel using a low-cost solution-based approach to passivate TFTs back channel. The passivated a-IGZO-TFTs exhibited enhanced electrical characteristics and improved stability compared with nonpassivated TFTs. Passivated TFTs presented significantly reduced hysteresis up to 87% and subthreshold slope degradation up to 71%. The passivated TFTs showed excellent stability under positive (20 V) and negative (−20 V) bias stress conducted for 5000 s.

Mechanical strain and bias-stress compensated, 6T-1C pixel circuit for flexible AMOLED displays

This paper proposes a novel topology for a pixel circuit with a voltage-programmed threshold voltage compensation technique for amorphous indium gallium zinc oxide thin-film transistor (a-IGZO TFT) used in flexible AMOLED (Active-Matrix Organic Light-Emitting Diodes) displays. Simulation of the proposed circuit was done in Cadence Spectre using SPICE models for a-IGZO TFT, and the circuit utilizes six a-IGZO TFTs and one storage capacitor. Moreover, a detailed analytical analysis of the circuit is also done to estimate the error introduced during the emission phase. The simulation results showed that this pixel circuit offers excellent immunity to threshold voltage variation of driving TFT caused by bending and prolonged operation under gate bias. It can compensate for a wide range of VTH variations, i.e., 0 V–2.1 V, from the original 0.7 V of the TFT model, and the maximum percentage error in OLED current obtained was below 1.14%. The circuit proposed also alleviates the effect of electrical instability caused by threshold voltage shifts due to the compressive and tensile strain in the flexible substrate of the AMOLED display. The OLED current error was found to be below 0.0018% for a ±0.3% strain in the driving TFT.

High Voltage Amorphous InGaZnO TFT With F Doped Drain Offset Structure

We report high voltage amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) using a drain offset structure. The a-IGZO TFT with drain offset length (Loff) = 2.5 μm exhibits a maximum operating voltage (VDS, Max) over 90 V, which increases with Loff. The drastic current drop from output characteristics appears for VDS>VDS, Max with a positive threshold voltage shift and increased subthreshold swing from transfer characteristics. We obtain maximum lattice temperatures of ~130 °C for both the conventional and drain offset TFTs due to Joule heating (JH) within the a-IGZO layer by TCAD simulation. It indicates that the rise in temperature by JH is almost independent of Loff. The JH is uniformly distributed over the entire Loff in drain offset TFT compared with a drastic increase near the drain side in conventional TFT. NF3 plasma treatment enhances conductivity at offset region, resulting in large VDS, Max.

Quantitative Analysis of Positive-Bias-Stress-Induced Electron Trapping in the Gate Insulator in the Self-Aligned Top Gate Coplanar Indium–Gallium–Zinc Oxide Thin-Film Transistors

We experimentally extracted the positive bias temperature stress (PBTS)-induced trapped electron distribution within the gate dielectric in self-aligned top-gate (SA-TG) coplanar indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs) using the analytical threshold voltage shift model. First, we carefully examined the effects of PBTS on the subgap density of states in IGZO TFTs to exclude the effects of defect creation on the threshold voltage shift due to PBTS. We assumed that the accumulated electrons were injected into the gate dielectric trap states near the interface through trap-assisted tunneling and were consequently moved to the trap states, which were located further away from the interface, through the Poole–Frenkel effect. Accordingly, we quantitatively analyzed the PBTS-induced electron trapping. The experimental results showed that, in the fabricated IGZO TFTs, the electrons were trapped in the shallow and deep trap states simultaneously owing to PBTS. Electrons trapped in the shallow state were easily detrapped after PBTS termination; however, those trapped in the deep state were not. We successfully extracted the PBTS-induced trapped electron data within the gate dielectric in the fabricated SA-TG coplanar IGZO TFTs by using the proposed method.