Gain Step Research Articles

A 28 GHz balun‐first LNA with db‐linear 32 db gain range for 5 G applications

AbstractThis letter presents a 28 GHz balun‐first low noise amplifier (LNA) featuring a wide dB‐linear variable gain range. The architecture of LNA includes three‐stage cascode amplifiers. An integrated balun at the input stage provides RF ESD protection and converts a single‐ended signal to a differential one (S‐to‐D). A transformer‐based dual‐resonant matching network is designed and analyzed to achieve wideband performance. To realize a continuous dB‐linear variable gain range and consistent input/output matching, gain control is implemented in the second stage using a 5‐bit digital‐to‐analog converter (DAC) for a 32 dB gain range. The DAC can generate a nonlinear analog voltage to control the gate of the common‐gate transistor in the second cascode stage, inversely compensating for the nonlinear gain variations of the cascode amplifier. The LNA is fabricated in 65‐nm CMOS process with a core size of 0.154 mm². Measurement results exhibit a maximum gain of 33.5 dB and a minimum noise figure (NF) of 3.65 dB with a 3‐dB bandwidth of 23–29.5 GHz. The measured variable gain range is approximately 32 dB across 32 different gain states, with a linear gain step of ~1 dB per state and an IP1dB ranging from −6.5 dBm to −35.25 dBm. The power consumption is 35.4–48 mW from a 1.2 V supply voltage.

A 31–36 GHz low noise‐variable gain amplifier with less than 0.37° RMS phase error and 0.4 dB gain step in 65‐nm CMOS

A 31–36 GHz low noise‐variable gain amplifier with less than 0.37° RMS phase error and 0.4 dB gain step in 65‐nm CMOS

A 148–170‐GHz 4‐bit variable gain amplifier with stagger‐tuning and multistage‐phase‐compensation techniques in 0.13‐μm SiGe

AbstractThis letter presents a 148–170‐GHz 4‐bit variable gain amplifier (VGA) with stagger‐tuning and multistage‐phase‐compensation techniques. In the design of this proposed VGA, phase variation is minimized by cascading overcompensation VGA and undercompensation VGA with reverse gain‐phase characteristics and phase suppression characteristics at sideband, achieved through different shunt inductors to ground. Additionally, stagger‐tuning technique has been introduced to realize VGA design. To prove these techniques, a 148–170‐GHz 4‐bit VGA has been fabricated in 0.13‐μm SiGe bipolar complementary metal‐oxide‐semiconductor (350/450 GHz ft/fmax) with a compact size of . The results show the VGA achieves phase variation and over 10‐dB tuning range with 0.6‐dB gain step for a wide operating frequency from 148 to 170 GHz. The RMS gain error is dB, the simulated input is dBm and the total power consumption is 32.4‐mW with 2.25 V supply voltage.

Prospective relations of maternal reward-related eating, pregnancy ultra-processed food intake and weight indicators, and feeding mode with infant appetitive traits

BackgroundInfant appetitive traits including eating rate, satiety responsiveness, food responsiveness, and enjoyment of food predict weight gain in infancy and early childhood. Although studies show a strong genetic influence on infant appetitive traits, the association of parent and infant appetite is understudied. Furthermore, little research examines the influence of maternal pregnancy dietary intake, weight indicators, and feeding mode on infant appetite. The present study investigated relations of maternal reward-related eating, pregnancy ultra-processed food intake and weight indicators, and feeding mode with infant appetitive traits.MethodsMothers in the Pregnancy Eating Attributes Study (458 mothers enrolled, 367 retained through delivery) completed self-report measures of reward-related eating, and principal component analysis yielded two components: (1) food preoccupation and responsiveness and (2) reinforcing value of food. Mothers completed 24-h dietary recalls across pregnancy, and the standardized NOVA (not an acronym) system categorized recalled foods based on processing level. Maternal anthropometrics were measured across pregnancy. At infant age 6 months, mothers reported on feeding mode and infant appetitive traits. Linear regressions were conducted predicting infant appetitive traits from household income-poverty ratio (step 1); maternal reward-related eating components (step 2); pregnancy ultra-processed food intake (% of energy intake), early pregnancy body mass index, and gestational weight gain (step 3); and exclusive breastfeeding duration (step 4).ResultsA 1-SD greater maternal food preoccupation and responsiveness was associated with 0.20-SD greater infant satiety responsiveness (p = .005). A 1-SD greater % energy intake from ultra-processed foods during pregnancy was associated with 0.16-SD lower infant satiety responsiveness (p = .031). A 1-SD longer exclusive breastfeeding duration was associated with 0.18-SD less infant food responsiveness (p = .014). Other associations of maternal reward-related eating, pregnancy ultra-processed food intake and weight indicators, and feeding mode with infant appetitive traits were non-significant.ConclusionsProximal early-life environmental factors including maternal pregnancy dietary intake and feeding mode may facilitate or protect against obesogenic infant appetitive traits, whereas infant appetite may not parallel maternal reward-related eating. Further investigation into the etiology of appetitive traits early in development, particularly during solid food introduction, may elucidate additional modifiable risk factors for child obesity.Trial registrationClinicaltrials.gov. Registration ID – NCT02217462. Date of registration – August 13, 2014.

A 16–24-GHz SiGe Decibel-Linear Low-Gain-Error Digitally Controlled High-Efficiency Variable Gain Amplifier

This letter presents a 16–24-GHz decibel-linear low-gain-error variable gain amplifier (VGA) in 130-nm SiGe technology. Negative feedback resistor is used in current source to expand the gain variation range and improve decibel-linearity. The nonproportion metal-oxide-semiconductor (MOS) array is introduced to reduce the gain variation error. This design achieves a 15–0 dB gain variation range at 1-dB gain step with root mean square (rms) gain-error less than 0.3 dB. The measured OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> is greater than 9.5 dBm between the 1-dB bandwidth of 16–24 GHz and this VGA consumes 8.8 mA from a 1.6-V supply.

A 1.8-2.7 GHz Triple-Band Low Noise Amplifier with 31.5 dB Dynamic Range of Power Gain and Adaptive Power Consumption for LTE Application.

This paper presents a multi-gain radio frequency (RF) front-end low noise amplifier (LNA) utilizing a multi-core based on the source degeneration topology. The LNA can cover a wide range of input and output frequency matching by using a receiver (RX) switch at the input and a capacitor bank at the output of the LNA. In the proposed architecture here, to avoid the saturation of RX chain, 12 gain steps including positive, 0 dB, and negative power gains are controlled by a mobile industry processor interface (MIPI). The multi-core architecture offers the ability to control the power consumption over different gain steps. In order to avoid the phase discontinuity, the negative gain steps are provided using an active amplification and T-type attenuation path that keeps the phase discontinuity below ±5 degrees between two adjacent power gain steps. Using the multi-core structure, the power consumption is optimized in different power gains. The structure is enhanced with the adaptive variable cores and reactance parameters to maintain different power consumption for different gain steps and remain the output matching in an acceptable operating range. Furthermore, auxiliary linearization circuitries are added to improve the input third intercept point (IIP3) performance of the LNA. The chip is fabricated in 65 nm complementary metal-oxide semiconductor (CMOS) silicon on insulator (SOI) process and the die area is 0.308 mm2. The proposed architecture achieves the IIP3 performance of −10.2 dBm and 8.6 dBm in the highest and lowest power gains, which are 20.5 dB and −11 dB, respectively. It offers the noise figure (NF) performance of 1.15 dB in the highest power gain while it reaches 14 dB when the power gain is −11 dB. The LNA consumes 16.8 mA and 1.33 mA current from a 1 V power supply that is provided by an on-chip low-dropout (LDO) when it operates at the highest and lowest gains, respectively.

A Dual-Band 47-dB Dynamic Range 0.5-dB/Step DPA with Dual-Path Power-Combining Structure for NB-IoT.

This paper presents a digital power amplifier (DPA) with a 43-dB dynamic range and 0.5-dB/step gain steps for a narrow-band Internet of Things (NBIoT) transceiver application. The proposed DPA is implemented in a dual-band architecture for both the low band and high band of the frequency coverage in an NBIoT application. The proposed DPA is implemented in two individual paths, power amplification, and power attenuation, to provide a wide range when both paths are implemented. To perform the fine control over the gain steps, ten fully differential cascode power amplifier cores, in parallel with a binary sizing, are used to amplify power and enable signals and provide fine gain steps. For the attenuation path, ten steps of attenuated signal level are provided which are controlled with ten power cores, similar to the power amplification path in parallel but with a fixed, small size for the cores. The proposed implementation is finalized with output custom-made baluns at the output. The technique of using parallel controlled cores provides a fine power adjustability by using a small area on the die where the NBIoT is fabricated in a 65-nm CMOS technology. Experimental results show a dynamic range of 47 dB with 0.5-dB fine steps are also available.

Ultra high gain step up DC/DC converter based on switched inductor and improved voltage lift technique for high‐voltage applications

Voltage lift is a well-known technique to improve the voltage gain of the converter. A combination of switched inductor and the conventional voltage lift technique can be used to achieve high gain, but the semiconductor's stress is still high. An improved voltage lift technique by employing an extra diode and capacitor and a switched inductor is proposed, which significantly increases the voltage boosting factor and reduces the voltage stress of semiconductor devices. The proposed converter is transformerless and non-isolated in nature. The proposed topology has a continuous input source current and has a common connection between the source and the load. The converter is controlled by a single switch, making it simple to use. The steady-state relations are drawn out in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The effect of the unequal inductance on the voltage gain is carried out in detail. The improved voltage lift technique can develop the n-stage converter to improve voltage gain further and reduce stress on semiconductors. The proposed topology is compared with the recent converters, and the effect of the non-idealities on the voltage gain and losses occurring in the components is discussed in detail. A hardware prototype with a rating of 20V/300V, 250 W is built to test the suggested topology's performance and theoretical analysis. At a 20-V input, the highest efficiency was measured to be 95.8%.

A Wideband Reconfigurable CMOS VGA Based on an Asymmetric Capacitor Technique with a Low Phase Variation

This paper presents a wideband digitally controlled variable gain amplifier (VGA) with a reconfigurable gain tuning range and gain step in a 65 nm CMOS process. A unique asymmetric capacitor-based reconfigurable technique is proposed to extend the gain tuning range and realize gain step reconfiguration. An active neutralization topology based on a stackless transistor is utilized to compensate for the additional phase shift introduced by the gain tuning. Moreover, a current-type digital-to-analog converter (DAC) is also integrated for easier precise gain control. With the asymmetric capacitor varying from 1000 fF to 200 fF with a step of 400 fF, the proposed VGA achieves a 12.2/9.2/6.1 dB gain tuning range with a 0.4/0.3/0.2 dB gain resolution, respectively. At the maximum gain tuning range mode, the measured minimum root-mean-square (RMS) phase error is 1.7° at 23.4 GHz. At the finest gain step control mode, the RMS phase error measured across 20–30 GHz is lower than 1.9°. The tested result also shows the proposed VGA achieves a peak gain of 13 dB with a 3 dB bandwidth of 21.4–29 GHz, and the output 1 dB compression point (OP1dB) is up to 8.6 dBm at 25 GHz.

An extendable single‐input reduced‐switch 11‐level switched‐capacitor inverter with quintuple boosting factor

This paper proposes a novel single-phase switched-capacitor-based inverter configuration that in its basic form can generate an 11-level staircase output voltage waveform with sinusoidal output current for Resistive-Inductive (R-L) loads. The increased levels, quintuple voltage-boosting factor, and natural voltage-balancing of capacitors are considered the main features of the proposed basic configuration. The proposed topology requires fewer components (resources, switches, driver circuits, and capacitors) than recently presented similar structures to acquire the same voltage gain and output steps. The proposed basic configuration can be extended in two ways: increasing levels and/or boosting factors with minimal devices. The employment of two half-bridges (rather than an H-bridge) for generating bipolar waveform has limited the number of switches tolerating the maximum output voltage to 2 (instead of 4), which results in reduced total blocking voltage (TBV) and accordingly reduced cost and losses. A comprehensive comparative analysis has been done and presented to verify the supremacy of the suggested structure. The experimental results of the laboratory-scaled prototype of the proposed basic topology have been provided, which approve its correct performance.

Assessment of ship accident risk in the east Surabaya shipping channel using formally safety assessment method

Surabaya East Shipping Channel is part of the busiest shipping lanes west of Surabaya in Indonesia after inflows in Tanjung Priok. With the navigation, channel conditions are long and narrow plus the number of flows in and out of the harbor boats is very vulnerable to accidents resulting in either the stranded sea, ship collision, or other accident types, which would harm the cruise interocular. By looking at the facts above, so it is necessary to conduct a more in-depth study of the accident risk assessment of the shipping channel east of Surabaya. This study aimed to obtain any kind of accident that has a high risk in the port of Surabaya, to know what impact may result from an accident with a high risk and gain steps that can be taken to reduce accidents in Surabaya East Shipping Channel by using Method Formal Safety Assessment (FSA). Of the six types of accidents that occur, there are three accidents with the highest risk of stranded ships, human accidents, collisions with ships dock at the time of sailing ships and dock. The impact of the third accident caused huge material losses. To reduce the risk of all three types of accidents was measured Implied Cost of Averting a Risk (ICAR), the lowest of any risk reduction options. Reduction of risk to do is impose a routine patrol and installation of signs groove ICAR ports have amounted to 234 million, giving a human rescue training vessel which has a value of 112 million ICAR and the latter is tightened harbor area with ICAR 84 million so that unauthorized parties do not enter in the harbor area.

A Ka-Band CMOS Phase-Invariant and Ultralow Gain Error Variable Gain Amplifier With Active Cross-Coupling Neutralization and Asymmetric Capacitor Techniques

This article presents a 23-28-GHz digital-controlled phase-invariant and ultralow gain error variable gain amplifier (VGA) for 5G applications. The mechanisms of gain control and phase variation in CMOS VGA based on single-level transistor structure are analyzed in detail. According to the analysis, an active cross-coupling neutralization (ACCN) technique is proposed. The ACCN technique not only compensates for phase variation, but also makes phase compensation insensitive to the process, supply voltage, and temperature (PVT) variations. For achieving ultralow gain error, an asymmetric capacitive gain resolution improvement (ACGRI) technique is adopted, which realizes a fine gain step with low control circuit complexity. Further to reduce gain error, greatly improving the accuracy and robustness against PVT of gain control is necessary. With regard to this, a current-type digital-to-analog converter (DAC) is also integrated onto the chip. The proposed VGA is demonstrated in 65-nm CMOS technology with a core chip area of 0.14 mm². Under 5-b digital gain control conditions, the presented VGA achieves a measured linear gain tunability range of 6.2 dB with a 0.2-dB fine tuning step. The measured root mean square (rms) phase error is less than 0.92° across 24-28 GHz with a minimum value of 0.63° at 27.8 GHz. The rms gain error is less than 0.13 dB, with a minimum value of only 0.03 dB at 25 GHz. At the maximum gain state, the proposed CS VGA exhibits a peak gain of 29.4 dB with 3-dB bandwidth of 23.5-27.5 GHz and the minimum noise figure is 4.8 dB at 26 GHz. Besides, the measured OP <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex>$_{{1 dB}}$</tex> </formula> and OP <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex>$_{{3 dB}}$</tex> </formula> are 6.3 and 9.6 dBm, respectively. The influence of VT variations on the phase compensation and gain tuning is also measured, and the proposed VGA exhibits strong robustness.

A Low-Band Multi-Gain LNA Design for Diversity Receive Module with 1.2 dB NF.

This paper presents and discusses a Low-Band (LB) Low Noise Amplifier (LNA) design for a diversity receive module where the application is for multi-mode cellular handsets. The LB LNA covers the frequency range between 617 MHz to 960 MHz in 5 different frequency bands and a 5 Pole Single Throw (5PST) switch selects the different frequency bands where two of them are for the main and three for the auxiliary bands. The presented structure covers the gain modes from −12 to 18 dB with 6 dB gain steps where each gain mode has a different current consumption. In order to achieve the Noise Figure (NF) specifications in high gain modes, we have adopted a cascode Common-Source (CS) with inductive source degeneration structure for this design. To achieve the S11 parameters and current consumption specifications, the core and cascode transistors for high gain modes (18 dB, 12 dB, and 6 dB) and low gain modes (0 dB, −6 dB, and −12 dB) have been separated. Nevertheless, to keep the area low and keep the phase discontinuity within ±10, we have shared the degeneration and load inductors between two cores. To compensate the performance for Process, Voltage, and Temperature (PVT) variations, the structure applies a Low Drop-Out (LDO) regulator and a corner case voltage compensator. The design has been proceeded in a 65-nm RSB process design kit and the supply voltage is 1 V. For 18 dB and −12 dB gain modes as two examples, the NF, current consumption, and Input Third Order Intercept Point (IIP3) values are 1.2 dB and 16 dB, 10.8 mA and 1.2 mA, and −6 dBm and 8 dBm, respectively.

A 24–28-GHz Four-Element Phased-Array Transceiver Front End With 21.1%/16.6% Transmitter Peak/OP1dB PAE and Subdegree Phase Resolution Supporting 2.4 Gb/s in 256-QAM for 5-G Communications

This article presents a power efficient 24-28-GHz four-element phased-array transceiver (TRX) front end (FE) for 5-G base stations and user equipment communications. A power efficient hybrid quadrature vector interpolation-based phase-shifting architecture is proposed to increase the TX and RX power efficiency and phase resolution. A transformer-based embedded T/R switch is proposed which minimizes TX and RX losses to ensure high TX output power and power efficiency while maintaining a low noise figure (NF) and extremely compact chip area. The 24-28-GHz four-element TRX FE is implemented in a 65-nm CMOS process (1P9M) for large-scale phased-array applications. The TX and RX paths achieve 0.8° phase resolution with <; 0.47°/0.17-dB RMS phase/gain error as well as 24-dB gain control range with 0.75-dB gain step and <; 0.1°/0.4-dB RMS gain/phase error over 24-30 GHz. The full TX path (including splitter and T/R switch) also achieves a measured 16.6-/18.9-dBm OP1dB/ P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> with 21.1%/16.6% PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">peak</sub> /OP1dB for each FE element while maintaining a minimum 4.4-dB NF in the full RX path (including combiner, T/R switch, and OFF-mode PA) at 28 GHz. Under the 64-/256-QAM modulation measurements, the full TX path achieves a state-of-the-art average output power of 13.5-/10.2-dBm per element (8.4%/3.5% full TX path PAE) with -26.4/-30.8 dB EVM and 27.8-/30.1-dB ACLR at 28 GHz, making the proposed TRX FE can be effectively deployed in both base stations and user equipment for 5-G communications. The chip size of the four-element TRX FE excluding I/O pads is only 3.4×1.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

WITHDRAWN: Bidirectional DC-DC converter for regenerative fuel cell electric vehicle

Today, there has been a rising concern and demand for electric vehicles due to the increase in price and pollution levels caused by non-renewable fossil fuels. Owing to this, the automobile industry is shifting production vehicles which run on electricity along with the traditional fuel gasoline (HEVs) and fully electric vehicles (EVs). One of the newer technological advancement in fuel source of EVs is the hydrogen Fuel Cell. Fuel Cells have more energy density than li-ion battery packs at higher energy levels, but their main drawback is that their output voltage is very low and need to be boosted up to power the EV. For this purpose, a bidirectional DC-DC converter is designed which acts like a high gain step up converter when fuel cell is powering the EV and a synchronous step-down converter when fuel cell is being charged from the high voltage battery pack or during regenerative braking is proposed and designed.

Implementing Robotic-Assisted Gait Training in Acute Inpatient Stroke Rehabilitation: A Quality Improvement Initiative.

The recovery of independent walking is one of the major goals of stroke rehabilitation; however, due to the current acute inpatient rehabilitation care paradigm, the intensity of walking practice provided has been far below that recommended for motor recovery to occur. A quality improvement initiative was implemented to encourage the physical therapist (PT) to incorporate various robotic gait training devices as part of the standard allotted PT sessions to improve the intensity of gait training. After 6 months, a retrospective review was performed to assess the feasibility of the robotic-assisted gait training (RAGT) intervention in limited-ambulatory stroke patients and determine preliminary efficacy of the RAGT program by analyzing Functional Index Measure (FIM) motor gain and accelerometer-based daily step counts in patients who received the RAGT versus a group treated with conventional therapy. About 30% of limited-ambulatory patients admitted to the stroke rehabilitation unit received consistent integrated RAGT without safety concerns. Compared to those who received conventional treatment, these patients showed greater mean FIM motor gain (32.30 versus 17.88) at discharge (P < 0.005) and higher number of step counts in PT sessions (P < 0.005). Age, gender, or admission FIM motor were not associated with FIM motor gain. Across a 6-month initial implementation period, RAGT was feasible and was associated with higher repetition of walking practice and also with improved FIM motor scores in limited-ambulatory individuals in an acute inpatient stroke rehabilitation program. However, the frequency of RAGT and the percentage of patients participating need to further improve. Some strategies to address these concerns were identified.

A Novel Stress Reduction Technique Using Switched Capacitor with Coupled Inductor Based High Gain Converter for Electric Green Transport Scheme

This article develops a newly unique high gain step up DC / DC converter which is the future for interfacing to initiate rear bone of the fully green electric vehicle scheme. This technique optimally integrates four diodes, three capacitors and a modified coupled inductor connected to electric vehicle motor, which is three –phase Brushless DC motor. With this structure, reduced conduction losses, high conversion range and functionality with switched capacitor method and reduced voltage stress will occur during the switching period of the converter. Due to utilization of energy from leakage inductance, mutually joined inductor will support to kick efficiency and power concentration of the developed topology. Herein, the circuit configuration of DC/DC converter accommodating for electric green drive claims for even operation. A grouping of parallel inductor and diode L–D in series with the power switch is developed in this work . The converter suits extra beneficial conservative one by decreasing the switching stress current through the usage of new topology. The new topology results to increase the output voltage to 505V for an input DC voltage of 30V with voltage gain of 24.28, output power 525W achieving the efficiency of 97.74% by means of lossless power electronic semiconductor components. The stress voltage on switch, diode and capacitor is 170 V, which is 34 % of the converter output voltage. The designed converter is simulated using MATLAB/Simulink and the performance of the new topology is compared with different converter topologies. https://dorl.net/dor/20.1001.1.13090127.2021.11.2.8.7

A Variable-Gain Low-Noise Transimpedance Amplifier for Miniature Ultrasound Probes

This article presents a low-noise transimpedance amplifier (TIA) designed for miniature ultrasound probes. It provides continuously variable gain to compensate for the time-dependent attenuation of the received echo signal. This time-gain compensation (TGC) compresses the echo-signal dynamic range (DR) while avoiding imaging artifacts associated with discrete gain steps. Embedding the TGC function in the TIA reduces the output DR, saving power compared to prior solutions that apply TGC after the low-noise amplifier. The TIA employs a capacitive ladder feedback network and a current-steering circuit to obtain a linear-in-dB gain range of 37 dB. A variable-gain loop amplifier based on current-reuse stages maintains constant bandwidth in a power-efficient manner. The TIA has been integrated in a 64-channel ultrasound transceiver application-specific integrated circuit (ASIC) in a 180-nm BCDMOS process and occupies a die area of 0.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It achieves a gain error below ±1 dB and a 1.7 pA/√Hz noise floor and consumes 5.2 mW from a ±0.9 V supply. B-mode images of a tissue-mimicking phantom are presented that show the benefits of the TGC scheme.

A 8.5 to 11.6 GHz digitally controlled variable gain amplifier with 15‐dB gain range and 1‐dB step

AbstractA X‐band variable gain amplifier (VGA) with low phase variation and high control resolution is presented in 180‐nm CMOS. The linear gain VGA and current‐type digital‐to‐analog converter (DAC) are implemented to improve the accuracy of gain control and the robustness against process, supply voltage, and temperature variations (PVT). The measured peak gain and 3‐dB bandwidth are 8 dB and 8.5 to 11.6 GHz, respectively. The gain range is 15 dB with a gain step of 1 dB. With a supply voltage varying from 1.6 to 2.0 V, the root‐mean‐square (RMS) gain and phase errors in 3‐dB bandwidth are &lt;0.62 dB and &lt;1.5°, respectively. With supply of 1.8 V, the measured root‐mean‐square (RMS) gain and phase errors across −25 to 110°C are &lt;0.65 dB and &lt;1.7°, respectively. Comparing the measurement results of five chips, the variation of RMS gain error is &lt;0.24 dB, and the RMS phase errors are almost the same. The measurement results demonstrate the proposed VGA is very suitable for phased arrays in X‐band.

Comprehensive Conception of High Step-Up DC–DC Converters With Coupled Inductor and Voltage Multipliers Techniques

Due to the plethora of non-isolated high gain step-up dc-dc converters presented in the literature, it has become important to comprehensively review and classify them, as well as to derive methods to generalize the usage of the commonly employed techniques. Motivated by this need, this paper not only proposes a new family of high gain step up dc-dc converter, but a generalized methodology to derive them from any classical dc-dc topology by applying a coupled inductor and voltage multiplier cells. For illustrating the methodology, high gain dc-dc converters based on the basic topologies (Buck, Boost, and Buck-Boost) are developed and analyzed. These converters are compared in terms of voltage gain, coupled inductor size, voltage stresses, total device rating, switching frequency effect in power loss, and output power regulation. Moreover, in order to verify the proposal, two practical experimentations are accomplished. Firstly, a prototype able to operate as any of the three basic topologies with different gain cells is developed for comparing theoretical, simulated, and experimental static gain results. Secondly, well-designed prototypes concerning to the Buck-, Boost-, and Buck-Boost-based converters are assembled for efficiency evaluation.