Gain Mismatch Research Articles

Genomic Determinants of Early Recurrences in Low-Stage, Low-Grade Endometrioid Endometrial Carcinoma.

Low-stage, low-grade endometrioid endometrial carcinoma (EEC), the most common histologic type of endometrial cancer, typically has a favorable prognosis. A subset of these cancers, however, displays an aggressive clinical course with early recurrences, including distant relapses. All statistical tests were 2-sided. Using a combination of whole-exome and targeted capture sequencing of 65 FIGO stage IA and IB grade 1 EECs treated with surgery alone, we demonstrate that chromosome 1q gain (odds ratio [OR] = 8.09, 95% confidence interval [CI] = 1.59 to 54.6; P = .02), PIK3CA mutation (OR = 9.16, 95% CI = 1.95 to 61.8; P = .01), and DNA mismatch repair-deficient molecular subtype (OR = 7.92, 95% CI = 1.44 to 87.6; P = .02) are independent predictors of early recurrences within 3 years in this patient population. Chromosome 1q gain was validated in an independent dataset of stage I grade 1 EECs subjected to whole-exome sequencing. Our findings expand on the repertoire of genomic parameters that should be considered in the evaluation of patients with low-stage, low-grade EEC.

Group-Chopping: An 8-Channel, 0.04% Gain Mismatch, 2.1 µW 0.017 mm2 Instrumentation Amplifier for Bio-Potential Recording.

An 8-channel AFE with a group-chopping instrumentation amplifier (GCIA) is proposed for bio-potential recording applications. The group-chopping technique cascades chopper switches to progressively swap channels and dynamically removes gain mismatch among all channels. An 8-phase non-overlapping clocking scheme is developed and achieves excellent between-channel gain mismatch characteristics. The dynamic offsets among all channels are mitigated by the GCIA as well. The GCIA is the first work that minimizes the gain mismatch across more than two channels. With the help of the group-chopping, combined with an area-efficient open-loop structure, the GCIA shows <0.04% between-channel gain mismatch, the lowest mismatch reported to date. The chip is fabricated in 0.18µm 1P6M CMOS, occupies only 0.017 mm2/Ch., consumes 2.1 μW/Ch. under 0.5 V supply and achieves an NEF of 2.1.

Intelligent Correction System of Students’ English Pronunciation Errors Based on Speech Recognition Technology

With the increasingly frequent international exchanges, English has become a common language for communication between countries. Under this research background, in order to correct students’ wrong English pronunciation, an intelligent correction system for students’ English pronunciation errors based on speech recognition technology is designed. In order to provide a relatively stable hardware correction platform for voice data information, the sensor equipment is optimised and combined with the processor and intelligent correction circuit. On this basis, the MLP (Multi-layer Perceptron) error correction function is defined; with the help of the known recognition confusion calculation results, the actual input speech error is processed by gain mismatch; and the software execution environment of the system is built. Combined with the related hardware structure, the intelligent correction system of students’ English pronunciation error based on speech recognition technology is successfully applied, and the comparative experiment is designed and the practical application value of the system is highlighted.

A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation

Different from the conventional two-point modulation (TPM) type-II phase-locked loops (PLLs) requiring non-trivial gain calibrations and TPM type-III PLLs with loop stability concern and limited chirp rate, a self-adapting gain mismatch TPM type-II digital PLL is proposed in this article. It directly detects frequency error as its input signal, allowing frequency ramp tracking with zero steady-state frequency error using a type-II PLL. In addition, the maximum trackable slope in the case of the proposed TPM type-II PLL is intrinsically larger than that of the conventional TPM type-III PLL. A polarity navigator is embedded in the digital loop filter to improve the linearity at the chirp turning-around points (TAPs). Fabricated in a 28-nm complementary metal–oxide–semiconductor (CMOS) technology, the proposed PLL consumes 23 mW from a 1-V power supply and occupies 0.31 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measurement results indicate that the proposed PLL can generate a precise triangular chirp with 2.27-GHz bandwidth (BW) and 18.2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> period at 12.5 GHz. To the best knowledge of the authors, this work demonstrates the widest normalized Chirp-bandwidth and the fastest chirp rate simultaneously.

A Greedy Search Approach for Time-Interleaved ADCs Calibration Based on NRZ Input Patterns

This paper presents a time-interleaved analog-to-digital converter mismatch calibration, which can be adapted to any interleaving factor and calibrate offset, gain, time skew and bandwidth mismatches. Moreover, the proposed scheme utilizes a non-return-to-zero pilot signal, avoiding the high-resolution requirements of sinusoidal generators. In addition, there are no multiplications in the detection path in contrast with the state-of-the-art approaches. Consequently, the proposed calibration presents the smallest complexity in terms of hardware requirements compared to previous work (to the author's knowledge). Therefore, the proposed calibration can be made with the smallest area and power consumption. Numerical simulations show an SNDR improvement of 49.52 dB for a 12-bit 4-channel TI-ADC and an SNDR improvement of 29.64 dB for an 8-bit 32-channel TI-ADC when random mismatches are applied. The measurement results show an SNDR improvement of 24.68 dB for a 3.6 GS/s 2-channel TI-ADC experimental board.

Calibration of gain and timing mismatch for TI-ADCs with signals in all Nyquist zones using adaptive noise canceller

This paper presents a novel all-digital background calibration technique for general Time-Interleaved Analog-to-Digital Converters (TIADCs). Calibration of gain and timing mismatch of TIADCs using the estimation technique is designed based on the principle of the Adaptive Noise Canceller (ANC). In this ANC, there are two stages in gain, timing mismatch estimation in which a cascade structure of the correction and estimation is proposed to guarantee that our calibration achieves high performance. Besides the first Nyquit zone, the input signal at different Nyquist zones is also experimented. It is shown through the result that our calibration performs excellently on all chosen Nyquist zones. It achieves the SNDR (Signal to Noise Ratio) and SFDR (Spurious Free Dynamic Range) improvement of 19dB and 49dB, respectively. Moreover, the synthesized design with hardware co-simulation carried on the Xilinx Kintex-7 field-programmable gate array (FPGA) platform consumes only 7.36 % of the hardware resources of the FPGA chip and reduces the mismatch tone level to -87 dB. In addition, our convergence speed of SNDR during calibration is approximately 1/3 others.

A Background M-Channel Time-Interleaved ADC Calibration for Multilevel Modulations Based on the Probability Density Function Difference and a Greedy Algorithm

This paper presents the first time-interleaved analog-to-digital background calibration targeted for multilevel modulations that can calibrate offset, gain, time skew and bandwidth mismatches (to the author&#x0027;s knowledge). The mismatch errors are estimated based on the interleaving channels histograms. Moreover, the proposed calibration can be adapted to any interleaving factor with a multiplication-less estimation logic based on a greedy algorithm. Numerical simulations show satisfactory performance improvements for a 2-level, a 4-level and an 8-level symbol transmission, along with 4-channel and 32-channel TI-ADC interleaving orders. Furthermore, a new SNDR formula is derived considering all the TI-ADC mismatch distortions that can be compared with the obtained results. The measurement results show the proposed calibration working under a binary PRBS31 pattern with both a 3.6 GS/s and 7.2 GS/s signaling rates for a 3.6 GS/s 2-channel TI-ADC experimental board.

Fully Digital On-Chip Wideband Background Calibration for Channel Mismatches in Time-Interleaved Time-Based ADCs

This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection, achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of the sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels below −60 dBc while running fully in the background. The operation is demonstrated with an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> TI 2-GS/s analog-to-digital converter (ADC) prototype chip implemented in a 28-nm CMOS process.

A 50nV/√Hz 2‐channel time multiplexed bio‐chopper amplifier with current‐attenuated feedback resistor

This paper presents 2-channel time-multiplexed chopper instrument amplifier for better gain accuracy and mismatch. Mostly, the current-attenuated feedback resistor with a duty-cycled resistor is adopted for boosting the RC time constant. It can achieve the high pass corner frequencies between 10 Hz and 320 Hz by a 3-bit digitally controlled resistor bank of the attenuator. As a result, the instrument amplifier achieves 0.6% gain accuracy between two time-multiplexed channels, 100 dB CMRR, -40 dB crosstalk, and noise densities of 50nV/√Hz. It is implemented in a 180-nm CMOS technology. It occupies a 0.6 mm*0.6 mm chip area and consumes 1.5μA current consumption from a 1.8 V supply for each channel.

Intelligent Correction System of Students’ English Pronunciation Errors Based on Speech Recognition Technology

With the increasingly frequent international exchanges, English has become a common language for communication between countries. Under this research background, in order to correct students’ wrong English pronunciation, an intelligent correction system for students’ English pronunciation errors based on speech recognition technology is designed. In order to provide a relatively stable hardware correction platform for voice data information, the sensor equipment is optimized and combined with the processor and intelligent correction circuit. On this basis, the MLP (Multilayer Perceptron) error correction function is defined, with the help of the known recognition confusion calculation results, the actual input speech error is processed by gain mismatch, and the software execution environment of the system is built. Combined with the related hardware structure, the intelligent correction system of students’ English pronunciation error based on speech recognition technology is successfully applied, and the comparative experiment is designed the practical application value of the system is highlighted.

A 20–42-GHz IQ Receiver in 22-nm CMOS FD-SOI With 2.7–4.2-dB NF and −25-dBm IP1dB for Wideband 5G Systems

This article presents a 20–42-GHz in-phase and quadrature (IQ) receiver in 22-nm CMOS fully depleted silicon on insulator (FD-SOI). The receiver includes a wideband low noise variable-gain amplifier (LN-VGA), double-balanced IQ mixers, wideband I/Q generation network and wideband local oscillator (LO) driver, low-pass filters, and wideband intermediate frequency (IF) amplifiers. The measured receiver has a peak conversion gain of 25.3 dB with a 3-dB bandwidth of 19.8–42 GHz and an I and Q bandwidth of 5.7 GHz and covers the 5G millimeter-wave (mm-wave) band. The measured single-sideband noise figure (NF) is 2.7–4.2 dB at 24–42 GHz with an IP1dB of −26 to −23 dBm. The I/Q downconverter consumes a total of 102 mW from 0.8- and 1.6-V supplies. The IP1dB can be improved by 5 dB with an NF degradation by only 1.2 dB using RF VGA gain control. At peak gain and −8-dB VGA setting, the receiver dynamic range is 64–68 dB for a 100-MHz bandwidth, which is very high for low power consumption. The gain and phase mismatch between the I and Q channels is < 0.6 dB and <6°, respectively. To the best of the authors’ knowledge, this is the first wideband I/Q receiver that covers the entire mm-wave 5G band based on GF 22-nm CMOS FD-SOI. The application area is multistandard multigigabit per second communication systems.

Broadband Mismatch Calibration for Time-Interleaved ADC Based on Linear Frequency Modulated Signal

Time-interleaved analog-to-digital converters can significantly increase system sampling rate, but channel mismatches, such as gain mismatch, offset mismatch and phase mismatch, can cause great error in the system. The problem of broadband mismatches calibration for multichannel time-interleaved analog-to-digital converters system will be discussed in this paper by using the foreground calibration technique. Essentially, the calibration can be divided into two steps: First, all the mismatches between analog input and digital output will be measured by taking a linear frequency modulated signal as the reference signal; Next, a set of finite-impulse response filters will be calculated based on those mismatches to generate frequency dependent mismatches compensation, so that the signal to noise and distortion ratio, and spurious-free dynamic range will not be limited by the channel mismatches. There are two advantages of the proposed method when compared with previous methods. The complexity of error estimation can be reduced dramatically and high precision error estimation can also be achieved. In order to evaluate the performance, a series of experiments were conducted in a two-channel time-interleaved analog-to-digital converter system. The results show that the spurious-free dynamic range is improved by more than 10dB.

Resolution-Related Design Considerations for a 120-GS/s 8-bit 2:1 Analog Multiplexer in SiGe-BiCMOS Technology

This article presents a 120-GS/s 2:1 8-bit analog multiplexer (AMUX) in SiGe-Bipolar CMOS (BiCMOS) technology that exhibits the highest effective resolution reported for an AMUX in any kind of semiconductor technology. This article presents the design considerations that have led to this high resolution. In particular, it contains a discussion on the choice of an AMUX circuit concept to support high linearity. A frequency-domain explanatory model for the signal contribution to the effective number of bits (ENoB) in the presence of mismatch errors is presented and applied to the analysis of timing and signal gain mismatch in the AMUX setup. Typical ENoB versus frequency characteristics were identified and utilized to speed up ENoB simulations and to develop calibration procedures for the different mismatch types in the AMUX setup. The results of the analysis and the performance of the AMUX in the calibrated setup were proven by measurement results.

A fast Fourier transform based method to estimate frequency response mismatches in time interleaved systems.

Time interleaving (TI) technique is widely used in acquisition systems to improve the sampling rate. However, as a parallel sampling structure, it inevitably brings in channel mismatches, such as the offset mismatch, gain mismatch, and time mismatch. Moreover, the gain mismatch and time mismatch are frequency-dependent, which means that the gain mismatch and time mismatch will be different when the signal frequency changes. This is because the gain and time mismatches are the special circumstances of frequency response mismatches. In this paper, a frequency response mismatch estimation method in TI acquisition systems is proposed and analyzed. First, the two kinds of mismatch models are compared to find the relationship between frequency response mismatches and the gain and time mismatches. Then, a mismatch estimation method that can estimate mismatches when the analog bandwidth exceeds the sampling rate of a single channel in a time interleaving analog to digital converter is proposed. Sinusoids with different frequencies are utilized to convert the question of estimating frequency response mismatches to acquiring the mismatch coefficients at a series of frequency points. Furthermore, a semi-automatic estimation technique is proposed to reduce the operation time, and a 10 GSPS eight-channel TI system is introduced. Simulations show the accuracy and effectiveness of the proposed method. At last, the frequency response mismatches are calibrated by using the estimated parameters. The calibration improves the performance of an eight-channel TI system from the original spurious free dynamic range of 27.6639 to 56.7029 dB and signal-to-noise ratio of 25.5468 to 32.7667 dB. The calibration result demonstrates the usefulness of the proposed method.

Binary Cyclic Pearson Codes

The phenomena of unknown gain or offset on communication systems and modern storages such as optical data storage and non-volatile memory (flash) becomes a serious problem. This problem can be handled by Pearson distance applied to the detector because it offers immunity to gain and offset mismatch. This distance can only be used for a specific set of codewords, called Pearson codes. An interesting example of Pearson code can be found in T-constrained code class. In this paper, we present binary 2-constrained codes with cyclic property. The construction of this code is adopted from cyclic codes, but it cannot be considered as cyclic codes.

A Novel Low Noise Instrumentation Amplifier for Bio-Medical applications

In this work we propose an efficient and a novel Instrumentation amplifier design fabricated using CMOS technology that can be used for the amplification of bio-medical signals. Instrumentation Biological amplifiers play a crucial role in biomedical devices like hearing aids, pacemaker etc. An instrumentation amplifier with current feedback and Current re-use topology along with the Chopper Offset-stabilization technique which was used in op-amps will also be extended to current-feedback instrumentation amplifiers, will help us to minimize and eliminate the flicker (1/f) noise and the offset voltages that will occur during the design of the feedback amplifiers. The gain mismatch problems that usually occurs due to the use of Current re -use topology was also minimized by the use of dynamic element matching technique that will be described in the paper. The design is simulated using Cadence Spectre tool. The Instrumentation amplifier final layout is designed in Cadence Layout editor with 0.18um CMOS technology.

Deterministic Digital Calibration Technique for 1.5 bits/stage Pipelined and Algorithmic ADCs with Finite op-amp Gain and Large Capacitance Mismatches

This paper proposes a high-speed deterministic digital technique to calibrate the errors due to capacitance mismatch and finite op-amp gain. Unlike other calibration techniques, this technique requires neither forcing the inputs of the intermediate stages being calibrated to exact voltages, nor reducing the gains of each stage to avoid saturation of output digital codes. A 1.5 bits/stage, 10 stages, 9 bits pipeline ADC with the three most significant stages calibrated is demonstrated in this paper. For a 10% mismatch in capacitances in the 3 MSB stages of the pipelined ADC, the calibration technique improved SNDR by more than 20 dB and SFDR by around 27 dB. The technique can also be slightly modified to calibrate algorithmic ADCs. For a 7% mismatch in capacitances of the algorithmic ADC, the proposed calibration technique improved SNDR by 18 dB and SFDR by around 28 dB.

Millimeter-Wave SiGe Radiometer Front End With Transformer-Based Dicke Switch and On-Chip Calibration Noise Source

We present a co-designed Dicke switch and low-noise amplifier (LNA) in which the switch incorporates a transformer-based topology and serves as the input matching network of the LNA. This topology is configured to minimize the amplifier gain mismatch between the two switching states caused by process variations while providing a low noise figure (NF). The circuit is implemented in a 0.13- μm SiGe BiCMOS technology, and it achieves more than 20-dB gain and minimum NF values of 4.5 and 0.58 dB at 300 and 20 K, respectively. It consumes a dc power of 15 mW. The front-end switch presents a peak isolation of 17 dB, and the input return loss is better than 15 dB across 45-70 GHz. A noise source is also coupled to the front-end circuitry to enable on-chip calibration. The noise performance and reliability of several on-chip p-n junctions were characterized, and the one with the highest excess noise ratio was coupled to the front-end circuitry. To the best of our knowledge, the lowest NF of an integrated switch and LNA at V-band frequencies is achieved in the present work, along with the first reliability study of on-chip noise sources in a SiGe BiCMOS technology.

A field programmable gate array based high speed real-time weak periodic signal detection technique

The detection of a high repetition rate weak signal is studied in this paper. Owing to the characteristics of the signal of interest, both high speed analog-to-digital converter (ADC) and low computational complexity data processing techniques are required for high speed real-time weak signal detection. In this paper, a novel field programmable gate array (FPGA) based high speed real-time periodic weak signal detection technique is presented. Cascaded comparators outside the FPGA and cascaded flip flops in the FPGA are used to implement a one-bit ADC, which performs quantization first followed by sampling. Based on this novel design, a time-interleaved structure with several sub-channels is further proposed to significantly improve the sampling rate of the one-bit ADC, which does not require calibration for offset, gain, and sample-time mismatches between sub-channels. Each sub-channel has a long-time coherent integration structure to coherently integrate the sampled one-bit data. A full layer clearance mechanism that only operates on specific bits of the integrated sums is proposed to overcome the influence of a noise baseline drift on the weak signal detection. Compared with the traditional adaptive threshold, this mechanism has a significantly lower computational complexity. A prototype with three sub-channels performing 1.5 Gs/s sampling is implemented to verify the proposed technique. The results obtained confirm its high sampling rate and noise baseline drift tolerance in weak signal detection.

Closed-Form Expression for the Combined Effect of Offset, Gain, Timing, and Bandwidth Mismatch in Time-Interleaved ADCs Using Generalized Sampling

The performance of a time-interleaved analog-to-digital converter (TI-ADC) gets compromised due to offset , gain mismatch , timing mismatch , and bandwidth mismatch . This article analyzes a TI-ADC from a generalized sampling perspective and then develops closed-form expression of the signal-to-noise and distortion ratio (SNDR) of an $N$ -channel TI-ADC when all of gain mismatch , timing mismatch , and bandwidth mismatch are present at the same time. The analysis is then extended to incorporate the effect of offset along with the other three mismatches to arrive at closed-form expression of SNDR in the presence of all the mismatches. The closed-form expressions have been validated through numerical simulations as well.