This paper presents a design methodology for class-J monolithic microwave integrated circuit (MMIC) power amplifiers (PAs). Theoretical derivations of optimum load impedances, output power, efficiency, and maximum bandwidth are described in presence of nonlinear drain–source resistance of transistors $(R_{DS})$ . A procedure is developed for ideal transistor sizing where transistors are concurrently stabilized and sized to achieve the maximum power-added efficiency (PAE). A 3.5–7 GHz, 0.5-W class-J PA is implemented in a $\text {0.1-}\mu \text {m}$ AlGaAs–InGaAs pHEMT technology to check the accuracy of the proposed approach. With chip dimensions of $1.57 \,\, \times \text {1.29 mm}^{2}$ , the PA achieves 56% average PAE over the frequency band while maintaining an average 11-dB small-signal gain.