GaAs FET Research Articles

Power FETs: Failure Analysis (FA) and Reliability Analysis (RA)

FET’s have become increasingly popular as possible replacements for microwave electron tubes and solid-state active diodes. Reliability is extremely important for these devices when used in communication systems, especially for space applications. The reliability of small, signal GaAs FET’s has been extensively investigated. As a result, the reliability of small-signal or low-noise devices is fairly well understood, and the essential problems are practically solved. However, the reliability of power devices is much more complicated because they are expected to operate in the vicinity of their maximum capability of voltage, current, or power dissipation, in the presence of large RF signals.

Planar substrate integrated waveguide‐based resonators and its usage to compact X‐band small phase noise oscillator

AbstractThis study denotes a procedure of a small phase noise (SPN) oscillator employing three different substrate integrated waveguide (SIW) resonators as a frequency stabilization‐component. The SIW resonator as modifying phase noise (PN) is investigated and branchline coupler in the feedback loop is presented. The design technique to attain SPN usage for optimized efficiency is proposed. Then, three different X‐band SIW oscillators using a packaged GaAs FET transistor are planned. Due to the PN and compacting, the miniaturized conventional SIW (MCSIW) oscillator is selected. This MCSIW oscillator operates at 8.15 GHz, mentions a PN of −169 dBc/Hz at 1‐MHz frequency‐offset.

A 6–12 GHz wideband low‐noise amplifier GaAs FET design with 0.8‐dB average NF and 25‐dB gain

AbstractLow‐noise amplifiers (LNAs) with low‐noise performance are critical components in communication systems. However, reaching a high level of performance is difficult. This study introduces a LNA for radio frequency front‐end receivers with a frequency range of 6–12 GHz. The planned LNA contains a two‐stage high‐electron‐mobility transistor cascade amplifier with a minimum measured noise figure of 0.8 dB and a peak gain of 25 dB at room temperature. The proposed LNA is based on a gallium arsenide field‐effect transistor transistor (CE3512K2) because of its good low‐noise performance at microwave frequency bands. The measured results demonstrate that the proposed LNA is perfectly matched over the whole operational frequency spectrum of the input/output ports (|S11|<−10 dB, |S22|<−10 dB). Also, output P1dB and input P1dB are, respectively, +4 and −19 dBm for this design. The suggested LNA is suitable for C and X frequency band applications.

Design of 2.4 GHz LNA of 400 MHz Bandwidth

Low Noise Amplifier (LNA) is the most important front-end block of the receiver. LNA’s Noise figure (NF) and Scattering Parameters affect the overall performance of the whole receiver circuit. Nowadays in the era of 5G technology, The quality of data that is being transmitted is increased. So there is a need for higher bandwidth to transfer data with higher speed. In such a case, communication blocks need an update. The research is carried out for the advancement of the LNA. The primary goal of LNA design is to lower the Noise Figure and return losses. The paper aims to design a 2.4 GHz LNA having a bandwidth of 400 MHz. The circuit is designed with the help of single-stub microstrip lines. We tried to keep the length of microstrip lines as minimum as possible. The transistor ATF-21170 Gallium Arsenide Field Effect Transistor (GaAs FET) is used in this work. The circuit is simulated in the Keysight Advance Design System (ADS). The amplifier is manually designed using standard methods. LNA is unconditionally stable for the frequency range of 2.2 GHz to 2.6 GHz. To build impedance matching circuits of the amplifier smith chart is used. It is observed that the LNA gain (S21) is greater than 15.3 dB, NF less than 1.2 dB, Input return loss (S11) is less than -13.3 dB, Output return loss (S22) is less than -17.1 dB over the 400 MHz bandwidth ranging from 2.2 to 2.6 GHz. This has, to the best of the authors' knowledge, not been presented in literature before.

A Miniaturized Bandwidth Reconfigurable Bandpass Chip Filter with Semi‐lumped Topology and GaAs pHEMT Technology

A miniaturized reconfigurable bandpass chip filter with semi-lumped topology and Gallium Arsenide pseudomorphic High electron mobility transistor (GaAs pHEMT) technology is proposed. Semi-lumped topology is employed to instead the traditional lumped inductor with microstrip transmission line, which can reduced the size of the tunable filter significantly. Three-order series and shunt resonated bandpass filter is implemented with shorted stubs and metal-insulator-metal capacitors. Two transmission zeros are introduced with the series resonator and the shunted GaAs FET. By tuning the gate bias circuit of the FET, the capacitance of the series resonator is changed and the bandwidth of the filter is adjusted correspondingly. An equivalent circuit model is developed to interpret the mechanism of the proposed filter circuit. A reconfigurable on chip filter sample operated at 10GHz is fabricated to validate the design. Two fractional bandwidth of 14.3% and 23.5% are tuned with bias voltage of the FET, while insertion loss of 2.4dB and 2.2dB are observed with the filter, respectively. The area of the chip filter is \begin{document}$ {{0.86 \times 0.96 \mathrm{mm}^{2}}} $\end{document} and is equivalent to an electrical length of \begin{document}$ {{0.08 \times 0.09 \lambda \mathrm{g}^{2} }}$\end{document} at center frequency. Measurement results agree well with the simulation ones.

Numerical analysis of high frequency GaAs FET transistor using alternating direction implicit (ADI) finite-difference time-domain method; Distributed modeling approach

The unconditionally stable ADI Finite Difference Time Domain (FDTD) method is used to govern the distributed model equations of high frequency GaAs FET transistor. This implicit scheme with no constraint by a stability criterion is exploited to increase the time performance of the CPU time considerably compared with the conditionally stable methods such as explicit Leap-Frog (LF) FDTD scheme. Moreover, the ADI method can effectively decrease the complexity of the sparse matrix structure emerging in Crank–Nicolson (CN) FDTD scheme by splitting it into two time increments. The accuracy of the ADI is appreciated to the LF, CN and measured results.

Dynamically Reconfigurable UWB Antenna Using an FET Switch Powered by Wireless RF Harvested Energy

In this article, a dynamically reconfigurable dual-layer ultra-wideband (UWB) antenna integrated with an energy harvesting (EH) system for powering a GaAs FET switch is presented. The UWB antenna dynamically creates a notch band in the presence of an interfering signal at 5.6 GHz and it goes back to normal UWB operation when the interferer is removed. For the switching operation, the FET switch is powered using only harvested energy carried by the interfering signals. The UWB antenna on the front layer is a microstrip-fed monopole with an embedded elliptical slot. A quarter wavelength linear stub acts as a resonator inside the slot, which is connected and disconnected using the low-power FET switch. The UWB antenna shares the RF ground with a very compact EH system that consists of a planar inverted-F antenna, a very compact voltage-doubler rectifier, and a passive direct-current (dc)-to-dc boost converter. The boost converter elevates the rectified voltage to above the 3.3 V threshold, which is the minimum voltage needed for the actuation of the FET switch. The dynamic notch-band reconfiguration of the UWB antenna without the need for an external dc power source is made possible when the collected power at the input of the rectifier is higher than -12 dBm.

Design and Simulation of an RF Feedback Oscillator Circuit Using Conventional X-Parameters

This letter demonstrates for the first time the usefulness of the X-parameters under 50-Ω load condition (conventional X-parameters) for simulating and designing RF feedback oscillator circuits. The measurement procedure to characterize a GaAs FET ATF34143 with conventional X-parameters is presented. The measured X-parameters' data are subsequently used in the design of an RF feedback oscillator at 2.47 GHz. The comparison of the experimental results with the harmonic balance simulations demonstrates the strengths and weakness that conventional X-parameters have to predict the electrical behavior of the feedback oscillator.

Features of Electrophysical Diagnostics of Schottky Field Transistors Based on GaAs Epitaxial Layers on Silicon Substrates for Microsystem Applications

In this paper, the structure of GaAs FET on a silicon substrate, suitable for local integration in the local SOI technology and the method of its electrophysical diagnostics based on changes in the thermal resistance (RT), is analyzed. It is known that the thermal conductivity of GaAs is 3-4 times worse than silicon. To eliminate this disadvantage, the technology of forming high-speed GaAs-structures on the surface of the silicon substrate was propoused.

Resonant Frequency and Bandwidth Tunable Ring Resonator Using GaAs FET SPST Switches

Resonant Frequency and Bandwidth Tunable Ring Resonator Using GaAs FET SPST Switches

Low phase‐noise X‐band oscillator based on elliptic filter and branchline coupler

This paper presents a procedure for designing of a very low phase-noise (LPN) X-band planar microwave oscillator based on a closely packed four-pole elliptic band-pass filter as a frequency stabilisation section. The elliptic band-pass filter as improving phase-noise is realised, and branchline coupler as a key factor in the feedback loop is introduced. The design method to obtain LPN applications for optimum performance is presented. As a proof of concept, the X-band oscillator employing a packaged GaAs FET transistor is designed and measured. The oscillator, operating at 8.172 GHz, exhibits a measured phase-noise of −160 dBc/Hz at 1-MHz frequency offset with 4 dBm output power. To the best of authors’ knowledge, this oscillator indicates the lowest phase-noise in the class of published X-band planar oscillators, to date.

A Two-stages Microstrip Power Amplifier for WiMAX Applications

Amplification is one of the most basic and prevalent microwave analog circuit functions. Wherefore power amplifiers are the most important parts of electronic circuits. This is why the designing of power amplifiers is crucial in analog circuit designing. The intent of this work is to present an analysis and design of a microwave broadband power amplifier by using two stages topology. A two stages power amplifier using a distributed matching network for WiMAX applications is based on ATF-21170 (GaAs FET). The configuration aims to achieve high power gain amplifier with low return loss over a broad bandwidth. The proposed BPA is designed with a planar structure on an epoxy (FR4) substrate. The planar structure is also utilized for getting the good matching condition. The advanced design system (ADS) software is used for design, simulation, and optimization the proposed amplifier. The complete amplifier achieves an excellent power gain; is changed between 28.5 and 20dB with an output power of 12.45dBm at 1dB compression point. For the input reflection coefficient (S11) is varied between -20 and -42dB. While the output reflection coefficient (S22) is varied between -10 and - 49dB over the wide frequency band of 3.2-3.8GHz.

Broadband GaAs FET Power Amplifier for L and S Bands Applications

Broadband GaAs FET Power Amplifier for L and S Bands Applications

Miniaturisation of a 2-Bits Reflection Phase Shifter for Phased Array Antenna based on Experimental Realisation

In this paper, a controllable reflection type Phase Shifter (PS) is designed, simulated and implemented. The structure of the 2-bits PS consists of branch line coupler, delay lines and six GaAs FET switches controlled in pair. The phase shifting is achieved by turning ON one pair of switches. The circuit design is fabricated using FR4 substrate with dielectric constant equal to 4.7. The size of the realised circuit is 7cm×2.8cm. To reduce this size, two methods are used. First, shortened quarter-wave length transmission line in T model is employed to develop a compact branch-line coupler. Second, a loaded line with capacitor is used to reduce the dimension of delays lines. The two methods are combined to realise a PS with compact size equal to 4.5cm×1.96cm.

Frequency Reconfigurable Antenna for Wireless Communications Using GaAs FET Switch

A compact frequency reconfigurable antenna which could be easily switched between a narrowband state and a dual-band state is presented in this letter. The narrowband covers the WLAN (2.4-2.48 GHz) and WiMAX (2.5-2.69 GHz), while the dual-band supports the PCS (1.85-1.99 GHz) and WiMAX (3.4-3.69 GHz). The reconfigurability is achieved by using a single GaAs field effect transistor switch to change the length of the current flow path. The switch can be directly driven by digital signal, and no bias network is needed. The simulated results are in agreement well with the measured results. The proposed antenna is well suited to be integrated within the wireless handheld devices.

마이크로웨이브 수신기용 광대역 RF 증폭기 설계 및 제작

본 논문은 마이크로웨이브 수신기 구성을 위한 광대역 RF 증폭기를 설계 및 제작하였다. 제안한 광대역 RF 증폭기는 수신된 신호의 안정적인 증폭을 위하여 소스단자에 연결되는 비아까지 EM설계를 하였으며, 능동소자의 소오스(Source) 측이 이상적인 접지(GND)로 동작함에 따라 발진하는 요소를 최소화 하여 광대역에서 일정한 이득 특성 및 안정적인 증폭특성을 얻도록 하였다. 상용 GaAs FET를 사용하고, 광대역 마이크로웨이브 수신기의 IF 주파수 대역인 720 MHz, 4,595 MHz와 6,035 MHz에서 동작하도록 입력 및 출력 정합회로를 구성하였다. 제작 및 측정결과 500 MHz ~ 7 GHz의 광대역 특성을 나타내었으며, 전압이득은 737.5 MHz에서 6.0575 GHz까지 10.635 dB ~ 13.129 dB, 기본파와 제2차 고조파 사이에서 20 dBc 이상의 고조파 억압특성을 나타내었다. In this paper, We proposed a broadband RF amplifier for Microwave band receiver. We also proposed a broadband RF amplifier, designed by using EM simulation for reliable amplification of the received signal. Connected to a source terminal to via, it minimizes those which are the active elements of source-side oscillation as the operating element in an ideal GND, and a constant gain characteristic in a broadband. The goal of this was to obtain stable amplification characteristics. For implementing this architecture, we designed the broadband(500 MHz ~ 7 GHz) RF amplifier by using commercial GaAs FET, which operate on 720 MHz, 4,595 MHz, and 6,035 MHz by impedance matching. The voltage gain is 10.635 dB ~ 14.407 dB(737.5 MHz ~ 6.0575 GHz), P1dB is 20 dBc of band(1st harmonic/2nd harmonic).

An alternative method to extract the parasitic capacitances of GaN FETs

ABSTRACTThis work presents a method to determine the parasitic capacitances of GaN FETs, especially the Cpd. The proposed method is based on an idea used for GaAs FET that assumes that Cpd is directly proportional to Cds by a factor of 0.25. The contribution of this work lies in the adaptation of this technique to be suitable for GaN FETs by proposing a methodology to accurately compute the proportionality factor. The proposed procedure is based on the ratio of Im(Y11+Y12) to Im(Y22+Y12), which is related to the asymmetry of the depletion region of the GaN FET under pinched‐off Cold‐FET condition. To validate the proposed method, several GaN FETs were modeled using the extracted capacitances and the simulations results have a high correlation with experimental data. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:223–225, 2015

Numerical simulation of the response of substrate traps to a voltage applied to the gate of a gallium arsenide field effect transistor

We report on a numerical simulation of the response of substrate traps to a voltage applied to the gate of a gallium arsenide field effect transistor (GaAs FET) using proprietary simulation software. The substrate is assumed to contain shallow acceptors compensated by deep levels. The ratio between the densities of deep and shallow levels is considered to be one hundred, which is a typical value for semi-insulating substrates. Although several traps may be present in the substrate but only the most commonly observed ones are considered, namely hole traps related to Cu and Cr, and the familiar native electron trap EL2. The current–voltage characteristics of the GaAs FET are calculated in the absence as well as in the presence of the above mentioned traps. It was found that the hole traps are affected by the gate voltage while the electron trap is not. This effect on the response of hole traps is explained by the fact that the quasi-hole Fermi level in the substrate is dependent on the gate voltage. However, the electron quasi-Fermi level in the substrate is insensitive to the gate voltage and therefore electron traps are not perturbed.

Backgating effect in GaAs FETs with a channel—semi-insulating substrate boundary

This study focuses on modeling the effects of deep hole traps, mainly the effect of the substrate (backgating effect) in a GaAs transistor MESFT. This effect is explained by the existence, at the interface, of a space charge zone. Any modulation in this area leads to response levels trapping the holes therein to the operating temperature. We subsequently developed a model treating the channel substrate interface as an N—P junction, allowing us to deduce the time dependence of the component parameters of the total resistance Rds, the pinch-off voltage VP, channel resistance, fully open Rco and the parasitic series resistance RS to bind the effect trap holes H1 and H0. When compared with the experimental results, the values of the RDS (tS) model for both traps show that there is an agreement between theory and experiment; it has inferred parameter traps, namely the density and the time constant of the trap. This means that a space charge region exists at the channel—substrate interface and that the properties can be approximated to an N—P junction.

A High-Speed LED Driver That Sweeps Out the Remaining Carriers for Visible Light Communications

The modulation speed of light-emitting diodes (LEDs) must be increased to improve the speed, increase the bandwidth, and miniaturize the hardware of visible light communication (VLC) systems. The LED modulation speed is limited by the remaining carriers that remain in the depletion capacitance. In this paper, we evaluate the increase in optical transmission rate for an LED driver for the first time by sweeping out the remaining carriers in a GaN-based LED for VLC system. The driver is fabricated using discrete GaAs FETs and passive elements on a board. An optical transmission experiment is performed. The experimental results demonstrate that the driver increases the maximum error-free bit rate for a NRZ PRBS signal from 69 to 95 Mb/s (38% increase). However, the additional current path for carrier sweep-out increases the power dissipation of the driver. To reduce the power dissipation, we employ a CMOS inverter, in which a PMOS FET sweeps out the carriers. The driver is fabricated using a 0.18-μm CMOS IC process and then implemented in a package. The experimental results demonstrate that this design increased the maximum error-free bit rate from 27.5 to 51.8 Mb/s (88% increase). The maximum bit rate for the packaged driver is 20% higher than that of the driver measured on the wafer.