GaAs DCFL Research Articles

Analysis of the operating-speed and power consumption of GaAs DCFL D-type flip-flops

The article describes, in terms of steady-state sinusoidal analysis, simple analytical expressions for the operating speed and power consumption of DCFL D-type flip-flops. The maximum operating speed fOPmax is limited to fτsin{ π/( n g+1)}/2 n FO, where f T is the cut-off frequency, n G is the number of critical path gates, and n FO is the fan-out number. In contrast, the influence of maximum frequency of oscillation f max on f OPmax is small compared with that for f T, but an FET with a higher f max can reduce the power consumption. These analytical results agree well with the experimental results.

A technique for compensating for temperature variation in low-supply-voltage GaAs DCFL circuits

This paper describes a technique for compensating for the thermal variation in DC characteristics and propagation delay for GaAs DCFL circuits. This technique controls a voltage with a minus-one slope of the transfer curve by applying the substrate voltage. The experimental circuit demonstrated no degradation in noise margin for the temperature range from 30 to 130°C and the temperature coefficient of the propagation delay for this circuit was as small as +0.19%/°C. Copyright

Comparison of GaAs DCFL and CMOS technologies for MCM-D implementations of a modularly configured attached processor

This paper describes the comparative evaluation of 1 μm GaAs DCFL and silicon CMOS technologies, for implementing a novel Modularly Configured Attached Processor (MCAP) architecture in MCM-D configuration. The transistor count was approximately ten million transistors for both cases, distributed on 25 chip dice. Delay, area and power calculations were performed using the SUSPENS model. Speed was calculated to be in the range of 250MHz using GaAs DCFL logic whereas, with silicon CMOS technology, speed was in the 100MHz range. The module footprint was found to be 90cm2 and power dissipation per unit area was low enough to allow air cooling in both cases.

Timing models for gallium arsenide direct-coupled FET logic circuits

In this paper we derive delay and transition time macromodels for GaAs DCFL logic gates. The macromodels are derived by a systematic application of dimensional analysis aimed at finding suitable minimal functional forms that capture the effects of all relevant parameters. The process is illustrated through a detailed step-by-step account of the macromodel development for DCFL inverters. Based on different modeling approximations, one- and two-argument macromodel functions are derived and compared. The inverter macromodel is then used as a basis for developing timing macromodels for superbuffers and NOR gates. The NOR gate macromodels account for the simultaneous and near-simultaneous switching of two inputs, with an extension to multiple inputs. >

GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's

GaAs 2.5 Gbps 16 bit MUX/DEMUX LSI's have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. To avoid the speed degradation caused by using DCFL, various technologies such as 8/spl times/2(MUX)/2/spl times/8(DEMUX) data conversion processes, a Selector Merged Shift Register, clock overlapping, and a 0.7-/spl mu/m BPLDD MESFET, have been introduced. Moreover the ECL I/O level interface and single power supply features make it easy to use MUX/DEMUX in optical communication systems. The maximum operating data rate is 3.2 Gbps for both LSI's, and the power dissipation of chips which operates with 2.5 Gbps are as low as 1.3 W for each MUX/DEMUX.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High speed primitives of hardware accelerators for DSP in GaAs technology

The EUROCHIP initiative is providing foundry, access and full support for a variety of technologies including CMOS and BiCMOS. At present, a GaAs foundry has been selected for high-frequency analogue design (MMIC), and some wafers have been processed. However no foundry runs have yet been selected for GaAs digital circuits. A number of European design laboratories are looking forward to that possibility. Certainly there are not many European foundries with suitable processing. Meanwhile, access to GaAs foundries has been set up by an international university consortium. In particular, this work has been done under the research program in GaAs digital circuits design set up by the Centro de Microelectronica Aplicada, of the University of Las Palmas, in collaboration with the Centre for Gallium Arsenide VLSI Technology, University of Adelaide, and the Middlesex Polytechnic of London. We hope that, in the future, EUROCHIP can support this technology. The paper describes work to design a set of basic computational primitives in digital signal processing (DSP) such as registers, adders and multipliers, and explores the influence of layout and design methodology on the performance of these cells. They have been developed using a design and buffering technique, and symbolic layout notation, well suited for robust design in GaAs DCFL logic. The results obtained so far show that they represent a good compromise between speed, area, and power for VLSI circuits.

A two-dimensional integrated device/circuit numerical model for GaAs DCFL gate simulation

A two-dimensional integrated numerical device/circuit model for GaAs/MESFET DCFL gate simulation is presented. It is different from previous publications in that (a) transient carrier transport equations of the FETs are calculated with consideration for the interaction between interconnected FETs in a circuit, (b) the numerical calculations are carried out for the coupled equations to provide accuracy and (c) with the new algorithm used, the numerical calculation can be carried out with high efficiency. A “dynamic method” and a “single gate method” have been developed to simulate the steady state transfer and ring oscillator transient characteristics, respectively, which have proved to be much more efficient than the previously used methods. Based on the model, a gate level two-dimensional numerical simulator, LADES2G, has been developed and successfully applied to GaAs DCFL circuit design.

A transient numerical scheme for the simulation of GaAs MESFETs and circuits

In this paper, an algorithm, Alternating Direction Scheme (ADS), for solving a two-dimensional time-dependent continuity equation is presented. By separating the continuity equation into two parts based on the direction ( x or y) of the vectors and solving them alternatively, ADS deals with the two-dimensional equation in a one-dimensional way and therefore has the advantages of better stability, less calculation, faster convergence and wider time steps than the schemes previously used. The application of the algorithm not only greatly improves the efficiency of the intrinsic response simulation, but also makes the two dimensional GaAs DCFL inverter simulation possible and practical.

Proposal of GaAs stacked DCFL circuit

The proposed stacked GaAs DCFL circuit structure can not only equalise a power supply voltage value (3–5 V) used in Si ICs, but can also reduce circuit current (30–50%) due to current sharing within a stacked circuit. A divide by 128/129 and 64/65 prescaler IC has been fabricated to confirm this concept.

High-speed and low-power GaAs DCFL divider

High-speed and low-power divide-by-252 or -256 circuit have been fabricated by using high-transconductance GaAs enhancement-mode MESFETs. This variable-modulus divider is able to operate up to a clock frequency of 3.7 GHz. The total power dissipation at the maximum frequency is 180 mW, and it is as low as 42 mW and 30 mW at 3 GHz and 2.5 GHz, respectively.

500 Gates GaAs Gate Array

High speed GaAs DCFL gate array consisting of 500 3-INPUT NOR gates, in which 2000 FETs are integrated, has been successfully fabricated by a Pt buried gate planar E/D process technology. Eleven different 15-stage ring oscillators were made on this gate array to investigate the dependence of gate performance on various loading conditions. Typical propagation delay times per gate were 0.16 ns and 0.69 ns under unloaded and loaded (fan-out=3, interconnection length=3 mm, cross-over=20) conditions at a power dissipation of 0.50 mW for 1.7 µm gate devices.

Design and Performance of GaAs DCFL Frequency Divider

GaAs frequency dividers for application to gigahertz-band equipment have been developed with E/D DCFL circuits. The relationship between maximum counting frequency and threshold voltage combination of the E-MESFET's and the D-MESFET's has been investigated in detail. The measured performance was as follows maximum counting frequency is 1.1 GHz with low dissipation power of 17 mW, and the values of dissipation power-divided-by-maximum-counting-frequency are as small as 1.6-16 pJ.

Analysis for optimum threshold voltage and load current of E-D-type GaAs DCFL circuits

A GaAs MESFET E-D invertor was analysed to estimate the optimum threshold voltage VT for a switching FET, and the optimum load current IL for a load FET, that will minimise the invertor switching time. The calculated results show that the optimum VT lies at around 0.2 V, and the optimum IL is about 55% of the saturation current of the switching FET.