Future Interconnects Research Articles

Theoretical study of point defects on transport properties in metallic interconnections

During the line width reduction, electron scattering caused by various defects in metal interconnects increases dramatically, which causes leakage or short circuit problems in the device, reducing device performance and reliability. Point defects are one of the important factors. Here, using density functional theory and non-equilibrium Green's function methods, we systematically study the effects of point defects on the transport properties of metals Al, Cu, Ag, Ir, Rh, and Ru, namely vacancy defects and interstitial doping of C atom. The results show that the conductivity of all systems decreases compared to perfect systems, because defects cause unnecessary electron scattering. Since the orbital hybridization of the C atom with the Al, Cu and Ag atoms is stronger than that metals Ir, Rh and Ru, the doping of C atom significantly reduces the conductivity of metals Al, Cu and Ag compared to vacancy defects. In contrast, vacancy defects have a greater impact than doping on the transport properties of metals Ir, Rh and Ru, which is mainly attributed to the larger charge transfer of the host atoms around the vacancies caused by lattice distortion. In addition, metal Rh exhibits excellent conductivity in all systems. Therefore, in order to optimize the transport properties of interconnect metals, our work points out that the doping of impurity atoms should be avoided for metals Al, Cu and Ag, while the presence of vacancy defects should be avoided for metals Ir, Rh and Ru, and Rh may be an excellent candidate material for future metal interconnects.

High-Performance Gate-Controlled Superconducting Switches: Large Output Voltage and Reproducibility.

Logic circuits consist of devices that can be controlled between two distinct states. The recent demonstration that a superconducting current flowing in a constriction can be controlled via a gate voltage (VG)─gate-controlled supercurrent (GCS)─can lead to superconducting logic with better performance than existing logics. However, before such logic is developed, high reproducibility in the functioning of GCS devices and optimization of their performance must be achieved. Here, we report an investigation of gated Nb devices showing GCS with very high reproducibility. Based on the investigation of a statistically significant number of devices, we demonstrate that the GCS is independent of the constriction width, in contrast with previous reports, and confirm a strong correlation between the GCS and the leakage current (Ileak) induced by VG. We also achieve a voltage output in our devices larger than the typical values reported to date by at least 1 order of magnitude, which is relevant for the future interconnection of devices, and show that Ileak can be used as a tool to modulate the operational VG of devices on a SiO2 substrates. These results altogether represent an important step forward toward the optimization of reproducibility and performance of GCS devices, and the future development of a GCS-based logic.

Optimizing Ultrathin 2D Transistors for Monolithic 3D Integration: A Study on Directly Grown Nanocrystalline Interconnects and Buried Contacts.

The potential of monolithic 3D integration technology is largely dependent on the enhancement of interconnect characteristics which can lead to thinner stacks, better heat dissipation, and reduced signal delays. Carbon materials such as graphene, characterized by sp2 hybridized carbons, are promising candidates for future interconnects due to their exceptional electrical, thermal conductivity and resistance to electromigration. However, a significant challenge lies in achieving low contact resistance between extremely thin semiconductor channels and graphitic materials. To address this issue, an innovative wafer-scale synthesis approach is proposed that enables low contact resistance between dry-transferred 2D semiconductors and the as-grown nanocrystalline graphitic interconnects. A hybrid graphitic interconnect with metal doping reduces the sheet resistance by 84% compared to an equivalent thickness metal film. Furthermore, the introduction of a buried graphitic contact results in a contact resistance that is 17 times lower than that of bulk metal contacts (>40nm). Transistors with this optimal structure are used to successfully demonstrate a simple logic function. The thickness of active layer is maintained within sub-7nm range, encompassing both channels and contacts. The ultrathin transistor and interconnect stack developed here, characterized by a readily etchable interlayer and low parasitic resistance, leads to heterogeneous integration of future 3D integrated circuits (ICs).

Mechanical characterizations of η′-Cu6(Sn, In)5 intermetallic compound solder joint: Getting prepared for future nanobumps

As advanced silicon manufacturing processes slow down in scaling, three-dimensional stacking of chips has become a future trend in microelectronic industry. High-density bonding technology is one of the core technologies used to achieve the stacking. In this work, we explored a new bonding technology that is possible to manufacture future high-density interconnects. We fabricated a series of sandwich structure solder joints with different thicknesses using SnBiIn-based nanoparticles under a low bonding temperature of 100 °C. The intermetallic compound (IMC) at the interface is proven to be η′-Cu6(Sn, In)5 nanocrystals with random grain orientations through X-ray diffraction (XRD), high-resolution transmission electron microscope (HRTEM), and atomic probe tomography (APT). The hardness and elastic modulus of η′-Cu6(Sn, In)5 were measured to be 4.093 GPa and 79.586 GPa by micropillar compression tests, respectively, decreasing by 35% and 29.1% compared to Cu6Sn5. Therefore, doping In atoms reduces the brittleness of IMCs, providing a new approach for mitigating the mechanical failures of full IMC bump. First-principles calculation also verified the change in mechanical properties. Furthermore, a full-Cux(Sn, In)y IMCs solder joint and an array of 3 μm solder joints were fabricated experimentally using the bonding technology. This technology successfully demonstrates a pioneer interconnection bonding methodology for future ultra-high-density chip stacking using low melting point solder nanoparticles.

Energy Islands in Greece: Are they Feasible in Aegean Sea?

The future development of energy islands in North Sea is going to assist the further growth of offshore wind farms in a territory characterized by rich wind energy resources. The development of offshore wind farms in Aegean Sea, which is characterized by high mean annual wind velocities, is in the initial phase while it is foreseen that by 2050 the electricity generated by offshore wind farms will have a high share in the energy mix in Greece. The future interconnection of the electric grids of the small islands in Aegean Sea with the grid of continental Greece is going to trigger the development of new renewable energy installations in these islands reducing the current use of oil-based fuels in them. The development of offshore wind farms in Aegean Sea could be combined with green hydrogen production, when it is profitable, while it could be also used in the future for electricity generation from sea waves. The future development of physical energy islands in the Archipelago combined with the development of offshore wind farms and the interconnection of the small islands' grids could promote the further development of the rich solar and wind energy resources in Aegean Sea assisting the de-carbonization of the Greek power system. The current work could be useful to policy makers, to local and regional authorities as well as to energy companies which are willing to invest in renewable energy systems in Aegean Sea.

Surface acoustic wave actuated plasmonic signal amplification in a plasmonic waveguide

Enhancement of nanoscale confinement in the subwavelength waveguide is a concern for advancing future photonic interconnects. Rigorous innovation of plasmonic waveguide-based structure is crucial in designing a reliable on-chip optical waveguide beyond the diffraction limit. Despite several structural modifications and architectural improvements, the plasmonic waveguide technology is far from reaching its maximum potential for mass-scale applications due to persistence issues such as insufficient confined energy and short propagation length. This work proposes a new method to amplify the propagating plasmons through an external on-chip surface acoustic signal. The gold–silicon dioxide (Au-SiO2) interface, over Lithium Niobate (LN) substrate, is used to excite propagating surface plasmons. The voltage-varying surface acoustic wave (SAW) can tune the plasmonic confinement to a desired signal energy level, enhancing and modulating the plasmonic intensity. From our experimental results, we can increase the plasmonic intensity gain of 1.08 dB by providing an external excitation in the form of SAW at a peak-to-peak potential swing of 3 V, utilizing a single chip.

(Invited) Interlayer Excitons in Two-Dimensional Perovskite/Monolayer Transition Metal Dichalcogenide Heterostructures

The emergence of two-dimensional (2D) materials has intrigued a great deal of research on novel physical phenomena and various functional applications due to their particular crystal structures and reduced dimensionality. Unlike 3D materials, bulks of 2D materials can be easily thinned to atomic thickness by mechanical exfoliation and atomically thin 2D materials can be arbitrarily stacked to form vertical van der Waals (vdW) heterostructures, which could inherit the unique characteristics of the constituent layers and even exhibit new properties not possessed by them. Particularly, when type-Ⅱ vdW heterostructures are excited, the positive and the negative charges would reside in the different layers after the charge transfer but be limited within a short distance due to the strong quantum confinement effect of 2D materials, leading to strong Coulomb interaction and the formation of interlayer excitons (IXs). IXs are generally equipped with orientated dipole moment and long lifetime, making them ideal media for the future interconnects between optical transmission and electronic computation. Currently, studies on IXs are mainly focused on the vdW heterostructures formed by monolayers of transition-metal dichalcogenides (TMDs). Here, I will first talk about vdW heterostructures formed by 2D perovskites and TMDs for studying IXs. Stacking different kinds of 2D perovskites and TMDs, formation of IXs is confirmed by excitation-power-, temperature-, electric-field-dependent and time-resolved photoluminescence (PL) studies. Notably, robust IX emission can be observed regardless of the stacking sequence and geometric alignment of the constituent layers, showing great advantages over the TMD/TMD vdW heterostructures, which require special twist-angle and thermal annealing. Then, I would like to give a brief introduction on widely tuning the IX emission energy by changing the layer number of the 2D perovskite or the TMD, which shed light on the application of 2D perovskite/TMD vdW heterostructures in broad-spectrum optoelectronics. Furthermore, I would like to next talk about how the selection of organic chains in 2D perovskites influences the properties of the IXs. By using chiral 2D perovskites, the IX emission shows substantial circular polarization and the polarization direction is only related to the chirality of the molecules regardless of the excitation scheme or any other external field, which could open up new passages for controlling valley- or spin-polarization of IXs. By introducing molecules with different dielectric constants, the dielectric screening strength in the vdW heterostructure is changed and hence the binding energy of the IXs is also modified, which offers great opportunities for exploiting tunable excitonic devices and studying exciton condensation. Finally, I will also introduce IX as a non-destructive tool for probing the local phase transition at the surface of the 2D perovskite (BA)2PbI4 flakes. By spatially PL mapping of the (BA)2PbI4/WSe2 heterostructure, two different IX species can be observed to distinguish the low-temperature and the high-temperature phase respectively.

Growth behavior and mechanism of atomic layer deposition of Ru for replacing Cu-interconnects

The growth behavior and nucleation mechanism of Ru films on various substrates using Ru(EtCp)2 as the precursor and O2 as the reactant were studied systematically. The results show that the Ru films grow rapidly on TiN substrates with almost no incubation time. Different of the segregation and combustion mechanism reported in the previous literature, we established the adsorption and combustion mechanism of ALD-Ru on TiN substrates. SEM and XPS confirmed that the grown Ru films were polycrystalline (average grain size of 16.53 nm, negligible impurities). The Ru films annealed at 600 °C showed significantly low resistivity of 9.73 μΩ•cm, which is one of the lowest resistivities reported in the literature so far. Suppressing electron scattering at grain boundaries is crucial factor to preparing Ru films with low resistivity. The work uses a simple plasma-free technique to construct high-quality Ru films with extremely low resistivity and low impurities, making them one of the ideal candidates for replacing Cu in future ultrafine-pitch interconnects. Furthermore, the work is significant for understanding the growth behaviors and nucleation mechanisms of Ru films on different substrates.

A review on future novel interconnect and polymeric materials for cryogenic memory packaging

A review on future novel interconnect and polymeric materials for cryogenic memory packaging

Prospects and Obstacles in the Bilateral Relations between Pakistan and Turkey

Since gaining independence, Pakistan and Turkey have maintained robust diplomatic relations. There are several connections that encompass trade, culture, spirituality, and similar values. The two fraternal nations have already been collaborating to enhance their commercial cooperation with the aim of achieving success in the global market and establishing trade agreements. Pakistan has had strong diplomatic relations with Turkey since its establishment. Both nations hold comparable perspectives on various global and regional matters. There exists a historical, religious, and cultural connection between Pakistan and Turkey. Both nations are situated in highly significant geostrategic regions and hold considerable importance within the Muslim world due to the robustness of their governments, economies, and military capabilities. Despite the mutual positive sentiments between Islamabad and Ankara, their efforts to foster robust economic and trade relations were unsuccessful. This study employs a chronological historical survey and a qualitative research methodology to examine the dynamics and rationales behind the evolution of bilateral interactions throughout history. Additionally, it examines the factors that have hindered the establishment of robust economic links between the two nations, including security concerns and the shared cultural and religious identities. This study will also examine the temporal stability of these factors and explore the potential implications and challenges that may arise from their future interconnections.

Design Issues in Intercalation-Doped-Multilayer Graphene Nanoribbon-Based Future Interconnects in Deep Submicron Regime

Intercalation-doped multilayer graphene nanoribbon (ID-MLGNR) is a potential contender for future interconnect applications. This work presents a comprehensive analysis of temperature-dependent design issues in ID-MLGNR-based future VLSI interconnects based on a temperature-dependent mean free path (MFP) model incorporating scattering owning to rough edges and defects in GNRs, which consequently reflects the extrinsic temperature-dependent circuit behavior of these interconnects in terms of wire impedance, propagation delay, and power dissipation. It is found that in deep submicron (DSM) regime, at a specific technology node of 14-nm MFP, edge scattering improves by 74% as Fermi energy ([Formula: see text] increases from 0.2 to 0.6, and at a specularity constant, [Formula: see text] for local and intermediate level of interconnects. For similar values of [Formula: see text] and [Formula: see text], at global length, this rise in MFP is about 70%, which signifies the significant reduction in resistance (varies inversely to MFP). Whereas, negligible variations are observed in the conductance and inductance of ID-MLGNR interconnects with an increase in temperature. Nevertheless, the reduction in resistance for local & intermediate, and global MLGNR interconnects reflects its low propagation delay and power-delay-product (PDP) for future VLSI ICs applications despite the negligibly poor decrease in power dissipation (with an overall % reduction in the power dissipation from 300[Formula: see text]K to 500[Formula: see text]K evaluated to 3.54% regardless increase in [Formula: see text] from 0.2[Formula: see text]eV to 0.6[Formula: see text]eV).

Highly efficient electroluminescence from SnO2 nanocrystals and Er3+ co-doped silica thin film via introducing Ca2.

Efficient and stable near-infrared silicon-based light source is a challenge for future optoelectronic integration and interconnection. In this paper, alkaline earth metal Ca2+ doped SiO2-SnO2: Er3+ films were prepared by sol-gel method. The oxygen vacancies introduced by the doped Ca2+ significantly increase the near-infrared luminescence intensity of Er3+ ions. It was found that the doping concentration of Sn precursors not only modulate the crystallinity of SnO2 nanocrystals but also enhance the luminescence performance of Er3+ ions. The stable electroluminescent devices based on SiO2-SnO2: Er3+/Ca2+ films exhibit the power efficiency as high as 1.04×10-2 with the external quantum efficiency exceeding 10%.

Flexible Data Rate Allocation Using Non-Orthogonal Multiple Access (NOMA) in a Mode Division Multiplexing (MDM) Optical Power Splitter for System-on-Chip Networks.

We put forward and demonstrate a silicon photonics (SiPh)-based mode division multiplexed (MDM) optical power splitter that supports transverse-electric (TE) single-mode, dual-mode, and triple-mode (i.e., TE0, TE1, and TE2). An optical power splitter is needed for optical signal distribution and routing in optical interconnects. However, a traditional optical splitter only divides the power of the input optical signal. This means the same data information is received at all the output ports of the optical splitter. The powers at different output ports may change depending on the splitting ratio of the optical splitter. The main contributions of our proposed optical splitter are: (i) Different data information is received at different output ports of the optical splitter via the utilization of NOMA. By adjusting the power ratios of different channels in the digital domain (i.e., via software control) at the Tx, different channel data information can be received at different output ports of the splitter. It can increase the flexibility of optical signal distribution and routing. (ii) Besides, the proposed optical splitter can support the fundamental TE0 mode and the higher modes TE1, TE2, etc. Supporting mode-division multiplexing and multi-mode operation are important for future optical interconnects since the number of port counts is limited by the chip size. This can significantly increase the capacity besides wavelength division multiplexing (WDM) and spatial division multiplexing (SDM). The integrated SiPh MDM optical power splitter consists of a mode up-conversion section implemented by asymmetric directional couplers (ADCs) and a Y-branch structure for MDM power distribution. Here, we also propose and discuss the use of the Genetic algorithm (GA) for the MDM optical power splitter parameter optimization. Finally, to provide adjustable data rates at different output ports after the MDM optical power splitter, non-orthogonal multiple access-orthogonal frequency division multiplexing (NOMA-OFDM) is also employed. Experimental results validate that, in three modes (TE0, TE1, and TE2), user-1 and user-2 achieve data rates of (user-1: greater than 22 Gbit/s; user-2: greater than 12 Gbit/s) and (user-1: greater than 12 Gbit/s; user-2: 24 Gbit/s), respectively, at power-ratio (PR) = 2.0 or 3.0. Each channel meets the hard-decision forward-error-correction (HD-FEC, i.e., BER = 3.8 × 10-3) threshold. The proposed method allows flexible data rate allocation for multiple users for optical interconnects and system-on-chip networks.

2.4-Tb/s/λ*km fundamental mode transmission over OM2 fiber employing Kramers-Kronig receiver.

We propose a digital-carrier Kramers-Kronig (DC-KK) scheme based high-speed multimode fiber short-reach optical interconnect system with fundamental mode transmission. After optimization of the parameters, including the roll-off factor of the root-raised-cosine (RRC) filter, and the guard interval (GI) between signal and carrier tone, as well as the carrier signal power ratio (CSPR), 200-Gb/s 32-quadrature amplitude modulation (32QAM) signal transmission over 12-km OM2 fiber has been experimentally demonstrated with a bit error ratio (BER) below the soft-decision forward error correction (SD-FEC) threshold of 4 × 10-2. To the best of our knowledge, this is the highest experimental record of single lambda bitrate-distance-product (SLBDP) achieved by direct-detection (DD)-based transmission over a standard multimode fiber (MMF). The proposed scheme has potential to improve the system performance without replacing massive deployed legacy MMFs for future large-capacity data center interconnects (DCIs).

Co-packaged optics (CPO): status, challenges, and solutions

Due to the rise of 5G, IoT, AI, and high-performance computing applications, datacenter traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three-fourths of the datacenter traffic resides within datacenters. The conventional pluggable optics increases at a much slower rate than that of datacenter traffic. The gap between application requirements and the capability of conventional pluggable optics keeps increasing, a trend that is unsustainable. Co-packaged optics (CPO) is a disruptive approach to increasing the interconnecting bandwidth density and energy efficiency by dramatically shortening the electrical link length through advanced packaging and co-optimization of electronics and photonics. CPO is widely regarded as a promising solution for future datacenter interconnections, and silicon platform is the most promising platform for large-scale integration. Leading international companies (e.g., Intel, Broadcom and IBM) have heavily investigated in CPO technology, an inter-disciplinary research field that involves photonic devices, integrated circuits design, packaging, photonic device modeling, electronic-photonic co-simulation, applications, and standardization. This review aims to provide the readers a comprehensive overview of the state-of-the-art progress of CPO in silicon platform, identify the key challenges, and point out the potential solutions, hoping to encourage collaboration between different research fields to accelerate the development of CPO technology.Graphical

Ultrafast Carbon Nanotube Photodetectors with Bandwidth over 60 GHz

The future interconnect links in intra- and inter-chip require the photodetector with high bandwidth, ultra-wide waveband, compact footprint, low-cost, and compatible integration process with silicon complementary metal-oxide-semiconductor (CMOS) technology. Here, we demonstrate a CMOS-compatible carbon nanotube (CNT) photodetector that exhibits high responsivity, high bandwidth and broad spectral operation over all optical telecommunication band based on high-purity CNT arrays. The ultrafast CNT photodetector demonstrates the 100 Gbit/s Nyquist-shaped on-off-keying (OOK) signal transmission, which can address the demand for high-speed optical interconnects in and between data centers. Furthermore, the photodetector exhibits a bandwidth over 60 GHz by scaling down the active area to 20 {\mu}m2. As the CNT photodetectors are fabricated by doping-free process, it also provides a cost-effective solution to integrate CNT photonic devices with CNT-based CMOS integrated circuits. Our work paves a way for future CNT-based high-speed optical interconnects and optoelectronic integrated circuits (OEICs).

An optimal algorithm for energy harvesting in optical networks

Optical fiber cables, which make up the majority of the world's telecommunications infrastructure, now carry the vast majority of digital data. However, because to the Internet's exponential expansion and a slew of bandwidth-hungry new services like online gaming, 3D or high-definition television, and cloud computing, this infrastructure will soon run out of capacity. The growing need for faster transmission speeds by clients has led to the development of heterogeneous optical networks. High throughput, portability, and future information interconnects may all be accommodated by such a system. Delivering such high-capacity connections to a mobile client should need heterogeneous optical networks. Different multiple access user technologies have been suggested to meet the needs of a group of future heterogeneous optical network users. In order to address the high energy consumption, poor QoS and low resource utilization in cloud radio access network, this paper proposed a novel algorithm. The main idea is to allocate virtual resources with energy-awareness and hybrid energy supply. Then, the energy arrival and consumption models were established based on different network devices. Simulation results show that the proposed algorithm effectively improved the energy consumption performance and QoS as compared with existing methods.

Petabit-Scale Silicon Photonic Interconnects With Integrated Kerr Frequency Combs

Silicon photonics holds significant promise in revolutionizing optical interconnects in data centers and high performance computers to enable scaling into the Pb/s package escape bandwidth regime while consuming orders of magnitude less energy per bit than current solutions. In this work, we review recent progress in silicon photonic interconnects leveraging chip-scale Kerr frequency comb sources and provide a comprehensive overview of massively scalable silicon photonic systems capable of capitalizing on the large number of wavelengths provided by such combs. We first consider the high-level architectural constraints and then proceed to detail the corresponding fundamental device designs supported by both simulated and experimental results. Furthermore, the majority of experimentally measured devices were fabricated in a commercial 300 mm foundry, showing a clear path to volume manufacturing. Finally, we present various system-level experiments which illustrate successful proof-of-principle operation, including flip-chip integration with a co-designed CMOS application-specific integrated circuit (ASIC) to realize a complete Kerr comb-driven electronic-photonic engine. These results provide a viable and appealing path towards future co-packaged silicon photonic interconnects with aggregate per-fiber bandwidth above 1 Tb/s, energy consumption below 1 pJ/bit, and areal bandwidth density greater than 5 Tb/s/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Electrochemically reduced graphene oxide (ERGO)-Cu bilayer structure fabricated at room temperature for future interconnects.

Copper is an important interconnect material in integrated circuits (IC) due to its outstanding electrical and thermal properties. However, the development of the IC industry requires novel interconnect materials with higher conductivity. Here, uniform graphene oxide (GO) is deposited on copper by electrophoretic deposition (EPD) to obtain a GO-Cu bilayer structure at room temperature. (3-Mercaptopropyl) trimethoxysilane (MPTS) is self-assembled on the Cu anode surface, which protects the anode from oxidation during the EPD process. We find that the in situ hydrolysis of methoxy under the promotion of EPD voltage can facilitate the uniform deposition of GO and enhance the interface bonding force. In order to achieve better electrical performance, different reduction methods are conducted to reduce the structural disorder of GO. ERGO-Cu reduced by the electrochemical reduction method at -0.75 V for 1 min shows the lowest square resistance with a 16% resistance decrease compared with the GO-Cu structure and a 4.5% decrease compared with Cu substrate, due to the proper adjustment of the GO crystal structure. The room temperature fabricated ERGO-Cu bilayer structure provides a possibility for future interconnects with improved conductivity.

Small-signal stability analysis of the asymmetrical DC operation in HVDC networks

• Stability of interconnection of monopolar and bipolar HVDC stations is analysed. • A small-signal stability model for asymmetric DC operation studies is developed. • The model is validated with EMT dynamic simulation. • The findings are useful for systematic design of the HVDC grounding systems. • A controller is designed to enhance stability during asymmetric DC operation. The increase in High Voltage Direct Current (HVDC) projects favors their future interconnection to form regional networks, but this interconnection can be hindered by the lack of standardization in station's configuration and converter's differing grounding schemes. Whilst other studies have studied the effect of Direct Current (DC) asymmetrical operation, they are limited in their scope. This paper proposes a more realistic perspective, considering stations with different topologies, permanent DC asymmetries and the influence of the grounding systems. This more complex point of departure requires the re-examination of the modeling methods, from time-domain to frequency-domain. This paper proposes a small-signal stability model of the system, which is validated with the electromagnetic transient (EMT) dynamic simulations using PowerFactory. This model provides guidelines for designing the grounding impedance and allows the proper design of a specific controller to dampen the asymmetrical DC operation mode.