Future Field-effect Transistors Research Articles

Oxygen vacancy related hole fast trapping in high mobility cubic-Ge/ZrO2 interface

Ge has the potential to replace Si as the future field-effect transistors channel material due to its superior hole mobility, and cubic zirconia with high dielectric constant and small lattice mismatch can be selected as its oxide layer. At present, the mechanism of charge trapping caused by defects in the Ge oxide layer interface and bulk of such device has not been accurately analyzed. In our work, we have constructed the cubic Ge/ZrO2 interface, and studied the electronic structure and hole trapping characteristics of the interface structure by first-principles hybrid-functional calculations with Marcus theory. According to research oxygen vacancies with the different distances (abbr. d O-int) away from the Ge substrate, we confirm that the oxygen vacancy can act as a fast trap center to capture the hole of the valence band maximum (VBM) from Ge, resulting in the ultrafast or fast transient charge trapping in the high-k gate dielectric. We found that, when a given range of applied electric field, the hole trap is ultrafast with capture time of 10−6–10−5 when d O-int is within the range of 2–7 , and there is a 2–3 order of magnitude increases in capture time as d O-int exceeds 7 with the maximum capture cross section reducing substantially. Here, our work provides a clear and reasonable description of the distance-dependent hole trapping process at the Ge/high-k dielectrics metal-oxide-semiconductor (MOS) devices and provides significant support for solving the reliability problem of microelectronic devices.

Tunable electrical contacts in two-dimensional silicon field-effect transistors: The significance of surface engineering

Two-dimensional silicon (2D-Si) semiconductor is highly desired for future field-effect transistors (FETs) due to the inherent compatibility with the silicon-based technology. Interfacial contact represents a significant bottleneck restricting the performance of 2D-Si-based FETs. Here, by first-principles calculations and quantum transport simulations, we propose a strategy of surface engineering by F-, H-, and OH-passivation to tune the electronic properties, electrical contacts, and device performance of 2D FETs based on monolayer dumbbell silicene (LHD-Si). It is found that surface passivation performed in the LHD-Si FETs can significantly eliminate the metal-induced gap states and greatly relieve the Fermi level pinning by improving the pinning factor from 0.08 to 0.46. Importantly, the LHD-Si monolayers passivated with F and OH prefer to form n-type and p-type contacts with the representative metals (Bi, Al, Ag, Cu, Au, and Pt), respectively. Among them, Ohmic or quasi-Ohmic contacts (with very small Schottky barrier) are realized for F-passivated (OH-passivated) LHD-Si with Bi/Al/Ag (Cu/Au/Pt) electrodes. In the particular case of LHD-Si FETs with Cu electrodes, n-type, p-type, and ambipolar-type transfer behaviors are obtained for the F-, OH–, and H-passivation, respectively, demonstrating the dominant role played by electrical contacts in determining the Schottky barrier of the devices. This work highlights the significance of surface engineering in tuning the electrical contact and transport properties of doping-free 2D-Si-based FETs.

Solid Phase Epitaxy of Single Phase Two-Dimensional Layered InSe Grown by MBE.

Single-phase two-dimensional (2D) indium monoselenide (γ-InSe) film is successfully grown via solid phase epitaxy in the molecular beam epitaxy (MBE) system. Having high electron mobility and high photoresponsivity, ultrathin 2D γ-InSe semiconductors are attractive for future field-effect transistor and optoelectronic devices. However, growing single-phase γ-InSe film is a challenge due to the polymorphic nature of indium selenide (γ-InSe, α-In2Se3, β-In2Se3, γ-In2Se3, etc.). In this work, the 2D α-In2Se3 film was first grown on a sapphire substrate by MBE. Then, the high In/Se ratio sources were deposited on the α-In2Se3 surface, and an γ-InSe crystal emerged via solid-phase epitaxy. After 50 min of deposition, the initially 2D α-In2Se3 phase was also transformed into a 2D γ-InSe crystal. The phase transition from 2D α-In2Se3 to γ-InSe was confirmed by Raman, XRD, and TEM analysis. The structural ordering of 2D γ-InSe film was characterized by synchrotron-based grazing-incidence wide-angle X-ray scattering (GIWAXS).

High‐Performance Monolayer SiMe‐Graphene n‐Type Field‐Effect Transistors with Low Supply Voltage and High On‐State Current in Sub‐5 nm Gate Length

AbstractWith the development of device miniaturization, traditional Si‐based field effect transistors (FETs) are approaching their scaling limits. It is necessary to find more alternative materials to improve the performance of FETs. 2D semiconductors attract great attention for channel material due to their atomic‐scale smoothness and dangling‐bond‐free surface, and the gate electrostatic properties and charge carrier mobility are better than traditional 3D Si‐based semiconductor. In this paper, using density functional theory combined with nonequilibrium Green's function formalism, the electronic properties and device performance of sub‐5 nm monolayer SiMe‐graphene n‐type field‐effect transistors are evaluated. Remarkably, the on‐state current value of the FET can reach 3070 µA µm−1, which greatly surpasses most of reported FETs based on other 2D semiconductors. In addition, the on‐state current, power dissipation, and delay time of the SiMe‐graphene FETs satisfy the high‐performance requirements of the 2020 International Roadmap for Device and Systems under different supply voltages, which indicates that the FETs can work at different operating frequencies and power consumption. Moreover, via controlling electrode doping concentration, the channel length can be reduced to 4 nm. In total, the SiMe‐graphene is a favorable channel material for future FETs devices.

Assessing the role of quantum effects in two-dimensional heterophase MoTe2 field effect transistors

The two-dimensional (2D) transition metal dichalcogenides (TMDs) have been proposed as candidates for the channel material in future field effect transistor designs. The heterophase design, which utilizes the metallic T or ${\mathrm{T}}^{\ensuremath{'}}$ phase of the TMD as contacts to the semiconducting H-phase channel, has shown promising results in terms of bringing down the contact resistance of the device. In this work, we use ab-initio calculations to demonstrate how atomic-scale and quantum effects influence the ballistic transport properties in such heterophase transistors with channel lengths up to 20 nm. We investigate how the charge transfer depends on the carrier density both in ${\mathrm{T}}^{\ensuremath{'}}\text{\ensuremath{-}}\mathrm{H} {\mathrm{MoTe}}_{2}$ Schottky contacts and in planar ${\mathrm{T}}^{\ensuremath{'}}\text{\ensuremath{-}}\mathrm{H}\text{\ensuremath{-}}{\mathrm{T}}^{\ensuremath{'}} {\mathrm{MoTe}}_{2}$ transistors. We find that the size of the Schottky barrier and the charge transfer is dominated by the local atomic arrangements at the interface and the doping level. Furthermore, two types of quantum states have a large influence on the charge transport: Interface states and standing waves in the semiconductor due to quantum confinement. We find that the latter can be associated with rises in the current by more than an order of magnitude due to resonant tunneling. Our results demonstrate the quantum mechanical nature of these 2D transistors and highlight several challenges and possible solutions for achieving a competitive performance of such devices.

Vapor-Phase Passivation of Chlorine-Terminated Ge(100) Using Self-Assembled Monolayers of Hexanethiol.

Continued scaling of electronic devices shows the need to incorporate high mobility alternatives to silicon, the cornerstone of the semiconductor industry, into modern field effect transistor (FET) devices. Germanium is well-poised to serve as the channel material in FET devices as it boasts an electron and hole mobility more than twice and four times that of Si, respectively. However, its unstable native oxide makes its passivation a crucial step toward its potential integration into future FETs. The International Roadmap for Devices and Systems (IRDS) predicts continued aggressive scaling not only of the device size but also of the pitch in nanowire arrays. The development of a vapor-phase chemical passivation technique will be required to prevent the collapse of these structures that can occur because of the surface tension and capillary forces that are experienced when tight-pitched nanowire arrays are processed via liquid-phase chemistry. Reported here is a vapor-phase process using hexanethiol for the passivation of planar Ge(100) substrates. Results benchmarking it against its well-established liquid-phase equivalent are also presented. X-ray photoelectron spectroscopy was used to monitor the effectiveness of the developed vapor-phase protocol, where the presence of oxide was monitored at 0, 24, and 168 h. Water contact angle measurements compliment these results by demonstrating an increase in hydrophobicity of the passivated substrates. Atomic force microscopy monitored the surface topology before and after processing to ensure the process does not cause roughening of the surface, which is critical to demonstrate suitability for nanostructures. It is shown that the 200 min vapor-phase passivation procedure generates stable, passivated surfaces with less roughness than the liquid-phase counterpart.

Rethinking the Characterization of Nanoscale Field-Effect Transistors: A Universal Approach.

Standard methods for calculating transport parameters in nanoscale field-effect transistors (FETs), namely carrier concentration and mobility, require a linear connection between the gate voltage and channel conductance; however, this is often not the case. One reason often overlooked is that shifts in chemical and electric potential can partially compensate each other, commonly referred to as quantum capacitance. In nanoscale FETs, capacitance is often unmeasurable and an analytical formula is required, which assumes the conducting channel as metallic and common methods of determining threshold voltage no longer couple properly into transport equations. As present and future FET structures become smaller and have increased channel-gate coupling, this issue will render standard methods impossible to use. This work discusses the validity of common methods of characterization for nanoscale FETs, develops a universal model to determine transport properties by only measuring the threshold voltage of an FET and presents a new parameter to easily classify FETs as either quantum capacitance-limited or metallic approximated charge transport. Also considered in this work is electrical hysteresis from trap states and, in combination with the proposed universal model, novel techniques are introduced to measure and remove the errors associated with these effects often ignored in literature.

Intriguing field-effect-transistor performance of two-dimensional layered and crystalline CrI3

There are many candidate materials that can be used as channel materials for the next-generation field effect transistors (FETs). CrI3 is one of the particular candidates for application in FET, because it is a two-dimensional (2D) ferromagnet and has giant tunneling magnetoresistance. The ferromagnetic nature extends to not only electronics but also spintronics. In this study, the large-area, layered, and crystalline 2D CrI3 were synthesized by horizontal Bridgman method. The suspended CrI3 FETs were fabricated for explorations of intrinsic electron transport in the CrI3 channel and of electrical contact problems. The suspended FET structure lets the CrI3 channel free from trapping charges in the SiO2-capped Si substrate. The on–off ratio of the suspended CrI3 FET is up to 104, making the 2D layered CrI3 potential for future FETs. The investigations of the mobility and the interface-trap density at various temperatures reveal that the trapping charges as well as the interface-trap densities are increased with further gas adsorption on the surface of the CrI3 flake. The performance of the suspended CrI3 FET can be improved, if the gas adsorption problem can be carefully treated.

Pressure-induced metallization of black arsenic

Black arsenic (bAs), a cousin of black phosphorus, has attracted increasing attention due to its excellent physical properties such as high carrier mobility and high on/off ratio, which provide new opportunities for future field-effect transistors and photodetectors. As a clear and powerful means, hydrostatic pressure is commonly used to tune the structure and electronic properties of materials. However, there have been few reports to date about bAs under pressure. In this work, a theoretical study is presented on the structure, stability, and electronic properties of bAs under high pressure. The calculation results show that bAs becomes unstable at pressures above 3 GPa. A transition from direct band gap to indirect band gap occurs at 1.2 GPa, and with a further increase of pressure, bAs undergoes a phase transition from semiconductor to metal at a critical pressure of 2.2 GPa. In addition, the carrier effective masses can be modulated slightly by hydrostatic pressure.

3D GaN nanoarchitecture for field-effect transistors

Abstract The three-dimensionality of 3D GaN field-effect transistors (FETs) provides them with unique advantages compared to their planar counterparts, introducing a promising path towards future FETs beyond Moore's law. Similar to today's Si processor technology, 3D GaN FETs offer multi-gate structures that provide excellent electrostatic control over the channel and enable very low subthreshold swing values close to the theoretical limit. Various concepts have been demonstrated, including both lateral and vertical devices with GaN nanowire (NW) or nanofin (NF) geometries. Outstanding transport properties were achieved with laterally contacted NWs that were grown in a bottom-up approach and transferred onto an insulating substrate. For higher power application, vertical FETs based on regular arrays of GaN nanostructures are particularly promising due to their parallel integration capability and large sidewall surfaces, which can be utilized as channel area. In this paper, we review the current status of 3D GaN FETs and discuss their concepts, fabrication techniques, and performances. In addition to the potential benefits, reliability issues and difficulties that may arise in complex 3D processing are discussed, which need to be tackled to pave the way for future switching applications.

Computational Study of MoS2/HfO2 Defective Interfaces for Nanometer-Scale Electronics.

Atomic structures and electronic properties of MoS2/HfO2 defective interfaces are investigated extensively for future field-effect transistor device applications. To mimic the atomic layer deposition growth under ambient conditions, the impact of interfacial oxygen concentration on the MoS2/HfO2 interface electronic structure is examined. Then, the effect on band offsets (BOs) and the thermodynamic stability of those interfaces is investigated and compared with available relevant experimental data. Our results show that the BOs can be modified up to 2 eV by tuning the oxygen content through, for example, the relative partial pressure. Interfaces with hydrogen impurities as well as various structural disorders were also considered, leading to different behaviors, such as n-type doping, or introducing defect states close to the Fermi level because of the formation of hydroxyl groups. Then, our results indicate that for a well-prepared interface the electronic device performance should be better than that of other interfaces, such as III–V/high-κ, because of the absence of interface defect states. However, any unpassivated defects, if present during oxide growth, strongly affect the subsequent electronic properties of the interface. The unique electronic properties of monolayer-to-few-layered transition-metal dichalcogenides and dielectric interfaces are described in detail for the first time, showing the promising interfacial characteristics for future transistor technology.

High‐Performance Field Effect Transistors Using Electronic Inks of 2D Molybdenum Oxide Nanoflakes

Planar 2D materials are possibly the ideal channel candidates for future field effect transistors (FETs), due to their unique electronic properties. However, the performance of FETs based on 2D materials is yet to exceed those of conventional silicon based devices. Here, a 2D channel thin film made from liquid phase exfoliated molybdenum oxide nanoflake inks with highly controllable substoichiometric levels is presented. The ability to induce oxygen vacancies by solar light irradiation in an aqueous environment allows the tuning of electronic properties in 2D substoichiometric molybdenum oxides (MoO3−x). The highest mobility is found to be ≈600 cm2 V−1 s−1 with an estimated free electron concentration of ≈1.6 × 1021 cm−3 and an optimal IOn/IOff ratio of >105 for the FETs made of 2D flakes irradiated for 30 min (x = 0.042). These values are significant and represent a real opportunity to realize the next generation of tunable electronic devices using electronic inks.

Scaling laws of band gaps of phosphorene nanoribbons: A tight-binding calculation

In this study, we analyze the band structure, the state characterization, and electronic transport of monolayer black phosphorus (phosphorene) zigzag nanoribbons (zPNRs) and armchair nanoribbons (aPNRs), using five-parameter tight-binding (TB) approximation. In zPNRs, the ratio of the two dominant hopping parameters indicates the possibility of a relativistic dispersion relation and the existence of a pair of separate quasi-flat bands at the Fermi level. Moreover, the corresponding states are edge localized if their bands are well separated from the valence and conduction bands. We also investigated the scaling laws of the band gaps versus ribbon widths for the armchair and zigzag phosphorene nanoribbons. In aPNRs, the transverse electric field along the ribbon width enhances the band gap closure by shifting the energy of the valence and conduction band edge states. For zPNRs, a gap occurs at the middle of the relatively degenerate quasi-flat bands; thus, these ribbons are a promising candidate for future field-effect transistors.

Crystallization of HfO2 in InAs/HfO2 core–shell nanowires

We report the impact of deposition parameters on the structure of HfO2 covering InAs nanowires (NWs) being potential candidates for future field-effect transistors (FETs). Molecular beam epitaxial-grown Au-free InAs NWs were covered with HfO2 deposited by atomic-layer deposition. The impact of the film thickness as well as the deposition temperature on the occurrence and amount of crystalline HfO2 regions was investigated by high-resolution transmission electron microscopy (TEM) and x-ray diffraction. Compared to the deposition on planar Si substrates, the formation probability of crystalline HfO2 on InAs NWs is significantly enhanced. Here, even 3 nm thick films deposited at 250 °C are partly crystalline. Similarly, a low deposition temperature of 125 °C does not result in completely amorphous 10 nm thick HfO2 films, they contain monoclinic as well as orthorhombic HfO2 nanocrystals. Combining HfO2 and Al2O3 into a laminate structure is capable of suppressing the formation of crystalline HfO2 grains.

Gap Opening of Graphene by Dual FeCl3-Acceptor and K-Donor Doping

The band gap opening of graphene is the most desired property in the device industry because it is vital to the application of graphene as a logical device of semiconductors. Here, we show how to make a reasonably wide band gap in graphene. This is accomplished with bilayer graphene (BLG) dual-doped with FeCl3-acceptor and K-donor. To elucidate this phenomenon, we employed the first-principles method taking into account van der Waals interaction. For the FeCl3 adsorbed BLG, the optimal distance between the adjacent graphene and FeCl3 layers is 4.6–4.8 Å, consistent with experiments. Due to the high electronegativity of FeCl3, these graphene layers are hole-doped. The dual-doped BLG gives a band gap of 0.27 eV due to broken symmetry, with a Dirac point shift by −0.09 eV. This increased band gap and proper Dirac point shift could make the dual-doped BLG useful for applications toward future field effect transistor devices.

Interfacial atomic structures, energetics and band offsets of Ge:ZrO2 interfaces

Future field effect transistors may use germanium as a high mobility channel material instead of silicon, and high dielectric constant (κ) oxides such as ZrO2 and HfO2 instead of SiO2 as the gate dielectric. First principles calculations of the polar (100) and nonpolar (110) Ge:ZrO2 interfaces are presented. A number of interface configurations that satisfy the valence bonding requirements are constructed and their relaxed structures, total energies, interface electronic states, and band offsets are calculated. For the polar (100) interfaces, the results are quite similar to those of (100) Si:ZrO2. There are numerous semiconducting O-terminated interfaces. The most stable O-terminated interface for a 1×1 surface unit cell has three coordinated oxygen sites. The interface with a tenfold coordinated Zr is the most stable metal-terminated interface, but it is metallic which makes this interface not useful for devices. The band offsets of the O-terminated interfaces have a relatively narrow range, whereas the Zr-terminated band offsets exhibit a range of 0.9eV.

Band offsets of high K gate oxides on high mobility semiconductors

High mobility semiconductors such as Ge and III–V compounds will be used in future field effect transistors, with the appropriate gate dielectric. The dielectrics must have band offsets over 1 eV to inhibit leakage. The band offsets of various gate dielectrics including HfO 2, Al 2O 3, Gd 2O 3, Si 3N 4 and SiO 2 on III–V semiconductors such as GaAs, InAs, GaSb and GaN have been calculated using the method of charge neutrality levels. Generally, the conduction band offsets are found to be over 1 eV, so they should inhibit leakage for these dielectrics. There is reasonable agreement to experiment where it exists, although the GaAs:SrTiO 3 case is even worse in experiment.

Comparison of Properties of an Al2O3 Thin Layers Grown with Remote O2 Plasma, H2O , or O3 as Oxidants in an ALD Process for HfO2 Gate Dielectrics

High- dielectric films were grown by an atomic layer deposition (ALD) technique using and on bare Si and various -passivated Si wafers. The films were grown by different ALD processes using trimethylaluminum as the Al precursor and remote plasma, , and , as the oxidants. The electrical and structural properties of the stacked films were compared. appeared to be the most appropriate oxidant for growing films as the interlayer with superior quality and thermal stability due to its high oxidation power. The stack exhibited an extremely low leakage current density suggesting its significance as a gate dielectric film for future field effect transistors. However, the stacked films with plasma or grown layer showed an unstable flatband behavior and serious charge injection properties that precluded their adoption to metal-oxide-semiconductor field effect transistor devices.

Silicon MOSFETs on insulator with lithography-independent 100 nm channel length

Future field-effect transistors should have control regions — also called channels or barriers — of a few tens of nanometers to achieve a transconductance of 1 S/mm and beyond, ƒ T of 100 GHz and safe operating voltages beyond 1 V. This paper presents two approaches for the fabrication of such MOS transistors in silicon on insulator (SOI) on today's average technology lines without resorting to nanometer lithography, but rather using differential doping available in reduced-temperature epitaxy and implantation. With 6 nm oxynitride gate dielectrics, inner transconductances of 700 mS/mm at room temperature are reported.

Lithography-independent nanometer silicon MOSFETs on insulator

Future field-effect transistors should have control regions-also called channels or barriers-of a few tens of nanometers to achieve a transconductance of 1 Siemens per mm and beyond, f/sub T/ of 100 GHz and safe operating voltages beyond 1 V. This paper presents two approaches for the fabrication of such MOS transistors in silicon on insulator (SOI) on today's average technology lines without resorting to nanometer lithography, but rather using differential doping available in reduced temperature epitaxy and implantation. With 6 nm oxinitride gate dielectrics, inner transconductances of 700 mS/mm at room temperature are reported.