Fundamental Frequency Negative Sequence Research Articles

Quasi Type-1 PLL With Tunable Phase Detector for Unbalanced and Distorted Three-Phase Grid

Out of various moving average filter (MAF)-based phase-locked-loop (PLL), quasi type-1 PLL (QT1-PLL) is widely adopted due to its fast dynamic performance, implementation simplicity, and harmonics rejection abilities. However, the performance of QT1-PLL deteriorates in the presence of an off-nominal frequency unbalanced grid voltage component. Moreover, the sensitivity towards the fundamental frequency negative sequence (FFNS) component is high. Hence, this paper proposes a novel enhanced QT1-PLL solution that is insensitive to unbalance in the grid voltage signal during off-nominal frequency conditions. The proposed adaptive phase detector makes it possible to estimate both the fundamental frequency positive sequence (FFPS) and FFNS components with a high degree of immunity against harmonics. Notably, the pre-loop separation of the FFPS and the FFNS components helps suppress the second harmonic oscillations for improving the parameter estimation accuracy. The loop-filter design of QT1-PLL remains unaffected and requires a proportional gain to estimate the fundamental phase and frequency information. To address the DC offset issue, a modified delayed signal cancellation method is also proposed, which can theoretically eliminate the DC offset for any arbitrary delay length. A small-signal model of the proposed PLL is developed for the sake of stability analysis. Comparative numerical simulation and experimental results are provided with various variants of QT1-PLLs to demonstrate the performance improvement achieved with the proposed technique.

A Third-Order MAF Based QT1-PLL That is Robust Against Harmonically Distorted Grid Voltage With Frequency Deviation

The quasi-type-l phase-locked loop (QT1-PLL) is a grid synchronization technique that has become very popular in recent years thanks to its attractive performance such as easy implementation, fast dynamic response, and good accuracy in steady-state operation. However, it is still vulnerable to operation under harmonically distorted grid voltages with frequency drift. This paper proposes a novel QT1-PLL based synchronization algorithm that makes an appropriate combination of two filters’ types: an in-loop third-order moving average filter (MAF) with a reduced window width, and a simplified second-order fast delayed signal cancellation (FDSC) based prefiltering stage. The proposed PLL is named third-order MAF based QT1-PLL (TQT1-PLL). Though both TQT1-PLL's filters do not need any adaptive algorithm, it is able to reject non-triplen odd-harmonics and the fundamental frequency negative sequence (FFNS) even under grid frequency drift. Its correct operation is confirmed through numerical simulations and real-time implementation on a digital signal processor (DSP). Moreover, the obtained results confirm its ability to reduce the ripple in the estimated frequency and phase under distorted grid voltages and off-nominal frequency operation. Authors show also through an analytical development that the topology of the proposed TQT1-PLL can be extended to enable the rejection of the DC-offset.

A fast hybrid PLL with an adaptive all-pass filter under abnormal grid conditions

Recently, various phase locked loop (PLL) methods have been improved for a reliable and robust synchronization under non-ideal grid conditions. One of the PLLs is a hybrid PLL (HPLL) which is an improved structure of the quasi-type-1 PLL (QT1-PLL) method. In this paper, an enhanced HPLL that offers both fast transient response and increased disturbance rejection capability for dominant harmonics is proposed. The proposed PLL includes adaptive all-pass-filters (APFs) in pre-filtering stage to eliminate fundamental frequency negative sequence (FFNS) component. Thus, window-width of the moving average filter (MAF) is reduced by three times compared with the HPLL by means of removing the FFNS component. So, the proposed PLL, which is called fast-hybrid PLL (FH-PLL), considerably ensures a fast transient response. Also, in case of grid faults (for example, type-B, type-C, type-D, and etc.), at the same time frequency change occurs, the FH-PLL completely blocks the FFNS component by means of using adaptive DAPF. In this study, it is experimentally implemented HPLL, QT1-PLL, and the proposed FH-PLL methods. The effectiveness of the FH-PLL is verified owing to experimental results and comparison with the QT1-PLL and HPLL.

A Novel Grid Synchronization Method Based on Hybrid Filter Under Distorted Voltage Conditions

The phase-locked accuracy of conventional phase-locked method is reduced when the grid voltage contains fundamental frequency negative sequence(FFNS) component, harmonic component, and DC offset component. Aiming at this problem, a novel adaptive notch filter (NANF) is proposed, and a dual NANF (DNANF) structure is designed to eliminate the FFNS component and extract the fundamental frequency positive sequence(FFPS) component based on NANF. Furthermore, dc DNANF with DC offset rejection capability is proposed by adopting DNANF. Then a novel hybrid filter in dq -frame is designed by combining dc DNANF and the cascaded delay signal cancellation operator filter whose delay parameters are 4 and 24 in dq -frame ( dq CDSC4,24). Meanwhile, a new SRF-PLL design method is proposed based on the novel hybrid filter. This proposed method employs dq CDSC4,24 to separate the positive and negative sequences of the voltage and eliminate the high frequency harmonics in the grid voltage, and uses dc DNANF to reject the DC offset, so as to achieve the accurate acquisition of the fundamental voltage information under distortion and unbalanced grid. Simulation and experimental results show that compared with the conventional SRF-PLL methods, the proposed method can obtain faster phase tracking speed, better phase-locked effect, faster dynamic response, and better stability.

A Hybrid Filtering Technique-Based PLL Targeting Fast and Robust Tracking Performance under Distorted Grid Conditions

In most grid-connected power converter applications, the phase-locked loop (PLL) is probably the most widespread grid synchronization technique, owing to its simple implementation. However, its phase-tracking performance tends to worsen when the grid voltage is under unbalanced and distorted conditions. Many filtering techniques are utilized to solve this problem, however, at the cost of slowing down the transient response. It is a major challenge for PLL to achieve a satisfactory dynamic performance without degrading its filtering capability. To tackle this challenge, a hybrid filtering technique is proposed in this paper. Our idea is to eliminate the fundamental frequency negative sequence (FFNS) and other harmonic sequences at the prefiltering stage and inner loop of PLL, respectively. Second-order generalized integrators (SOGIs) are used to remove FFNS before the Park transformation. This makes moving average filters (MAFs) eliminate other harmonics with a narrowed window length, which means the time delay that is caused by MAFs is reduced. The entire hybrid filtering technique is included in a quasi-type-1 PLL structure (QT1-PLL), which can provide a rapid dynamic behavior. The small-signal model of the proposed PLL is established. Based on this model, the parameter design guidelines targeting the fast transient response are given. Comprehensive experiments are carried out to confirm the effectiveness of our method. The results show that the settling time of the proposed PLL is less than one grid cycle, which is shorter than most of the widespread PLLs. The harmonic rejection capability is also better than other methods, under both nominal and adverse grid conditions.

An Efficient Hybrid Filter-Based Phase-Locked Loop under Adverse Grid Conditions

Synchronous-reference-frame phase-locked loop (SRF-PLL) is widely used in grid synchronization applications. However, under unbalanced, distorted and DC offset mixed grid conditions, its performance tends to worsen. In order to improve the filtering capability of SRF-PLL, a modified three-order generalized integrator (MTOGI) with DC offset rejection capability based on conventional three order generalized integrator (TOGI) and an enhanced delayed signal cancellation (EDSC) are proposed, then dual modified TOGI (DMTOGI) filtering stage is designed and incorporated into the SRF-PLL control loop with EDSC to form a new hybrid filter-based PLL. The proposed PLL can reject the fundamental frequency negative sequence (FFNS) component, DC offset component, and the rest of harmonic components in SRF-PLL input three-phase voltages at the same time with a simple complexity. The proposed PLL in this paper has a faster transient response due to the EDSC reducing the number of DSC operators. A small-signal model of the proposed PLL is derived. The stability is analyzed and parameter design guidelines are given. Experimental results are included to validate the effectiveness and robustness of the proposed PLL.

A Novel Hybrid Filter-Based PLL to Eliminate Effect of Input Harmonics and DC Offset

Synchronous reference frame phase locked loop (SRF-PLL) is widely used for grid synchronization and control in grid-connected applications. A major problem with SRF-PLL is how to improve its dynamic performance and filtering capability under complex grid conditions such as unbalance, distortion, and dc offset mixing without affecting its phase tracking performance and stability. In order to achieve this goal, a novel second-order generalized integrator (NSOGI) and a modified NSOGI (MNSOGI) with dc offset rejection capability based on NSOGI are proposed, and then, an effective hybrid filter is designed and incorporated into the inner loop of a SRF-PLL. The proposed hybrid filter is a combination of a dual MNSOGI and a moving average filter (MAF), it can block the fundamental frequency negative sequence component, dc offset component, and the rest of harmonic components in the SRF-PLL input three-phase voltages at the same time with a simple complexity. The proposed PLL in this paper has a faster transient response due to reducing the window length of the MAF. A small-signal model of the proposed PLL is derived. The stability is analyzed, and parameters design guidelines are given. The effectiveness of the proposed PLL is confirmed through simulation experimental results.

Performance Improvement of Quasi-Type-1 PLL by using a Complex Notch Filter

The synchronous reference frame phase-locked loop (SRF-PLL) is widely used for synchronization applications. However, it suffers from a poor performance under unbalanced and distorted grid conditions. To improve the filtering capability of SRF-PLL, moving average filter (MAF) is incorporated into its control loop at the cost of a slow transient response of PLL in recently published literature. To further improve their dynamic performance without compromising the disturbance rejection capability and stability, a novel PLL based on quasi-type-1 PLL structure is proposed in this paper. A complex notch filter is incorporated into the QT1-PLL to eliminate the fundamental frequency negative sequence voltage component. The window length of MAF in QT1-PLL is reduced. And MAF is responsible for rejecting the rest of harmonics. Parameter design guidelines are suggested to obtain the minimum settling time for both phase jump and frequency jump. The proposed PLL provides a faster transient response with higher stability margins. The effectiveness of the proposed PLL is confirmed through simulation and experimental results and comparison with advanced PLLs.