Fundamental Circuit Research Articles

Double‐gate line‐tunneling field‐effect transistor devices for superior analog performance

SummaryThis paper presents a double‐gate line‐tunneling field‐effect transistor (DGLTFET) device optimized for superior analog performance. DGLTFET has thrice the on currents Ion, at least one order lower off currents I o f f, twice the transconductance gm, at least two orders higher output resistance ro, and at least two orders higher overall intrinsic gain gmro than the equivalent metal‐oxide‐semiconductor field‐effect transistor (MOSFET) having the same width at the same technology node. The proposed device, being a double‐gate (DG) structure, exhibits extremely high vertical fields which ensures that line‐tunneling dominates over the point‐tunneling by several orders. This eliminates the notorious “hump” or the “kink” effects observed in conventional LTFET characteristics, which are detrimental for analog applications. In this work, we have optimized the DGLTFET device by changing critical parameters like the epi‐layer thickness and its doping concentration, which have serious influence on the line‐tunneling behavior. Optimization of the critical parameters for enhanced line‐tunneling leads to improved analog performance parameters like gm and ro, and finally, superior analog circuits. The performance of the DGLTFET was benchmarked with the equivalent MOSFET in fundamental analog VLSI circuits, namely, CS amplifier (both resistive and cascode loads), current mirror (both single‐stage and cascode configurations), and a two‐stage op‐amp. This paper shows that the DGLTFET CS amplifier has a gain‐BW product or unity‐gain BW fT of 15 GHz, while that of MOSFET CS amplifier with the same bias current is 10 GHz. The DGLTFET current mirror has at least three orders of magnitude higher ro than the corresponding MOSFET current mirror. Similarly, the common‐mode rejection ratio (CMRR) of the DGLTFET op‐amp is 57 dB compared to the CMRR of 33.5 dB of the equivalent design in standard 45‐nm complementary metal‐oxide semiconductor (CMOS) technology. The 45‐nm library is the lowest industry‐standard technology node currently available free for academic licenses in the public domain; hence, the benchmarking for validation was carried out at 45 nm. However, the claims/investigations made in this work are also valid for lower technologies, and related results are excluded in this report keeping the manuscript length in mind.

Poziom zapewnienia bezpieczenstwa - PL Czesc I – Podstawowy parametr funkcji bezpieczenstwa maszyny (SF)

The paper discusses the concept of the safety function for the machine control circuit, which is one of the basic concepts that allow to design machines in accordance with the safety requirements. The basics of the architecture of systems implementing safety functions in machines were also discussed. Using the example of the fundamental emergency stop circuit, the basics of the reliability parameters for electromechanical components are explained. The concept of forced contact guidance is also explained. The basic formulas are given and the basis for further clarification of the performance level (PL) is prepared.

A method to estimate parameters of five-phase induction machines including the third-harmonic airgap field

We propose a method to estimate all electrical parameters of five-phase induction motors based on a new concept of instantaneous impedance. Only stator voltages and currents acquired during no-load startup tests are required to determine the parameters of the fundamental and third-harmonic equivalent circuits. Additional quantities, such as rotor speed and electromagnetic torque, are also estimated from measurements. Unlike similar procedures, the parameters of the third-harmonic circuit are estimated separately from the parameters of the fundamental circuit, thus making the estimation more accurate. To experimentally validate the method, we tested a 4.5-kW and a 5.5-kW prototype using sinusoidal as well as trapezoidal voltages generated by a static converter. One of the main advantages of the proposed procedure is the possibility of using data acquired also with a static converter. Besides, to validate the method as well as to assess the accuracy of the estimated parameters, we first simulated the machine behavior using the estimated parameters and the measured stator voltages as input and subsequently compared the simulated currents with those acquired during no-load startup and load tests. Furthermore, we implemented a closed-loop Rotor Field Oriented Control (RFOC) scheme using both calculated and estimated parameters and then compared the controller performance with both sets of parameters. The practical results demonstrate not only that the method provides accurate estimates for all parameters but also that the use of the estimated parameters can improve the performance of the controller.

Memristor Modeling Using the Modified Nodal Analysis Approach

The memristor has long been presented as the fourth fundamental circuit element alongside the resistor, the capacitor, and the inductor. As the future of computing heads toward neuromorphic circuits, there has been a renewed interest in the modeling and simulation of memristors which have emerged as promising key components in the design of these systems. Despite such critical applications, very few models have been presented in the literature that allow for the automated and flexible integration of memristors in different simulators. In this article, three different models of the memristor are presented using the modified nodal analysis (MNA) formulation technique. Each stamp is tested and compared with a theoretical model of the memristor. Simulations are also performed on a memristor-based active high-pass filter circuit to demonstrate the accuracy of the model.

Characterization of three phase solid state VAR compensation scheme in three phase pulse width modulation voltage source inverter

The principle of a three phase solid state VAR compensation (SSVC) system that uses a three-phase pulse width-modulated (PWM) Voltage-Source Inverter (VSI) is presented and analyzed. The proposed SSVC system can compensate for leading and lagging displacement power factor and the PWM is used as a means of reducing the size of reactive components. The significant aspect of the presented VAR compensator is the adjustment of the angle difference between the static fundamental circuit output voltage and the utility supply voltage in order to optimize the alternating current (a.c.) power factor to a non-linear load. The SSVC system is analyzed under self-controlled DC bus voltage operating conditions. Other areas of investigation include the design of SSVC reactive components. The dynamic analysis is carried out in a d-q reference frame to verify the performance of the VAR compensator in terms of speed of response and stability. Analysis and stability plots generated confirm a high performance static VAR compensator. Finely, the findings of present research work were found within good agreement with some other workers.

U=RIsolve: A Web-Based Application for Learning Electrical Circuit Analysis [Education

Learning circuit analysis is often a challenging issue for Electrical Engineering undergraduate students. During the course's early stages, procedures such as the correct identification of Branches, Nodes and Loops, the expression of Kirchhoff Current and Voltage Laws, as well as the application of analysis/simplification Theorems and Algorithms, usually embed tricky and error-prone steps for beginners. While circuit simulators offer a validation for theoretical and experimental analysis, they do not explain how to obtain the results nor the fundamental laws supporting them. In this regard, a new web-based framework, - dubbed U=RIsolve (read as you resolve) - for teaching and self-learning the Node Voltage Method (NVM) is presented in this paper. The U=RIsolve application goes far beyond the capabilities of traditional circuit simulators, as it outputs the fundamental circuit information, the methodology, the equations and the results related to the NVM. An outlook of the application main features, user interface and usage in electrical circuit analysis is provided, along with the future implementations.

Emergent electromagnetic induction in a helical-spin magnet.

An inductor, one of the most fundamental circuit elements in modern electronic devices, generates a voltage proportional to the time derivative of the input current1. Conventional inductors typically consist of a helical coil and induce a voltage as a counteraction to time-varying magnetic flux penetrating the coil, following Faraday's law of electromagnetic induction. The magnitude of this conventional inductance is proportional to the volume of the inductor's coil, which hinders the miniaturization of inductors2. Here, we demonstrate an inductance of quantum-mechanical origin3, generated by the emergent electric field induced by current-driven dynamics of spin helices in a magnet. In microscale rectangular magnetic devices with nanoscale spin helices, we observe a typical inductance as large as -400nanohenry, comparable in magnitude to that of a commercial inductor, but in a volume about a million times smaller. The observed inductance is enhanced by nonlinearity in current and shows non-monotonous frequency dependence, both of which result from the current-driven dynamics of the spin-helix structures. The magnitude of the inductance rapidly increases with decreasing device cross-section, in contrast to conventional inductors. Our findings may pave the way to microscale, simple-shaped inductors based on emergent electromagnetism related to the quantum-mechanical Berry phase.

A Dream that has Come True: Chaos from a Nonlinear Circuit with a Real Memristor

In the last decade, researchers, who work in the field of nonlinear circuits, have the “dream” to use a real memristor, which is the only nonlinear fundamental circuit element, in a new or other reported nonlinear circuit in literature, in order to experimentally investigate chaos. With this intention, for the first time, a well-known nonlinear circuit, in which its nonlinear element has been replaced with a commercially available memristor (KNOWM memristor), is presented in this work. Interesting phenomena concerning chaos theory, such as period-doubling route to chaos, coexisting attractors, one-scroll and double-scroll chaotic attractors are experimentally observed.

Acute and Post-Traumatic Stress Disorders: A biased nervous system.

Acute stress disorder and post-traumatic stress disorder are generally triggered by an exceptionally intense threat. The consequences of this traumatogenic situation are explored here in chronological order, from exposure to the threat to development of symptoms. Such a situation may disrupt the equilibrium between two fundamental brain circuits, referred to as the "defensive" and "cognitive". The defensive circuit triggers the stress response as well as the formation of implicit memory. The cognitive circuit triggers the voluntary response and the formation of explicit autobiographical memory. During a traumatogenic situation, the defensive circuit could be over-activated while cognitive circuit is under-activated. In the most severe cases, overactivation of the defensive circuit may cause its brutal deactivation, resulting in dissociation. Here, we address the underlying neurobiological mechanisms at every scale: from neurons to behaviors, providing a detailed explanatory model of trauma.

Generalized Single Stage Class C Amplifier: Analysis from the Viewpoint of Chaotic Behavior

This paper briefly describes a recent discovery that occurred during the study of the simplest mathematical model of a class C amplifier with a bipolar transistor. It is proved both numerically and experimentally that chaos can be observed in this simple network structure under three conditions: (1) the transistor is considered non-unilateral, (2) bias point provides cubic polynomial feedforward and feedback transconductance, and (3) the LC tank has very high resonant frequency. Moreover, chaos is generated by an autonomous class C amplifier; i.e., an isolated system without a driving force is analyzed. By the connection of a harmonic input signal, much more complex behavior can be observed. Additionally, due to the high degree of generalization of the amplifier cell, similar fundamental circuits can be ordinarily found as subparts of typical building blocks of a radio frequency signal path.

Modeling of fundamental electronic circuits by the Euler method using the Python programming language

In this work three examples of textbook circuits (resistor-capacitor, resistor-inductor and resistor-inductor-capacitor) have been modeled by employing the Euler method for the approximate solution of differential equations using algorithms implemented in the Python programming language. The aim of this work was to demonstrate how simple, yet highly effective, algorithms can be neatly implemented in one of the currently most popular programming languages for scientific applications. At the same time, the visualization of the results allows for a detailed introduction to the properties of the circuits most frequently commented on in all the relevant textbooks. Our code, as provided to the reader, includes detailed comments, and can easily be modified to model other similar systems. Instructions on how to prepare tasks for students have been also provided.

Piezoelectric energy harvesting using macro fiber composite patches

Over the last decade, vibration energy harvesting has received substantial attention of many researchers. Piezoelectric materials are able to capture energy from ambient vibration and convert it into electricity which can be stored in batteries or utilized to power small electronic devices. In order to benefit from the 33-mode of the piezoelectric effect, interdigitated electrodes have been utilized in the design of macro fiber composites which are made of piezoelectric fibers of square cross sections embedded into an epoxy matrix material. This paper presents an analytical model of a macro fiber composite bimorph energy harvester using the 33-mode. The mixing rule is applied to determine the equivalent and homogenized properties of the macro fiber composite structures. The electromechanical properties of a representative volume element composed of piezoelectric fibers and an epoxy matrix between two successive interdigitated electrodes are coupled with the overall electro-elastodynamics of the harvester utilizing the Euler–Bernoulli theory. Macro fiber composite bimorph cantilevers with diverse widths are simulated for power generation when a resistive shunt loading is applied. Stress components in the Kapton layers, which are typically a part of any macro fiber composite patch, and in the bonding layers have been included in the model contrary to previously published studies. Variable tip mass, attached at the free end of the beam, is utilized in this paper to tune the resonance frequency of the harvester. The generated power at the fundamental short circuit and open circuit resonance frequencies of harvesters having three different widths is analyzed. It has been observed that higher electrical outputs are produced by the wider macro fiber composite bimorph using (M8528-P1 patches).

Recent Advances in Halide Perovskite Memristors: Materials, Structures, Mechanisms, and Applications

AbstractThe memristor is the fourth fundamental circuit element discovered after resistors, capacitors, and inductors. Although this concept has only been proposed in 1971 and confirmed in 2008, many materials with memristive properties have been found since 1962. Halide perovskites have been widely used in solar cells, and recently it has been found that they also possess good memristive properties. Different halide perovskites have been applied to memristors, including 3D organic–inorganic hybrid perovskites, 2D organic–inorganic hybrid perovskites, all‐inorganic cesium/rubidium lead halide perovskites, lead‐less and lead‐free perovskites, and halide perovskite quantum dots. Flexible and fiber‐shaped halide perovskite memristors have been fabricated. Several resistive switching mechanisms of halide perovskite memristors have been proposed, and the relationships between halide perovskite memristors and perovskite solar cells have been discussed. Based on halide perovskite memristors, light‐induced resistive switching and logic gate, high‐density and cross‐bar array data storage unit, and artificial synapse have been designed. Herein, recent advances in halide perovskite memristors are comprehensively and systematically reviewed. Finally, the current challenges and potential future directions in this field are discussed.

Mathematical analysis of memristor through fractal‐fractional differential operators: A numerical study

The newly generalized energy storage component, namely, memristor, which is a fundamental circuit element so called universal charge‐controlled mem‐element, is proposed for controlling the analysis and coexisting attractors. The governing differential equations of memristor are highly nonlinear for mathematical relationships. The mathematical model of memristor is established in terms of newly defined fractal‐fractional differential operators so called Atangana‐Baleanu, Caputo‐Fabrizio, and Caputo fractal‐fractional differential operator. A novel numerical approach is developed for the governing differential equations of memristor on the basis of Atangana‐Baleanu, Caputo‐Fabrizio, and Caputo fractal‐fractional differential operator. We discussed chaotic behavior of memristor under three criteria such as (i) varying fractal order, we fixed fractional order; (ii) varying fractional order, we fixed fractal order; and (ii) varying fractal and fractional orders simultaneously. Our investigated graphical illustrations and simulated results via MATLAB for the chaotic behaviors of memristor suggest that newly presented Atangana‐Baleanu, Caputo‐Fabrizio, and Caputo fractal‐fractional differential operators generate significant results as compared with classical approach.

A new design of a low-power reversible Vedic multiplier

In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.

SPARC_A DNA‐based optical nanosensor for in vivo imaging of acetylcholine in the peripheral nervous system

The study of neurotransmitter signaling helps to understand fundamental neuronal circuits and develop strategies against neurodegenerative diseases. Acetylcholine (ACh) plays a pivotal role in modulating neuron functions. Monitoring its physiological level in real‐time and probing its biological distribution is of crucial importance. However, the current techniques are subject to temporal and spatial limitations which impede their further in vivo applications. Herein we report the development of a ACh nanosensor by using DNA as a scaffold, acetylcholinesterase as a recognition component, pH‐sensitive fluorophores as signal generator, and α‐bungarotoxin as a targeting ligand. The nanosensor was delivered to the submandibular ganglion in living mice by microinjection for in vivo imaging of endogenous ACh release. The ACh nanosensor selectively binds to acetylcholine receptors on the post‐synaptic neurons, and display a sensitive response to physiological ACh range from 0.228 μM to 358 μM in ex vivo calibration. The ACh nanosensors also respond to endogenous ACh release triggered by electrical stimulation in a reversible and dose‐dependent manner. We also found that the treatment of cholinergic inhibitor, Vesamicol, significant suppresses the response of the ACh nanosensor. This work provides a tool for in vivo imaging of ACh dynamics with unprecedented capabilities to enhance the spatial and temporal resolution of detection. We envision such a sensor platform could be applied to imaging other neurotransmitters in mammalian system as well as extended to other organ systems in the peripheral nervous systemSupport or Funding InformationNIH common fund_SPARC_Project number: 1OT2OD024909‐01DNA‐based acetylcholine (ACh) nanosensors detect the ACh in the submandibular ganglion (SMG) of living mice. (A) ACh sensors were microinjected into the SMG of a living mouse. With the targeting ability of bungarotoxin, the ACh nanosensor can immobilize in the synaptic cleft of the mouse. (B) The mechanism of ACh nanosensors. (D) ΔF/F from pHAb channel in response to electrical stimulation (indicated by red arrow).Figure 1

Nonvolatile Memory Cell Based on Memristor

Memristor, one of the fundamental circuit elements, has promising applications in non-volatile memory and storage technology as it can theoretically achieve infinite states. Information can be stored independently in these states and retrieved whenever required. In this paper, we have proposed a non volatile memory cell based on memristor emulator. The circuit is able to perform read and write operations. In this memristor based memroy cell, unipolar pulse is used for writing and bipolar pulse is used for reading. Unlike other earlier designs, the circuit does not need external read/write enable switches to switch between read and write operations; the switching is achieved by the zero average bipolar read pulse given after the completion of write cycle. In our proposed memristor based memory cell, single bit can be read and any voltages from 0 to 5 volts can be written. Mathematical analysis and the simulation results of memristor emulator based read write circuit have been presented to confirm its operation.

Monolithic 3D Integration of InGaAs Photodetectors on Si MOSFETs Using Sequential Fabrication Process

We demonstrated the monolithic 3D (M3D) integration of InGaAs photodetectors (PDs) on silicon-on-insulator metal-oxide-semiconductor field-effect transistors (SOI-MOSFETs) by the sequential process of InGaAs PDs on pre-fabricated SOI-MOSFETs. InGaAs PDs and SOI MOSFETs showed their original performances after integration and sequential process thanks to the low-temperature process. In addition, the integrated devices successfully performed the fundamental readout circuit operation such as direct injection and source follower per detector (SFD) by connecting transistors (Trs) and PDs. By illuminating 1550 nm laser on InGaAs PDs, the different behaviors of output voltages were clearly obtained according to the Tr’s on/off state. From these results, we believe that this monolithic 3D integration method could be a feasible approach toward high-resolution multicolor imaging systems.

RETRACTED: FPGA implementation of PMSG based ac conversion using soft switching twin–mode PWM/FPGA control for high power IM application

This paper exhibits an impedance-source control converter and its control strategy for actualizing dc-to-ac, ac to-dc, ac to-ac, and dc-to-dc control change. The proposed inverter consolidates the fundamental circuit and the power source. This setup conveys a solid lift ability to conquer the obstructions of the arrangement inductance Z-source inverter. The Induction engine related control strategy for PMSG (Permanent Magnet Synchronous Generator) based breeze vitality age with a created two leg transformer based Z-source inverter. Including, the gadget may get crushed because of the control of resounding current amid build up by the altered inverter. In comparative of existing transformer based inverters with Z-source/transformer based inverters with semi Z source, to get comparative transformer input, yield, adjusted inverter has limited voltage worry with bigger regulation esteem, lesser current strain, lesser info current twisting, diode. This printed material examination the working standards, reproduction results, and looks at to the current six switch inverters. To demonstrate the productivity of the novel proposed change circuit, an equipment model was displayed in view of a FPGA introduced omplex programmable logic device (CPLD) memory to create heartbeat and it is given to the propounded inverter to deal with the Induction engine in a well way.

Digital photonics parity bit error detection system

The optical communication medium is emerging to be one of the potential replacements to the current electronic systems widely used today. This is due to its much higher data transmission with extremely low loss properties, not to mention that it is almost invulnerable to electromagnetic interference. In this paper we demonstrated our proposed design of a digital photonic parity bit error detection system, one of the fundamental digital electronic circuits used during long-range digital signal transmission. Silicon photonic micro-ring resonators are used as its core component, where each of the rings operates as a digital logic XOR mode, by taking advantage of the resonance shifting properties of the silicon waveguide. Dynamic response characterization has been carried out by simulating the proposed circuits at the data rate of 1Gbps, with the data sampling rate of 1.6THz, and clear timing waveform was generated to show that the proposed circuit operates as the parity bit error detection system.