Fundamental Arithmetic Operations Research Articles

Effectiveness of Peer Tutoring in Enhancing Fundamental Arithmetic Operations

This study utilized the descriptive correlational design to determine the effectiveness of Peer tutoring in enhancing Fundamental Arithmetic Operations of the fifty-two (52) learners in Grade III-Lily and Jasmine of U-og Elementary School, Inabanga, Bohol. Most of the respondents were at the age of 9 and majority were female. A researchers-made survey questionnaire was used as tool in gathering the data. The gathered data were tallied and analyzed using frequency count, simple percentage, weighted mean, and Pearson Product Moment Correlation Coefficient to test the relationship between Peer tutoring and Fundamental Arithmetic Operations. Results showed that the computed r-value 0.413782 was higher than the critical r-value 0.2732 at 0.05 level of significance with 50 degrees of freedom, so the null hypothesis was rejected. Therefore, there was a significant relationship between Peer tutoring and Fundamental Arithmetic Operations which implied that peer tutoring is one of the strategies that may help and assist learners in enhancing fundamental arithmetic operations.

Speed, Power and Area Optimized Monotonic Asynchronous Array Multipliers

Multiplication is a fundamental arithmetic operation in electronic processing units such as microprocessors and digital signal processors as it plays an important role in various computational tasks and applications. There exist many designs of synchronous multipliers in the literature. However, in the domain of Input–Output Mode (IOM) asynchronous design, there is relatively less published research on multipliers. Some existing works have considered quasi-delay-insensitive (QDI) asynchronous implementations of multipliers. However, the QDI asynchronous design paradigm, in general, is not area- and speed-efficient. This article presents an efficient alternative implementation of IOM asynchronous multipliers based on the concept of monotonic Boolean networks. The array multiplier architecture has been considered for demonstrating the usefulness of our proposition. The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). The multipliers were implemented using a 28 nm CMOS process technology.

AritPIM: High-Throughput In-Memory Arithmetic

Digital processing-in-memory (PIM) architectures are rapidly emerging to overcome the memory-wall bottleneck by integrating logic within memory elements. Such architectures provide vast computational power within the memory itself in the form of parallel bitwise logic operations. We develop novel <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">algorithmic</i> techniques for PIM that, combined with new perspectives on computer arithmetic, extend this bitwise parallelism to the four fundamental arithmetic operations (addition, subtraction, multiplication, and division), for both fixed-point and floating-point numbers, and using both bit-serial and bit-parallel approaches. We propose a state-of-the-art suite of arithmetic algorithms, demonstrating the first algorithm in the literature of digital PIM for a majority of cases – including cases previously considered impossible for digital PIM, such as floating-point addition. Through a case study on memristive PIM, we compare the proposed algorithms to an NVIDIA RTX 3070 GPU and demonstrate significant throughput and energy improvements.

A horizontal refined piecewise linear interface reconstruction (HOPLIRE) method based on the VOSET method for capturing the two-phase interface

The interface reconstruction method is significant for the numerical research of the two-phase problem, but the implementation of popular ones is not easy enough. In this paper, a horizontal refined piecewise linear interface reconstruction (HOPLIRE) method with a straightforward implementation procedure is proposed for the incompressible flow, and the idea of that is to reconstruct the two-phase interface in one grid cell with many horizontal refined pieces. Only one situation without complex classifications needs to be considered for reconstructing the interface, and the volume fraction flux through the grid cell face can be easily obtained to solve the VOF function by a simple four fundamental operations of arithmetic. In addition to the advantages of simple implementation for the HOPLIRE method, the accuracy of the reconstructed vapor–liquid interface is also high. The proximity between the HOPLIRE method and the popular piecewise linear interface reconstruction (PLIC) method increases with the divided piece number of the HOPLIRE method, and 30 is recommended based on calculation accuracies of LS function, interface direction, and curvature. Besides, the good performances of the VOSET-HOPLIRE method in the calculation accuracy and efficiency are verified by comparing with VOF-PLIC and VOSET-PLIC methods by some classical two-phase problems. Currently, the HOPLIRE method is only presented based on a two-dimensional problem under a structured mesh. In the future, this methodology will be improved to cover three-dimensional problems and unstructured meshes.

A Fibonacci analogue of the two’s complement numeration system

Using the classic two’s complement notation of signed integers, the fundamental arithmetic operations of addition, subtraction, and multiplication are identical to those for unsigned binary numbers. We introduce a Fibonacci-equivalent of the two’s complement notation and we show that addition in this numeration system can be performed by a deterministic finite-state transducer. The result is based on the Berstel adder, which performs addition of the usual Fibonacci representations of nonnegative integers and for which we provide a new constructive proof. Moreover, we characterize the Fibonacci-equivalent of the two’s complement notation as an increasing bijection between ℤ and a particular language.

Quantum Protocol for Secure Multiparty Logical AND With Application to Multiparty Private Set Intersection Cardinality

Like addition, subtraction, multiplication and division, logical AND is a fundamental arithmetic operation in scientific computing. In this paper, we first consider and define a new privacy-preserving problem, i.e., Secure Multiparty Logical AND (SMLA), in which multiple participants can jointly compute the logical AND of their respective private bits. Furthermore, we present a novel quantum SMLA protocol by employing phase-matching quantum conference key agreement and perfect quantum encryption, and design the corresponding quantum circuits. The proposed quantum SMLA protocol can ensure information-theoretical security. What’s more, we design a private grouping strategy to reduce the communicational complexity and accordingly present an improved quantum SMLA protocol with the linear communicational rounds. In addition, we investigate its applications and design a feasible quantum Multiparty Private Set Intersection Cardinality (MPSI-CA) protocol based on the improved quantum SMLA protocol, in which multiple participants jointly compute the intersection cardinality without revealing their respective private sets. Finally, we verify the correctness and the feasibility of the proposed quantum protocols by circuit simulations in IBM Qiskit.

An Analysis of 3rd Graders’ Problem Solving Strategies on Early Algebra

The purpose of this study was to investigate the understanding of and the preparation for third graders’ learning of algebra, and to derive didactic implications for helping students’ transition from arithmetical thinking to algebraic thinking. Twenty third graders in elementary school were selected as subjects of this study from I elementary school in Seoul. Since the students have learned the four fundamental arithmetic operations on whole numbers, they were able to understand equations, additions, subtractions, multiplications, and divisions and perform them.&#x0D; Questionnaires were developed by adapting and reconstructing the problems for preparing algebraic learning, as proposed by Blanton et al. (2011) and Lim &amp; Chang (2019), to be available to elementary school students. The students’ problem solving strategies were analyzed by means of the questionnaires. Implications for developing essential understandings of algebraic thinking and supporting elementary students’ transition from arithmetical thinking to algebraic thinking were identified through the results of the analysis.

High-Performance 10-Transistor Adder Cell for Low-Power Applications

Addition is one of the most fundamental arithmetic operations. Any adder in a digital circuit and system can improve the digital system's performance. Adders, for example, are commonly found in the critical path of many ALUs, processors, and digital signal processing chips. As a result, each of these blocks should execute efficiently and precisely on their own, enhancing the overall performance of the system. Optimizing an adder may lead to overall system optimization. A desirable adder meets all the criteria, such as high speed, low-power dissipation, low leakage power, and small footprint. However, because there is a trade-off between the area, power and, speed.Obtaining the finest adder in terms of speed, power dissipation, leakage power, and area consumed would assist the designer in selecting an adder for the given application. Transmission function adder (TFA), 17-transistor adder (17-TA), 14-transistor adder (14-TA), ripple carry adder (RCA), carry lookahead adder (CLA), and carry-select adder are among the new 2-bit adders suggested and compared (CSL). This research presents a comparative analysis and performance evaluation of adders based on latency, power dissipation, PDP, leakage power, area, and EDP. Simulations are being done using HSPICE software at 28-nm technology with a supply voltage range of 0.7–1.1 V. The suggested adder has a minimum delay and is 8.6% faster than CLA, according to simulation results. When compared to the other adders, it uses the minimum area and has the lowest leakage power. The proposed adder has minimum power delay product.

Gradient descent for quadratic functions using geometric mean and the Kai Fang method

SummaryThe geometric mean is typically used to measure the mean of inflation rate and population fluctuation. It is also used in the description and analysis of singularities and geometric distance spaces. Gradient descent is an integral part of artificial intelligence. In this study, we transform the gradient calculation from conventional quadratic gradient descent algorithms into a root extraction calculation using geometric means. To eliminate the computational complexity of differential operations in gradient calculation and to easily calculate roots using only fundamental arithmetic operations, we introduce the Kai Fang method, the East Asian traditional root extraction method. To do this, we propose a new quadratic gradient descent method based on geometric means and we apply the Kai Fang method with geometric means to create an improved quadratic gradient descent method. The proposed method shows improved computational ease over conventional methods.

Implementing parallel arithmetic via acetylation and its application to chemical image processing

Chemical mixtures can be leveraged to store large amounts of data in a highly compact form and have the potential for massive scalability owing to the use of large-scale molecular libraries. With the parallelism that comes from having many species available, chemical-based memory can also provide the physical substrate for computation with increased throughput. Here, we represent non-binary matrices in chemical solutions and perform multiple matrix multiplications and additions, in parallel, using chemical reactions. As a case study, we demonstrate image processing, in which small greyscale images are encoded in chemical mixtures and kernel-based convolutions are performed using phenol acetylation reactions. In these experiments, we use the measured concentrations of reaction products (phenyl acetates) to reconstruct the output image. In addition, we establish the chemical criteria required to realize chemical image processing and validate reaction-based multiplication. Most importantly, this work shows that fundamental arithmetic operations can be reliably carried out with chemical reactions. Our approach could serve as a basis for developing more advanced chemical computing architectures.

Hardware implementation of the coding algorithm based on FPGA

In this article, the efficient implementation multiplier of polynomials irreducible polynomials modulo for cryptographic encryption and decryption using FPGA is presented. For this, the Nexys 4 board based on the Artix-7 Field Programmable Gate Array (FPGA) from Xilinx was chosen. Verilog HDL is used to describe the circuit for reducing a number modulo. The results of a timing simulation of the device are presented in the form of time diagrams for a given 8-bit number, confirming the correct operation of the device. The developed encryption algorithm on the basis of non-positional polynomial notations is intended for software, hardware, and also software and hardware implementation. The main hardware-implemented device in non-positional algorithm of the cryptographic transformation is a device for the multiplication of polynomials irreducible polynomials modulo, which produces routine calculations on data encryption. These mathematical operations are computationally intensive and fundamental arithmetic operations, which are intensively used in many fields such as cryptography, number theory, and finite field arithmetic.

Linear complementarity model predictive control with limited iterations for box-constrained problems

This paper presents a sufficient condition and its certification algorithm for solving box-constrained linear model predictive control (MPC) problems within a certain number of iterations equal to the number of constrained prediction points. For implementing a model predictive controller in industrial applications, it is crucial to guarantee a concrete upper bound on the computational load so that the processor specifications can be determined. To address this matter, we transform the constrained quadratic optimization of MPC into an equivalent linear complementarity problem (LCP). Then, we show that if a modified n-step vector exists for a given problem, the corresponding LCP is feasible and solvable within a predetermined number of iterations, each comprising fundamental arithmetic operations. The existence of a modified n-step vector is independent of the current states and box constraint bounds. Thus, the total computational load required to solve an MPC problem can be explicitly determined. In addition, an explicit certification algorithm for checking the existence of a modified n-step vector is proposed. Utilizing this algorithm, the existence range of a modified n-step vector is investigated for various problem configurations. Numerical tests show that the computational speed of the proposed method is competitive with those of commonly available algorithms.

Unpacking Mathematics Pedagogical Content Knowledge for Elementary Number Theory: The Case of Arithmetic Word Problems

“Number” is an important learning dimension in primary mathematics education. It covers a large proportion of mathematical topics in the primary mathematics curriculum, and teachers use most of their class time to teach fundamental number concepts and basic arithmetic operations. This paper focuses on the nature of mathematics pedagogical content knowledge (MPCK) concerning arithmetic word problems. The aim of this qualitative research was to investigate how well the future primary school teachers in Hong Kong had been prepared to teach mathematical application problems for third and sixth graders. Nineteen pre-service teachers who majored in both mathematics and primary education were interviewed using two sets of scenario-based questions. The results revealed that innovative approaches were suggested for teaching third graders while the strategies suggested for teaching sixth graders were mostly based on a profound understanding of mathematical content knowledge. Many participants demonstrated sound knowledge about the sixth grader’s mathematical misconception, but most of them were unable to precisely indicate the third grader’s error in presenting a complete solution for a typical mathematics word problem. A deep understanding of elementary number theory seems to be a precondition for developing pre-service teachers’ MPCK in teaching arithmetic word problems.

VLSI design of APT-VDF using novel variable block sized ternary adder and multiplier

Nowadays, Variable digital filters (VDF) play an essential role in the field of communication and signal processing. The desired frequency response of any prototype filter can be obtained by developing an All Pass Transformation (APT) based Variable digital filter (APT-VDF) that maintains an exhaustive control over the cut off frequency. The performance of the APT-VDF is limited by its speed and area utilization. In this paper, the pipelined APT-VDF is modified by developing a new Variable Block Sized Ternary Adder (VBS-TA) and a modified Ternary multiplier for the fast realization of the filter structure. Because, the fundamental arithmetic operations involved in the design of APT-VDF are addition and multiplication. The ternary logic transmits more data through interconnection wire, and hence the ternary logic based arithmetic requires fewer components and interconnections. The proposed VBS-TA increases the speed of the addition process by skipping the carry propagation with the help of ternary compound gates. This VBS-TA can also be used to boost up the speed of the multiplier circuit in the APT-VDF filter. Furthermore, the ternary multiplier is modified by introducing a divide and conquers approach in the partial product generation part. The simulation results show that the proposed APT-VDF overtakes the existing VDFs in terms of delay, power and area utilization. It consumes only 0.289Wpower with a latency of 9.24 ns. Also, it achieves an operating frequency of 210.87 MHz, and it is much better than the existing VDFs.

VLSI Implementation of Digital Filter using Novel RTSD Adder and Booth Multiplier

Finite Impulse Response (FIR) filters are most important element in signal processing and communication. Area and speed optimization are the essential necessities of FIR filter design. This work looks at the design of Finite Impulse Response (FIR) filters from an arithmetic perspective. Since the fundamental arithmetic operations in the convolution equations are addition and multiplication, they are the objectives of the design analysis. For multiplication, Booth encoding is utilized in order to lessen the quantity of partial products. Consequently, considering carry-propagation free addition strategies should improve the addition operation of the filter. The redundant ternary signed-digit (RTSD) number framework is utilized to speedup addition in the filter. The redundant ternary representation utilizes more bits than required to denote the single binary digit because of which most numbers have several representations. This special behavior of RTSD allows the addition along with the absence of typical carry propagation. Xilinx ISE design suite 14.5 is used for the design and validation of proposed method. From the implementation result, the proposed design of FIR filter is compared with other conventional techniques to show the better performance by means of power, area and delay.

Electronic Abacus (e-Abacus) using FPGA Altera DE2 Board

The development of electronic abacus using Altera DE2 115, is to integrate the use of abacus along with electronic devices which offer better visualisation of the abacus operations. The main focus of this technology is to assist the primary school students in validating a fundamental arithmetic operation. The electronic abacus is developed by integrating an abacus, abacus decoder module and field programming gate array (FPGA) based processor. DE2 115 is chosen as the development module and very high-speed integrated circuit hardware description language (VHDL) as a main programming language. The arithmetic algorithm developed for the electronic abacus is limited to the computational of whole numbers only, involving the basic arithmetic operation of additional, subtraction, multiplication and division. This electronic abacus comes with two operational modes, display and arithmetic mode. In the display mode, the abacus beads position at column one until column seven is displayed as numerical representation on the liquid crystal display (LCD) screen. A computation of arithmetic operations with less than three operators is available in the arithmetic mode with the capability of displaying the negative numerical and infinite value. From the simulation conducted in Quartus II, the implementation of the algorithm in FPGA utilise 4% from the total logical element allowed and consume approximately 143.4 mW of power. As a conclusion, this enhanced ancient apparatus hopefully will contribute to the development of more lively and interesting teaching approach.

Design and Analysis of a Low Power Binary Counter-based Approximate Multiplier Architecture

Multiplication has become the fundamental arithmetic operation in modern electronic world. Many researches in Signal processing and image processing applications are looking for energy efficient architectures. These applications exhibit error tolerance thus laying foundation for approximation techniques. The proposed work utilizes a new binary counter for partial product accumulation in a segmentation based approximate multiplication technique. The fundamental building block of the counter is a 3-bit stack circuit, which combines each of “Logic 1” bits collectively, after which a stacking process is done to convert two 3-bit modules into a 6-bit stack module. The counter circuit is obtained by converting the bit stacks to binary counts, without any XOR gates on the critical line of operation. This leads to design of binary counters with effective yield of power and delay. Moreover, applying these counters for partial product accumulation in the approximate multipliers found to be more effective when compared with conventional techniques. In future, these counter based approximate multipliers can be utilized to design energy efficient filters for image processing and signal processing applications.

Design and Implementation of Compressor based 32-bit Multipliers for MAC Architecture

Arithmetic operations play a major role in digital circuit design like adders, multipliers etc. Multiplication is an important fundamental arithmetic operation in high performance systems such as microprocessor and digital signal processors circuits. Implementation of multipliers using compressor circuit over conventional adders will reduce the number of levels of addition, which will in turn reduces the latency of the multiplier. Multiplier module is most likely the essential part of MAC (Multiplier-Accumulator) unit design. Compressor based multipliers in MAC architecture design results high performance. FPGA and ASIC implementations of 4:2 compressor based 32-bit Wallace and Dadda multipliers can be done by using Xilinx Vivado and Cadence CMOS technology tools. These results are compared with other multiplier designs with respect to area, latency and power dissipation.

Mathematics and Speed for Interval Arithmetic

After a short introduction, the article begins with an axiomatic definition of rounded arithmetic. The concepts of rounding and of rounded arithmetic operations are defined in an axiomatic manner fully independent of special data formats and encodings. Basic properties of floating-point and interval arithmetic can directly be derived from this abstract mathematical model. Interval operations are defined as set operations for elements of the set ¯IR of closed and connected sets of real numbers. As such, they form an algebraically closed subset of the powerset of the real numbers. This property leads to explicit formulas for the arithmetic operations of floating-point intervals of ¯IF, which are executable on the computer. Arithmetic for intervals of ¯IF forms an exception free calculus, i.e., arithmetic operations for intervals of ¯IF always lead to intervals of ¯IF again. Later sections are concerned with programming support and hardware for interval arithmetic. Both are a must and absolutely necessary to move interval arithmetic more into the center of scientific computing. With some minor hardware additions, interval operations can be made as fast as simple floating-point operations. In vector and matrix spaces for real, complex, and interval data, the dot product is a fundamental arithmetic operation. Computing the dot product of two vectors with floating-point components exactly substantially speeds up floating-point and interval arithmetic as well as the accuracy of the computed result. Hardware needed for the exact dot product is very modest. The exact dot product is essential for long real and long interval arithmetic. Section 9 illustrates that interval arithmetic as developed in this article already has a long tradition. Products based on these ideas have been available since 1980. Implementing what the article advocates would have a profound effect on mathematical software. Modern processor architecture from Intel, for example, comes quite close to what is requested in this article.

Research on arithmetic operations over generalized orthopair fuzzy sets

The four fundamental operations of arithmetic for real (and complex) numbers are well known to everybody and quite often used in our daily life. And they have been extended to classical and generalized fuzzy environments with the demand of practical applications. In this paper, we present the arithmetic operations, including addition, subtraction, multiplication, and division operations, over -rung orthopair membership grades, where subtraction and division operations are both defined in two different ways. One is by solving the equation involving addition or multiplication operations, whereas the other is by determining the infimum or supremum of solutions of the corresponding inequality. Not all of -rung orthopairs can be performed by the former method but by the latter method, and it is proved that the former is a special case of the latter. Moreover, the elementary properties of arithmetic operations as well as mixed operations are extensively investigated. Finally, these arithmetic operations are pointwise defined on -rung orthopair fuzzy sets in which the membership degree of each element is a -rung orthopair.