XOR Gate Research Articles

Non-Volatile Reconfigurable Compact Photonic Logic Gates Based on Phase-Change Materials.

Photonic logic gates have important applications in fast data processing and optical communication. This study aims to design a series of ultra-compact non-volatile and reprogrammable photonic logic gates based on the Sb2Se3 phase-change material. A direct binary search algorithm was adopted for the design, and four types of photonic logic gates (OR, NOT, AND, and XOR) are created using silicon-on-insulator technology. The proposed structures had very small sizes of 2.4 μm × 2.4 μm. Three-dimensional finite-difference time-domain simulation results show that, in the C-band near 1550 nm, the OR, NOT, AND, and XOR gates exhibit good logical contrast of 7.64, 6.1, 3.3, and 18.92 dB, respectively. This series of photonic logic gates can be applied in optoelectronic fusion chip solutions and 6G communication systems.

Parity Generators for Nanocommunication Systems Using QCA Nanotechnology

Quantum-dot cellular automata (QCA) nanotechnology has the capability to design highly-dense, ultra-low power, and high-speed digital circuits at ultra-deep sub-micron (ultra-DSM) level. QCA nanostructure provides a transistor-free operation that saves large energy dissipation as compared to the conventional metal oxide semiconductor field effect transistor (MOSFET) technology. In this paper, 3-input exclusive-OR (XOR) and exclusive-NOR (XNOR) gates are presented using QCA cells. XOR and XNOR (XOR-XNOR) gates are further utilized to design the 2-, 3-, 4-, and 5-bit even and odd parity generators. The QCA-based 3-input XNOR gate is constructed using only 10 QCA cells and two clock phases. The target of the presented designs is to use the minimum count of QCA cells in a simplistic way to form the higher bit-size parity generators. The comparative analyses for the different performance metrics are showing that the developed designs are performing well for the cell count, latency, area, and layout cost as compared to the existing designs. Energy dissipation for the designs is calculated to check the energy efficiency by using the QCA Designer-E and QCA Pro tools.

A Framework for Reliability Analysis of Combinational Circuits Using Approximate Bayesian Inference

A commonly used approach to compute the error rate at the primary outputs (POs) of a circuit is to compare the fault-free and faulty copies of the circuit using XOR gates. This model results in poor accuracies with nonsampling-based methods for reliability estimation. An alternative is to use a single copy of the circuit with a four-valued representation for each net corresponding to the correct and incorrect signals. One problem in this formulation is the accurate propagation of associated probabilities. We use the framework of Bayesian inference (BI) to address this issue. We derive the conditional probability distribution (CPD) corresponding to the four-valued signals and find the output error rate using various approximate BI techniques. With our formulation, we demonstrate that the output error rate scales with the gate error probabilities. It is guaranteed to be zero when the gate error probability is zero, provided approximate BI algorithms based on sum-product belief propagation (BP) are used. Although inaccuracies increase at very low gate error probabilities, it is able to capture the relative reliability of outputs with respect to each other. We also propose a new method for finding the overall circuit error rate as the partition function for a fixed state of POs. This method provides a significant improvement in accuracy when compared with the existing method using OR gates.

Advanced approach for encryption using advanced encryption standard with chaotic map

At present, security is significant for individuals and organizations. All information need security to prevent theft, leakage, alteration. Security must be guaranteed by applying some or combining cryptography algorithms to the information. Encipherment is the method that changes plaintext to a secure form called cipherment. Encipherment includes diverse types, such as symmetric and asymmetric encipherment. This study proposes an improved version of the advanced encryption standard (AES) algorithm called optimized advanced encryption standard (OAES). The OAES algorithm utilizes sine map and random number to generate a new key to enhance the complexity of the generated key. Thereafter, multiplication operation was performed on the original text, thereby creating a random matrix (4×4) before the five stages of the coding cycles. A random substitution-box (S-Box) was utilized instead of a fixed S-Box. Finally, we utilized the eXclusive OR (XOR) operation with digit 255, also with the key that was generated last. This research compared the features of the AES and OAES algorithms, particularly the extent of complexity, key size, and number of rounds. The OAES algorithm can enhance complexity of encryption and decryption by using random values, random S-Box, and chaotic maps, thereby resulting in difficulty guessing the original text.

SecGreen: Secrecy Ensured Power Optimization Scheme for Software-Defined Connected IoV

Software-Defined Internet of Vehicles (SD-IoV) is an emerging technology that is being used in modern intelligent transportation systems (ITS). The ultimate goal of SD-IoV is to provide seamless connectivity to the end-users with low latency and high-speed data transfer. However, due to the increase in the density of the connected IoV using an open channel, i.e., the Internet, the foremost challenges of high power consumption and secure data transfer are inevitable in such an environment. An external eavesdropper may intercept the transmitted message to access the legitimate information over the public channel, i.e., the Internet. Most of the solutions reported in the literature to tackle these issues may not be applicable in the SD-IoV environment due to high computation and communication costs. Motivated from this, in this paper, the problems of high power consumption and secure data transfer in SD-IoV are formulated using mixed-integer non-linear programming (MINLP) with associated constraints. To solve the aforementioned problem, we propose a joint power optimization and secrecy ensured scheme known as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> . <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> has an efficient energy harvesting algorithm using simultaneous wireless information and power transfer (SWIPT) to maximize the energy efficiency. Moreover, to mitigate various security attacks, a resilient lightweight secrecy association protocol is designed between vehicle and trusted gateway node of SD-IoV so that only trusted vehicles can communicate with each other and with the nearest base stations. The secrecy association protocol uses security primitives such as– physically unclonable function (PUF), one-way hash function, and bitwise exclusive OR (XOR) operations which are suitable for energy-constraint sensors in SD-IoV. The performance of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> is compared with the existing schemes, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Stable &amp; Scalable Link Optimization (SSLO), and Secure &amp; Energy-Efficient Blockchain-enabled (SEEB)</i> respectively. The result shows that when the number of packets across the subchannel increases, the energy consumption increases. Also, the result shows that the proposed scheme attains 22.5% and 20.34% better energy efficiency as compared to SSLO and SEEB schemes, respectively. In addition, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> scheme achieves 37.48% and 32.15% higher throughput as compared to SSLO and SEEB schemes. The results obtained show the superior performance of the proposed <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> scheme in comparison to these existing competitive schemes in the literature.

Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality Analysis

During the last decade, logic locking has been proposed to protect integrated circuits against piracy and reverse engineering threats. Functional pruning attacks, such as the Boolean satisfiability (SAT) attack, have greatly challenged the security of logic locking techniques, yet they require access to an oracle and suffer from muted efficacy on inherently SAT-hard circuits. In this article, we present a novel oracleless attack on both XOR and MUX-based logic locking by analyzing the redundancy level deviation under different keys. Our fundamental insight is that incorrect keys would produce circuits that violate universally followed design principles, prominent among which stands the minimization of logic redundancy. We leverage the redundancy-level deviation produced by individual and pairs of key bits to recover key bit values and establish pairwise equivalence, leading to an efficient nearly linear time attack algorithm. We experimentally verify that the proposed attack quickly unveils more than half of the key bits with high accuracy on 21 ISCAS’85 and MCNC circuits locked with a variety of locking techniques. To fortify logic locking in the face of this successful redundancy attack, we supplement this article with a key gate insertion methodology that smooths the deviation in redundancy level. We achieve this goal by selecting key gates that exhibit pairwise dissociation among a set of individually secure locations, which effectively breaks down correlations in arbitrary sets of key gates and, thus, imposes a consistent redundancy level throughout the key space. Experimental results confirm the strong redundancy attack resilience of the proposed defense strategy.

Ultra-Low-Power and Compact-Area Analog Audio Feature Extraction Based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectification

To address the power and area bottleneck imposed by the frontend feature extractor relative to the backend neural network in on-device keyword spotting (KWS), we propose two time-mode analog signal processing (ASP) circuit techniques showcased in an analog audio feature extractor chip that advances the state of the art in power- and area-efficiency. Time-mode analog filterbank interpolation uses digital XOR gates to double the number of outputs of an analog bandpass filterbank. Time-mode analog rectification uses a single digital XOR gate as an analog full-wave rectifier. The 65 nm low power (LP) CMOS chip uses only 80 nW and 0.53 mm2 to extract from an input analog audio signal, an output digital auditory feature vector with 31 elements. This represents <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$18\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.3\times $ </tex-math></inline-formula> improvements in power/feature and area/feature, as compared, respectively, to the most area- and power-efficient published analog audio feature extractor chips. All the while, competitive classification accuracy is maintained at >90% across ten keywords, as evaluated by feeding the chip’s digital output directly into a small-footprint software backend classifier.

Encryption of Dynamic Areas of Images in Video based on Certain Geometric and Color Shapes

The paper is devoted to the search for new approaches to encrypting selected objects in an image. Videos were analyzed, which were divided into frames, and in each video frame, the necessary objects were detected for further encryption. Images of objects with a designated geometric shape and color characteristics of pixels were considered. To select objects, a method was used based on the calculation of average values, the analysis of which made it possible to determine the convergence with the established image. Dividing the selected field into subregions with different shapes solves the problem of finding objects of the same type with different scales. In addition, the paper considers the detection of moving objects. The detection of moving objects is carried out based on determining the frame difference in pixel codes in the form of a rectangular shape. Cellular automata technology was used for encryption. The best results were shown by the transition rules of elementary cellular automata, such as: 90, 105, 150, and XOR function. The use of cellular automata technologies made it possible to use one key sequence to encrypt objects on all video frames of the video. Encryption results are different for the same objects located in different places of the same video frame and different video frames of the video sequence. The video frame image is divided into bit layers, the number of which is determined by the length of the code of each pixel. Each bit layer is encrypted with the same evolution, which is formed by one initial key bit sequence. For each video frame, a different part of the evolution is used, as well as for each detected object in the image. This approach gives different results for any objects that have a different location both on the video frame image and in different video frames. The described methods allow you to automate the process of detecting objects on video and encrypting them.

Logic-Gates of Gas Pressure for Portable, Intelligent and Multiple Analysis of Metal Ions.

DNA logic gates have shown outstanding magic in intelligent biology applications, but it remains challenging to construct a portable, affordable and convenient DNA logic gate. Herein, logic gates of gas pressure were innovatively developed for multiplex analysis of metal ions. Hg2+ and Ag+ were input to interact specifically with the respective mismatched base pairs, which activated DNA extension reaction by polymerase and led to the enrichment of platinum nanoparticles for catalyzing the decomposition of peroxide hydrogen. Thus, the gas pressure obtained from a sealed well was used as output for detecting or identifying metal ions. Hg2+ and Ag+ were sensitively and selectively detected, and the assay of the real samples was also satisfactory. Based on this, DNA logic gates, including YES, NOT, AND, OR, NAND, NOR, INHIBIT, and XOR were successfully established using a portable and hand-held gas pressure meter as detector. So, the interactions between DNA and metal ions were intelligently transferred into the output of gas pressure, which made metal ions to be detected portably and identified intelligently. Given the remarkable merits of simplicity, logic operation, and portable output, the metal ion-driven DNA logic gate of gas pressure provides a promising way for intelligent and portable biosensing.

Efficient GDI-based approximate subtractors for change detection in bio-image processing applications

Three new approximate subtractors are presented based on the gate diffusion input (GDI) technique which benefits from the dynamic threshold (DT) technique using carbon nanotube field-effect transistors (CNTFETs) technology. Proposed-1, Proposed-2, and Proposed-3 subtractors have 10, 8, and 6 transistors with a total area of 0.289 μm2, 0.123 μm2, and 0.065 μm2, respectively. In Proposed-1 and Proposed-2, only XOR and F1 gates are used, which respectively have 2 and 4 errors. To solve the non-full-swing defects of these two circuits, only three F2-GDI gates are used in the Proposed-3, which has 4 errors. The Proposed-1 gives 0.25 as error distance (ED) while two other circuits with a lower area have an ED of 0.5. The Proposed-3 has a simple, low-power, and ground-free structure. The subtractors are implemented in an 8 to 4 non-restoring divider in four different configurations including vertical, horizontal, square, and triangular. The drivers based on Proposed-2 and Proposed-3 are the best circuits with average power-delay-product (PDP) savings of 68.16% and 57.43%, respectively. Finally, the dividers are used in the change detection of medical images, where, the proposed circuits show better circuitry performance and image quality production.

A New Design of a 3 × 3 Reversible Circuit Based on a Nanoscale Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is the best-suggested nanotechnology for designing digital electronic circuits. It has a higher switching frequency, low-power expenditures, low area, high speed and higher scale integration. Recently, many types of research have been on the design of reversible logic gates. Nevertheless, a high demand exists for designing high-speed, high-performance and low-area QCA circuits. Reversible circuits have notably improved with developments in complementary metal–oxide–semiconductor (CMOS) and QCA technologies. In QCA systems, it is important to communicate with other circuits and reversible gates reliably. So, we have used efficient approaches for designing a [Formula: see text] reversible circuit based on XOR gates. Also, the suggested circuits can be widely used in reversible and high-performance systems. The suggested architecture for the [Formula: see text] reversible circuit in QCA is composed of 28 cells, occupying only 0.04[Formula: see text][Formula: see text]m2. Compared to the state-of-the-art, shorter time, smaller areas, more operational frequency and better performance are the essential benefits of the suggested reversible gate design. Full simulations have been conducted with the utilization of QCADesigner software. Additionally, the proposed [Formula: see text] gate has been schematized using two XOR gates.

A novel method for measuring body bioimpedance and its FPGA implementation

One of the most promising methods for assessing human tissue and diagnosing diseases is to measure the bioimpedance of the body. They have been various methods presented for achieving this goal. The most important point is measuring the phase along with the amplitude. On this basis, a field-programmable gate array (FPGA) is used in this study to measure the accuracy in amplitude and phase. At the first, a frequency spectrum is applied to the body model, then an algorithm in the VHDL compiler determines the amplitude of the output voltage. The phase change is measured by using direct digital measurement (DDM), and the product displayed in degrees or radian units. Subsequently, an FPGA model of the body has been simulated by using a lookup table (LUT) and various dependent circuits. FPGA-based hardware implementation is conducted by using Xilinx ISE 14.7 software, in which the chip selected for implementation is xc7z0203clg484. In this regard, the phase has detected. It's using an XOR gate, which consumes less power and hardware compared to flip-flop detectors. This novel phase measurement technique eliminates that needs for an exact adjustment of the clock, which increases measurement accuracy and reduces error. In the analysis of simulation results and theoretical values, the amount of the error has been calculated and plotted. As a result, the advantages of this method include being highly accurate, requiring little hardware, being flexible when changing the circuit, and consuming very little power.

New Methodology for the Design of Nanostructured Integrated Circuits

Background: A metal oxide semiconductor field effect transistor (MOSFET) is widely used to make integrated circuits (ICs). MOSFET devices are reaching the practical limitations for further scaling in the nanoscale regime. It motivates the researchers to explore and develop new ways to advance the electronics industry. Quantum-dot cellular automata (QCA) is a potential way to replace the MOSFET devices in the nanoscale regime. QCA nanotechnology not only solves the issue of scalability but also degrades the leakage current. It has numerous benefits, such as a highly dense design, fast speed, and energy efficiency compared to complementary metal-oxide-semiconductor (CMOS) technology. Objective: An extensive study of QCA nanotechnology is needed to quickly understand the field. Optimizing the QCA designs is the mandatory requirement to minimize the occupied cell area, latency and quantum cost. The preliminary knowledge of QCA nanotechnology boosts the idea of generating different logic functions. This review paper presents the methodology for making the fundamental logic gates using QCA nanotechnology. XOR gate is commonly used to implement popular circuits such as adders, subtractors, comparators, code converters, reversible gates etc. The various available QCA-based 2-input XOR gate designs are discussed and compared for the different performance metrics. Methods: Columbic interaction causes logical operations, and data is transferred from one cell to another cell using cell-to-cell interaction. A specific arrangement of QCA cells produces a specific logic. QCA Designer tool using a Bi-stable simulation engine is used to design different digital circuits. Results: This review paper deals with the design of the 2-input XOR gate. The considered performance metrics for the comparison purpose are cell count, occupied area, clock cycle, and quantum cost. Existing works on 2-input XOR gates show that a minimum of 8 QCA cells are needed for a 2-input XOR gate using QCA nanotechnology. A single clock cycle-based 2-input XOR gate requires at least 9 QCA cells. The quantum cost can be minimized by reducing the number of QCA cells and clock cycles. Conclusion: This review paper helps the circuit designers to select the appropriate 2-input XOR gate for the design of complex circuits. Circuit designers can use the fundamental concepts detailed in the paper to implement any Boolean function and optimize it for the existing designs. A researcher had developed a 2-input XOR gate using only 8 QCA cells with 0.50 clock cycles. Therefore, designers can start from here to further optimize the 2-input XOR gate with a single clock cycle.

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder (M2CSA) using single leaf cell i.e., 2–1 Multiplexer. M2CSA is designed using a new type of Excess-1 block. The Excess-1 block is designed in a distinct way using 2–1 multiplexers. The architectures of the proposed carry select adder and its internal excess-1 blocks are completely distinct when compared to existing carry select adders. The proposed 4-, 8-, 16-, 32-, and 64-bit M2CSAs use a 2–1 multiplexer only. The complex gates such as XOR gates are eliminated which exist in existing Carry Select Adders (CaSeAs). A 64-bit M2CSA that utilises one kind of 2-1 Mux cell is clearly decomposed to retain outstanding cell regularity. In previous designs, ripple carry adder blocks are substituted with half adders by limiting carry propagation to a particular degree. By avoiding carry propagation over adder blocks, particularly in 32- and 64-bit adders, the performance of M2CSA is initially increased. For CaSeAs, the area is of primary significance; for M2CSAs, it is also diminished by preserving cell regularity. Verilog HDL is utilised in the design of the M2CSA and current CaSeAs. Using Cadence NCLaunch, all of the designs are functionally tested. At a 90nm technology node, all of the designs are generated and executed using Genus and Innovus tools, respectively. As a comparison to prior designs, the 64-bit M2CSA final ASIC architecture is on average 17% less in terms of space. The comparison and result analysis show that 64-bit M2CSA performs 20% and 19% faster than 64-bit SQCSC in terms of performance and power dissipation, respectively.. The proposed 4-, 8-, 16-, 32-, 64- bit M2CSA exhibits less PDP (Power-Delay Product) ranging from 25%–30% concerning SQCSCs. Similarly, EDP (Energy- Delay Product) values for all the designs are calculated. The improvement in EDP for the 4-, 8-, 16-, 32-, 64- bit M2CSA is 41, 38, 42, 43, and 45 percentages compared to 4-, 8-, 16-, 32-, 64- bit SQCSC respectively. Therefore, the M2CSAs outperform the existing designs in terms of EDP by 38%–45%.

Low Area and Low Power Threshold Implementation Design Technique for AES S-Box

Threshold implementation (TI) is a promising countermeasure against side-channel attacks (SCA) in the presence of glitches. However, the hardware implementation of TI in S-box needs a large number of D flip-flops to synchronize intermediate signals, which results in a large silicon area and power consumption overhead. In this brief, we present the low area and low power TI design technique for advanced encryption standard (AES) S-box. In the proposed approach, instead of using D flip-flops, low-cost synchronization circuits such as customized tri-state XOR gates, tri-state buffers, and D latches are efficiently adopted with critical path replica (CPR) circuits. As a result, the proposed TI S-box implementation with 28nm CMOS process shows up to 33.7% area and 44.3% power savings. The security of the proposed TI AES S-box against side-channel attacks is also verified with test vector leakage assessment (TVLA) tests.

왼쪽 시프트 연산을 n-1번 사용하여 n비트 유한체 곱셈기 설계 및 구현

In this paper, we propose a finite fields GF(2n) multiplier algorithm by repeating the 2 multiplication algorithm n-1 times with a combination circuit composed only of AND and XOR gates. The proposed algorithm can be configured with fewer gates than the existing finite fields multiplication algorithm, and is expected to be easy to implement in hardware because it is very regular. Finally, the time to perform finite fields multiplication is also expected to be faster than other multiplication algorithms due to the smaller number of gates.

An active memristor based rate-coded spiking neural network

Neuromorphic computing is a novel computing paradigm that aims to mimic the behavior of biological neural networks for efficiently solving complex problems. While CMOS based neurons and synapses have been developed, they are limited in their ability to demonstrate bio-realistic dynamics. This, coupled with the fact that a huge number of these individual devices are required to build neurons and synapses, limits the scaling and power efficiency of such systems. A viable answer to this problem is neuromemristive systems that are based on memristor devices. These devices exhibit physical behaviors that can be related to the bio-physical dynamics of synapses and neurons. In this paper, a rate-coded all memristive “spiking neural network” (SNN) is presented. The proposed SNN is built with an active memristor neuron based on vanadium dioxide (VO2) coupled with a non-volatile memristor synapse. The results are validated by first simulating spiking versions of two Boolean functions viz., AND and XOR gates in SPICE. With features extracted from the small neural nets, a large-scale 3-layer spiking neural network is then simulated in Python which yields a validation accuracy of 87% on the MNIST dataset of handwritten digits. One of the prime features of this work is the realization of the XOR function using a single neuron which is not possible without the use of 2-layers of neurons in traditional neural networks. Another significant contribution is the utilization of a gradient-based learning approach for online training of a large-scale SNN. For this, we use the inherent activation function (Sigmoid/ReLU) of the proposed neuron design.

Size-Independent Reconfigurable Logic Gate with Bismuth Oxide Based Photoelectrochemical Device.

XOR gate, an important building block in computational circuits, is often constructed by combining other basic logic gates, and the hybridity inevitably leads to its complexity. A photoelectrochemical device could realize XOR function based on the current change of the photoelectrode; however, such signal is highly sensitive to photoelectrode size and therefore requires precise manufacturing at a high cost. Herein we developed a novel XOR gate based on the light-induced open-circuit potential (OCP) of the Bi2O3 photoelectrode. Surprisingly, the OCP of Bi2O3 does not increase with light intensity according to the traditional logarithmic relationship. Instead, an unusual decrease in OCP is observed at high light intensity, which is attributed to the dramatic light-induced increase in surface states that can be easily regulated by varying the oxygen partial pressure during reactive magnetron sputtering. Based on such a nonmonotonic variation of OCP, a facile Bi2O3-based gate is designed to realize the XOR function. Unlike the commonly used current signal, OCP is size independent, and therefore, the Bi2O3-based gate does not require high manufacturing accuracy. Moreover, in addition to XOR, the Bi2O3-based PEC gate also demonstrates great versatility in realizing other logic functions including AND, OR, NOT, NIH, NAND, and NOR. The strategy of modulating and applying nonmonotonic OCP signal opens a new avenue for designing size-independent reconfigurable logic gates at low manufacturing cost.

Design and analysis of Tbps all-optical gray code converter using photonic crystal-semiconductor optical amplifier-Mach–Zehnder interferometric structure

Future communication networks require the entire communication system to be all-optical to overcome the bandwidth constraints of electronics. All-optical devices play a vital role in supporting future networks, which demand a high speed of up to Tbps. An all-optical gray code converter operation was demonstrated numerically using a photonic crystal semiconductor optical amplifier (PhC-SOA) in a Mach–Zehnder interferometric (MZI) configuration at 1 Tbps for M-ary differential phase shift keying modulated binary and BCD inputs. The design achieved a very high extinction ratio of about 123.8 dB with a good quality factor value of about 45. The results show that PhC-SOA-based XOR and OR gates in the gray code converter design exhibits improved modulation features compared with traditional SOAs in our previous works.

A nano-scale n-bit ripple carry adder using an optimized XOR gate and quantum-dots technology with diminished cells and power dissipation

In the nano-scale era, quantum-dot cellular automata (QCA) technology has become an appealing substitute for transistor-based technologies. QCA will be the preferred technology for developing the next generation of digital systems. On the other hand, the full-adder and ripple carry adder (RCA) are the crucial building blocks of complex circuits, the most used structures in digital operations systems, and a practical part of the most well-known complex circuits in QCA technology. In addition, this technology was used to design the full adder for several procedures, like multiplication, subtraction, and division. For this reason, the full adder is generally investigated as a central unit and microprocessor in developing QCA technology. Furthermore, most previous QCA-based adder structures have suffered from some drawbacks, such as a high number of cells, high energy consumption, the high number of gates, and the placement of inputs and outputs in a closed loop; hence, the implementation of an efficient adder with only one gate and a low number of cells, such as exclusive-OR (XOR) gate, can solve all previous problems. Therefore, in this paper, a significantly improved structure of 3-input XOR is suggested based on the promising QCA technology. In addition, a QCA clocking mechanism and explicit cell interaction form the foundation of the proposed QCA-based XOR gate configuration. This gate can be easily converted into an adder circuit while containing a small number of cells and being extremely compressed. The suggested QCA-based XOR design is focused on optimizing a single-bit adder using cellular interaction. The suggested single-bit adder contains 14 cells. Based on this adder, several different RCAs, such as 4, 8, 16, and 32-bit, are designed. The comparison of the proposed single-bit adder to the best coplanar and multi-layer ones shows a 51.72% and 36.36% reduction of cells, respectively. In addition, all suggested designs are verified through simulation using QCADesigner and QCAPro. Finally, many physical validations are provided to approve the functionality of the suggested XOR design.