Abstract
In this paper, we propose a finite fields GF(2n) multiplier algorithm by repeating the 2 multiplication algorithm n-1 times with a combination circuit composed only of AND and XOR gates. The proposed algorithm can be configured with fewer gates than the existing finite fields multiplication algorithm, and is expected to be easy to implement in hardware because it is very regular. Finally, the time to perform finite fields multiplication is also expected to be faster than other multiplication algorithms due to the smaller number of gates.
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