Functional Clock Cycles Research Articles

Test Compaction by Test Removal Under Transparent Scan

This brief describes a new approach to test compaction under transparent scan. Transparent scan achieves higher levels of test compaction than possible with the conventional scan-based tests by interleaving scan shift cycles and functional clock cycles in arbitrary ways. Earlier approaches relied on the computation of a single transparent-scan sequence, and the omission of test vectors from it. However, a single transparent-scan sequence can be prohibitively long. In the approach described in this brief, a transparent-scan test set consists of several sequences whose lengths are limited. Test compaction is achieved by combining sequences into longer sequences that detect more faults, and removing from the test set entire sequences that become unnecessary. Experimental results for benchmark circuits demonstrate the ability of the procedure to achieve test compaction without creating prohibitively long transparent-scan sequences.

LFSR-Based Generation of Multicycle Tests

This paper describes a procedure for computing a multicycle test set whose scan-in states are compressed into seeds for a linear-feedback shift register, and whose primary input vectors are held constant during the application of a multicycle test. The goal of computing multicycle tests is to provide test compaction that reduces both the test application time and the test data volume. To avoid sequential test generation, the procedure uses a single-cycle test set to guide the computation of multicycle tests. The procedure optimizes every multicycle test, and increases the number of faults it detects, by adjusting its seed, primary input vector, and number of functional clock cycles. Optimizing the seed instead of the scan-in state avoids the computation of scan-in states for which seeds do not exist. Experimental results for benchmark circuits are presented to demonstrate the effectiveness of the procedure.

Piecewise-Functional Broadside Tests Based on Reachable States

This paper describes a new characterization of broadside tests that measures the proximity to functional operation conditions during their functional clock cycles, where delay faults are detected. Proximity to functional operation conditions is important for avoiding overtesting of delay faults. The new characterization considers a test as piecewise-functional based on its scan-in state. For functional operation conditions, the scan-in state must be a reachable state (a state that the circuit can enter during functional operation). However, using only reachable states as scan-in states limits the fault coverage that can be achieved. In a piecewise-functional broadside test, the scan-in state can be partitioned into substates that are also substates of reachable states. The paper presents a definition that allows every broadside test to be characterized as piecewise-functional. It also describes procedures for characterization, and for modification of broadside test sets so as to ensure that they create closer-to-functional operation conditions.

A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors

Test compaction can be achieved by using multicycle tests. To avoid the computationally intensive process of sequential test generation, multicycle tests can be generated by extending two-cycle tests. However, the scan-in state of a two-cycle test is not always effective for a multicycle test when the primary input vectors are held constant during the functional clock cycles of a test. This paper studies the extent of this issue by considering exhaustive two-cycle and multicycle test sets with constant primary input vectors for finite-state machine benchmarks. Based on the results of this study, it describes an efficient test compaction procedure that modifies selected two-cycle tests in a given test set in order to make them more effective as a source for multicycle tests with constant primary input vectors. Experimental results are presented to demonstrate the importance of this step to test compaction.

IJARCCE - Computer and Communication Engineering

2 Abstract: Low-power test generation procedure targets the switching activity during the fast functional clock cycles of broadside tests. The procedure is based on Test Cubes merging using Test Point Insertion that it extracts from functional broadside tests. Test cube merging supports test compaction and test point insertion improves fault coverage. The use of functional broadside tests provides a target for the switching activity of low-power tests, not exceeding the switching activity that is possible during functional operation. The use of test cubes that are extracted from functional broadside tests is a unique feature. It ensures that the low-power tests would create functional operation conditions in sub circuits that are defined by the test cubes and test point insertion reduces the complexity involved in detecting additional faults. Experimental results show that the procedure detects all or almost all the transition faults that are detectable by arbitrary (functional and non-functional) broadside tests in benchmark circuits. The simulation results are obtained using MODELSIM 6.3f and the power is analysed using XILINX 8.1 software.

English

In the proposed method we are test the S27 sequential circuit by using Built in Self Test.This paper describes an on-chip test generation method for functional broadside tests. The hardware was base on the application of primary input sequences initial from a well-known reachable state, therefore using the circuit to produce additional reachable states. Random primary enter sequences were changed to avoid repeated synchronization and thus defer varied sets of reachable states. Functional broadside tests are two-pattern scan based tests that avoid over testing by ensuring that a circuit traverses only reachable states in the functional clock cycles of a check. These consist of the input vectors and the equivalent responses. They check for proper operation of a verified design by testing the internal chip nodes. Useful tests cover a very high percentage of modeled faults in logic circuits and their generation is the main topic of this method. Often, functional vectors are understood as verification vectors, these are used to verify whether the hardware actually matches its specification. Though, in the ATE world, any one vectors applied are understood to be functional fault coverage vectors applied during developing test. This paper show the on chip test Generation for a bench mark circuit using simple fixed hardware design with small no of parameters altered in the design for the generation of no of patterns. If the patterns of the input test vector results a fault simulation then circuit test is going to fail.

Low-Power Test Generation by Merging of Functional Broadside Test Cubes

This paper describes a low-power test generation procedure, which targets the switching activity during the fast functional clock cycles of broadside tests. The procedure is based on merging of test cubes that it extracts from functional broadside tests. The use of test cube merging supports test compaction and it can be used for accommodating the constraints of test data compression. The use of functional broadside tests provides a target for the switching activity of low-power tests, which does not exceed the switching activity that is possible during functional operation, or that the circuit is designed for. The use of test cubes that are extracted from functional broadside tests is a unique feature of this procedure. It ensures that the low-power tests would create functional operation conditions in subcircuits that are defined by the test cubes. Experimental results show that the procedure detects all or almost all the transition faults that are detectable by arbitrary (functional and nonfunctional) broadside tests in benchmark circuits.

Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks

An approach to test application called transparent scan provides an opportunity to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. A transparent-scan sequence for one block is likely to detect faults in other blocks since transparent scan does not distinguish between functional and scan clock cycles, and allows faults to be detected at all the clock cycles of the sequence. Such sharing of tests is not meaningful with conventional scan-based tests, especially when the blocks have different numbers of state variables. Transparent scan thus enhances the ability to produce a compact test set for a group of logic blocks. The static test compaction procedure described in this paper uses transparent-scan sequences that follow the application of conventional scan-based tests precisely. The procedure obtains a set of transparent-scan sequences for a group of logic blocks from compacted test sets for the logic blocks in the group. From this set, it selects a subset that detects all the target faults, which are detected by the complete set.

Multi‐cycle broadside tests with runs of constant primary input vectors

Multi-cycle tests, with two or more functional clock cycles between scan operations, can be used for test compaction. When tester limitations prevent primary input vectors from being changed at-speed, one of the possible solutions is to hold the primary input vector constant during the functional clock cycles of a multi-cycle test. However, this limits the level of test compaction that can be achieved. To provide an alternative to this solution, a new type of multi-cycle tests has been defined, where the primary input vector is changed during a clock cycle that is applied under a slow clock. This is followed by a run of the same vector applied under a fast clock. Transition faults are activated during the clock cycles that are applied under a fast clock. A test generation procedure that produces such test sets for transition faults has also been described. Experimental results demonstrate that the new type of tests can improve the ability to produce a compact test set for certain benchmark circuits.

Design-for-testability for multi-cycle broadside tests by holding of state variables

This article describes a design-for-testability approach for increasing the transition fault coverage of multi-cycle broadside tests. Earlier methods addressed two-cycle tests. The importance of multi-cycle tests results from the ability to produce more compact test sets than possible with two-cycle tests, from the fact that when multi-cycle tests are applied at-speed, they can detect defects that are not detected by two-cycle tests and from their ability to avoid overtesting of delay faults. The approach described in this article is based on holding the values of selected state variables constant during the functional clock cycles of a multi-cycle broadside test. This allows new tests to be produced, which are different from broadside tests, without relying on nonfunctional toggling of state variables as in earlier methods for two-cycle tests. Experimental results show significant improvements in transition fault coverage using a fixed set of hold configurations for two types of multi-cycle broadside test sets: (1) test sets that are stored and applied from an external tester, and (2) functional broadside test sets that are generated using on-chip hardware.

Low-power skewed-load tests based on functional broadside tests

This article studies the generation of low-power skewed-load tests such that the signal transitions (and line values) they create during their fast functional clock cycles match those of functional broadside tests. Functional broadside tests create functional operation conditions during their fast functional clock cycles. As a result, the signal transitions that occur during these clock cycles can also occur during functional operation. The procedure described in this article matches these signal-transitions on a line-by-line basis when generating low-power skewed-load tests. The procedure accepts a functional broadside test set for transition faults. In one of its basic steps, the procedure modifies a functional broadside test into a skewed-load test. This allows it to retain many of the signal transitions (and line values) of the functional broadside test in the skewed-load test. Experimental results for benchmark circuits demonstrate the extent to which it is possible to match the signal-transitions of skewed-load tests with those of functional broadside tests while achieving the high transition fault coverage that is typical of skewed-load tests.

Reducing the input test data volume under transparent scan

Under an approach to test compaction called transparent scan, a scan circuit is considered as a sequential circuit where the scan-chain inputs and scan-select input are included in the set of inputs of the circuit. This provides the flexibility to interleave functional and scan clock cycles in arbitrary ways, and enhances the ability of transparent-scan sequences to detect target faults. These features are used in this study for reducing the input test data volume by using the same scan-chain input sequences with different scan-select sequences to define transparent-scan sequences. The circuits under consideration have a scan chain that includes their state variables, primary inputs and primary outputs. Scan-chain input sequences are computed based on a given conventional scan-based test set that includes compacted single-cycle and two-cycle test sets for single stuck-at and transition faults, respectively. The set of scan-select sequences is fixed. Using the same scan-chain input sequences for defining several transparent-scan sequences, with different scan-select sequences, allows more faults to be detected with the same set of scan-chain input sequences. This allows the number of scan-chain input sequences to be reduced compared with the number of tests in the conventional scan-based test set.

Functional Broadside Templates for Low-Power Test Generation

This brief describes a new approach to low-power test generation targeting the maximum switching activity during the fast functional clock cycles of broadside tests. This brief defines functional broadside templates as incompletely-specified broadside tests, which capture the signal-transitions that occur during the fast functional clock cycles of functional broadside tests. The same signal-transitions can occur during functional operation. Therefore, functional broadside templates can guide the generation of low-power test sets when the goal is to match the power dissipation that is possible during functional operation on a line-by-line basis. This brief describes a procedure for computing functional broadside templates from completely-specified functional broadside tests, and a low-power test generation procedure for transition faults based on templates.

On multi‐cycle test cubes

This article studies the generation of test sets that consist of multi-cycle test cubes. Such test cubes have partially-specified scan-in states, and several functional clock cycles between scan operations. Test cubes are important for test data compression. In addition, multi-cycle tests can detect delay defects that are not detected by single-cycle tests. The use of multi-cycle test cubes is shown to reduce the number of test cubes required for detecting single stuck-at faults compared with the case where single-cycle test cubes are used. This article also shows that a multi-cycle test cube for a single stuck-at fault can have fewer specified scan-in values than a single-cycle test cube for the same fault. As a result, multi-cycle test cubes can be more effective for test data compression. This article also discusses the conditions under which multi-cycle test cubes can be merged in order to further reduce the number of test cubes in a test set.

Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests

The scan-in states of functional broadside tests are reachable states, which are states that the circuit can enter during functional operation. This is used for ensuring functional operation conditions during the functional clock cycles of the tests. For a partially-functional broadside test, the scan-in state has a known Hamming distance to a reachable state. This ensures measurable deviations from functional operation conditions during the functional clock cycles of the test. It is important for addressing overtesting as well as excessive power dissipation. This brief develops a fault-simulation procedure for transition faults under arbitrary (functional and nonfunctional) broadside tests that considers the tests as partially-functional broadside tests. The procedure can be used for evaluating the proximity to functional operation conditions of arbitrary broadside test sets. For illustration, the procedure is used for comparing a low-power test set with an arbitrary broadside test set.

Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure

Functional broadside tests are two-pattern scan-based tests that avoid overtesting by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test. In addition, the power dissipation during the fast functional clock cycles of functional broadside tests does not exceed that possible during functional operation. On-chip test generation has the added advantage that it reduces test data volume and facilitates at-speed test application. This paper shows that on-chip generation of functional broadside tests can be done using a simple and fixed hardware structure, with a small number of parameters that need to be tailored to a given circuit, and can achieve high transition fault coverage for testable circuits. With the proposed on-chip test generation method, the circuit is used for generating reachable states during test application. This alleviates the need to compute reachable states offline.

Low-power test sets under test-related primary input constraints

This paper considers the generation of low-power test sets under test-related primary input constraints. Such constraints are used for addressing tester limitations related to the application of tests at-speed. Specifically, the paper considers the switching activity which measures the power dissipation during the fast functional clock cycles of broadside tests with constrained primary input vectors. For a functional broadside test, the switching activity during the fast functional clock cycle is guaranteed not to exceed the switching activity possible during functional operation. Therefore, functional broadside tests are appropriate as low-power tests. In addition, the switching activity of functional broadside tests can be used for bounding the switching activity of other tests in a low-power test set. The paper observes that functional broadside tests for computing the bound should be generated under the same primary input constraint as the low-power test set. This is important since primary input constraints affect the switching activity possible in parts of the circuit that are influenced by the primary inputs. It helps ensure that the switching activity in other parts of the circuit will not be higher, or not be restricted to be lower, than during functional operation.

Undetectable transition faults under broadside tests with constant primary input vectors

In a broadside test, a scan-in operation is followed by two functional clock cycles where primary input vectors, denoted by v0 and v1, are applied. Because of tester limitations that prevent the primary input vectors from being changed at speed, broadside tests are computed under the constraint where v0=v1. This results in a loss of delay fault coverage. This study develops a fast procedure for identifying transition faults that are undetectable by broadside tests under the constraint v0=v1. Faults that are undetectable because of this constraint are undetectable because of tester limitations and not because of the logic in the circuit. These faults may be able to affect the circuit during functional operation, when the primary input vectors are unconstrained. In this case the faults are important to detect. A fast procedure for identifying undetectable transition faults under the constraint v0=v1 provides a quantitative measure of the effect of this constraint on the achievable fault coverage without performing test generation. If it turns out that the effect on fault coverage is unacceptable, other solutions may be used without first performing test generation.

Generation of Multi-Cycle Broadside Tests

The use of multi-cycle (or multi-pattern) tests for delay faults can reduce the number of clock cycles required for test application, and enhance the ability of a test set to detect delay defects. This is achieved by exercising the circuit in functional mode for several clock cycles as part of each test. This advantage is especially important for multi-pattern functional broadside tests, which guarantee normal functional operation conditions during the functional clock cycles of the test. This paper describes a procedure for generating multi-pattern broadside tests. The procedure extends a two-pattern test set gradually to increase the number of patterns included in each test while reducing the number of tests. Experimental results demonstrate that significant reductions in the numbers of clock cycles are possible with the proposed procedure for both functional and arbitrary broadside test sets.

Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits

This paper describes a design for testability (DFT) approach for synchronous sequential circuits that combines scan with nonscan DFT in a transparent way. DFT control inputs and scan chain inputs are used as primary inputs of the circuit, and scan chain outputs are used as primary outputs of the circuit during test generation to eliminate the distinction between functional clock cycles and the various types of nonfunctional clock cycles. The result is 1) short test application times due to the nonscan DFT modes and the ability to use limited scan operations and 2) the ability to detect all the combinationally irredundant faults due to the scan mode