Fully-depleted SOI Research Articles

Non-Linear Coupling Effects in Fully Depleted SOI Transistors

Experimental results show the response of 22 nm fully depleted silicon on insulator (FDSOI) transistors to 10 keV x-rays. The extracted coupling factor between the front and back-gates of the device shows a divergence from the traditionally assumed coupling factor exhibiting a non-linear dependence on total ionizing dose (TID). A depletion region in the well under the buried oxide is included in the model of the device. The coupling factor is rederived using the new model following the previous derivation. The new coupling factor has a dependence on TID received by the device. Verification of the new model is performed with comparisons to the experimental data and technology computer aided design (TCAD) simulations. The new model fits well to data and simulations.

Machine Learning-Assisted Statistical Variation Analysis of Ferroelectric Transistor: From Experimental Metrology to Adaptive Modeling

A novel machine learning (ML)-assisted approach is proposed for investigating the variability of ferroelectric field-effect transistor (FeFET) to shorten the loop of technology pathfinding. To quantify the ferroelectric (FE) domain variation, the atomic intragranular misorientation of Si-doped HfO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> thin film is measured by transmission Kikuchi diffraction (TKD) and is transformed into a polarization map. With the metrology data, polarization variation (PV) of FE domains on the gate-stack is modeled in technology computer-aided design (TCAD) to assess the impact of PV on the FeFET performance and to obtain datasets for ML-assisted analysis. A neural network model is trained using the datasets (input: polarization maps; output: high/low threshold voltage, ON-state current, and subthreshold slope) for the 28-nm bulk FeFET analysis. Our trained network, if used for inference to obtain three-sigma statistics, shows <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula> 98% of accuracy of the device features and significantly faster simulation time than TCAD. In addition, we used the transfer learning technique to reduce the number of training datasets by 83% for the fully depleted silicon-on-insulator (FDSOI) FeFET by applying the pretrained model from the bulk FeFET.

Efficacy of Transistor Stacking on Flip-Flop SEU Performance at 22-nm FDSOI Node

Fully depleted silicon-on-insulator (FDSOI) technology nodes offer better single-event performance compared with comparable bulk technologies. However, upsets are still possible at nanoscale feature sizes and additional hardening techniques need to be explored. Single-event upset (SEU) performance of multiple flip-flop designs using the stacked-transistor hardening technique at a 22-nm FDSOI technology node is presented in this paper. Irradiation results show significant reductions in SEU cross-sections for stacked-transistor-based hardened designs compared to a conventional design. Alpha particle exposures showed zero upsets for all D-Flip-Flop (DFF) designs tested. When exposed to heavy-ions, the stacked-transistor DFF design showed a 17X improvement over a conventional DFF design at an LET value of 47 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg. The stacked-transistor design with the charge-cancelling technique showed upsets when particle LET exceeded 93.8 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg and at a high angle of incidence. The stacked-transistor design with the interleaving technique showed zero upsets for all test conditions.

Fully-Depleted Silicon-on-Insulator (FDSOI) Based Complementary Phototransistors for In-Sensor Vector-Matrix Multiplication

Two type CMOS-compatible complementary phototransistors (CPTs) with NMOS or PMOS transistor are proposed in this work for in-sensor vector-matrix multiplication (VMM). The CPT is fabricated by the 22nm FDSOI process technology and composed of a MOSFET with a p-doped well under the buried oxide (BOX). The well serves for photoelectron generation and affects the on-state current of the MOSFET by the photoelectrons. The bidirectional and tunable photoresponsivity characteristics as well as the optical-electrical signed multiplication operation (average error < 2.5%) are experimentally demonstrated in the pair of CPTs. The in-sensor VMM is verified by typical artificial neural networks using the CPT array as the image-input layer. Simulated results show slight inference accuracy losses (< 1%) in LeNet3 for MNIST and VGG11/VGG16 for CIFAR-10 recognition.

A Fully Differential Analog Front-End for Signal Processing from EMG Sensor in 28 nm FDSOI Technology

This paper presents a novel analog front-end for EMG sensor signal processing powered by 1 V. Such a low supply voltage requires specific design steps enabled using the 28 nm fully depleted silicon on insulator (FDSOI) technology from STMicroelectronics. An active ground circuit is implemented to keep the input common-mode voltage close to the analog ground and to minimize external interference. The amplifier circuit comprises an input instrumentation amplifier (INA) and a programmable-gain amplifier (PGA). Both are implemented in a fully differential topology. The actual performance of the circuit is analyzed using the corner and Monte Carlo analyses that comprise fifth-hundred samples for the global and local process variations. The proposed circuit achieves a high common-mode rejection ratio (CMRR) of 105.5 dB and a high input impedance of 11 GΩ with a chip area of 0.09 mm2.

Understanding conditions for the single electron regime in 28 nm FD-SOI quantum dots: Interpretation of experimental data with 3D quantum TCAD simulations

Single electrons trapped in quantum dots hosted in silicon nanostructures are a promising platform for the implementation of quantum technologies. In this study, we investigated the required conditions to attain the single-electron regime in an Ultra-Thin Body and Buried oxide (UTBB) Fully Depleted Silicon-On-Insulator (FD-SOI) quantum dot device fabricated using the standard manufacturing process of STMicroelectronics. The cryogenic temperature operation of the quantum dot device is simulated and analyzed using the 3D Quantum Technology Computer Aided Design (QTCAD) software developed by Nanoacademic Technologies, achieving convergence down to 1.4 K. We report here simulations exploring single-electron occupancy of a single side-gate activated corner quantum dot and compare them to experimental data collected from the measurements on a device with the same geometry.

Compact CMOS-Compatible Majority Gate Using Body Biasing in FDSOI Technology

This is the first work that employs the body biasing feature, available in fully depleted silicon on insulator (FDSOI) technology nodes, to build CMOS-compatible compact majority (MAJ) and minority (MIN) logic gates. Compared to their CMOS counterpart, our novel MAJ/MIN gates exhibit considerably fewer transistors, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {2.3} \times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {2} \times $ </tex-math></inline-formula> , respectively. The use of MAJ/MIN gates for logic synthesis has been widely investigated in the literature since any function can be realized using only these two gates. Nevertheless, the use of MAJ/MIN gates to synthesize circuits remained very limited because such gates are area hungry when implemented using conventional standard cells. Therefore, state-of-the-art research in the last decade has extensively focused on exploring beyond-CMOS technologies to build alternative MAJ/MIN gates. However, such emerging technologies are still immature and suffering considerably from variability. On the other hand, our novel FDSOI-based MAJ/MIN gates are based on mature CMOS commercial technologies. Our analysis of the proposed gates has been conducted using accurate SPICE simulations with an industry-compact transistor model, BSIM-IMG, calibrated for an industrial 14nm FDSOI technology. Using our developed MAJ/ MIN synthesis and error injection framework called MAJinBoo, we demonstrate that MAJ/MIN-based circuits exhibit an outstanding resiliency against errors due to the inherent voting-based computing. This encourages the employment of our MAJ/MIN gates in safety-critical applications where reliability is a prime concern. Our MAJinBoo framework is available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/Brunno815/MAJinBoo</uri> .

On the Zero Temperature Coefficient in Cryogenic FD-SOI MOSFETs

In this article, we propose an explanation of the origin of the zero-temperature coefficient (ZTC) in fully depleted-silicon on insulator (FD-SOI) MOSFETs capacitance curves from room to cryogenic temperature. It is demonstrated that the ZTC is a natural consequence of the Fermi–Dirac function controlling the carrier population. Moreover, based on transport analysis in linear region, it is proven that the ZTC point is preserved in the drain current transfer characteristics only if the mobility varies as the reciprocal temperature, i.e., if it is purely phonon scattering-limited. The inclusion of other defective scattering mechanisms dispels the ZTC point. Finally, the model developed is validated by some TCAD simulations down to deep cryogenic temperatures.

Impact of thermal coupling effects on the digital and analog figures of merit of UTBB SOI MOSFET pairs

This work studies the thermal cross-coupling between two side-by-side UTBB (ultra-thin body and ultra-thin BOX) fully-depleted Silicon-on-Insulator (FD-SOI) MOSFETs. Due to the operation (i.e. heating) of the neighbor (actuator) device, the temperature of the measured device increases, which deteriorates its electrical parameters. This degradation is studied as a function of the bias applied to (i.e. power dissipated by) the neighbor device on main digital (SS, VTh and Ion/Ioff) and analog (gm, gm/Id and Av) Figures of Merit as well as the 2nd and 3rd order harmonic distortions (HD2 and HD3).

Characteristics and deviation of low-temperature FD-SOI-MOSFETs using a sputtering SiO2 gate insulator

A fully depleted silicon-on-insulator (FD-SOI) MOSFET using a low-temperature sputtering SiO2 gate insulator (GI) was fabricated via a resistless process without a cleanroom. The resultant average characteristics with standard deviations were field-effect mobility (μ n) and subthreshold swing (ss) values of 612 ± 37 cm2 Vs−1 and 135 ± 18 mV dec−1, respectively. These were compared with our previous single-crystal thin-film transistors (TFTs) on glass substrates with μ n of 339 ± 116 cm2 Vs−1 and ss of 255 ± 24 mV dec−1, and it was inferred that the inferior ss in TFTs originated from poor bottom Si/SiO2 interface quality with a trap density of 1 × 1012 cm−2 V−1. Furthermore, it was demonstrated that to achieve TFT characteristics similar to those of the FD-SOI-MOSFET, the top interface trap density and bottom interface quality had to be lower than 1 × 1011 cm−2 V−1.

An improved subthreshold swing expression accounting for back-gate bias in FDSOI FETs

In a MOSFET transistor, the subthreshold swing defines the switching efficiency, and the associated slope factor, or so-called body factor, is a critical parameter in charge-based models. However, in an advanced Fully-Depleted Silicon-On-Insulator (FDSOI) process, the slope factor is influenced by a strong back gate coupling due to a thin buried oxide (BOX). A conventional constant expression cannot describe the slope factor at various back-gate voltages. Therefore, this paper proposes a general slope factor expression for front- and back-gate transfer characteristics of long-channel FDSOI MOSFETs in a strong gate coupling. The proposed expression is a continuous function of the surface potential difference between the front and back sides, which explains the slope factor behavior versus the back-gate voltage. Besides, the systematic study is presented for the front/back interface states. The proposed model is applied to evaluate the down-scaling of FDSOI technologies in terms of the gate-coupled slope factor. The scaling in the buried oxide layer degrades the front slope factor, which a thinner channel or a reverse body bias can compensate for at the cost of a higher vertical electric field. Compared to the SiO2, the application of high-κ dielectric for the buried oxide layer shows a better stand to the degraded slope factor by the interface states.

Low Thermal Budget Reconfigurable Fully Depleted Silicon on Insulator Field-Effect-Transistors With Embedded Boolean Logic

We report the low thermal budget reconfigurable fully depleted silicon on insulator (FDSOI) field-effect-transistors, focusing on the management of the fabrication thermal budget, toward three-dimensional integration and the further improvement of the circuit functionality. This is realized using atomic layer deposition tool-enabled O2/NH3 plasma surface passivation technology and long duration thermal procedure. Moreover, such front-gated FDSOI reconfigurable field effect transistors (RFETs) gain the embedded Boolean logic of “AND” and “NOR” in N and P-type modes, respectively. This strategy has the potential to be a key enabler for functional improvement in the nanoscale hyper-scaling era.

Study on low rate of change characteristics of saturation output current of 28 nm UTBB FDSOI at 300 °C high-temperature

Partially-depleted silicon-on-insulator (PDSOI) MOSFETs with full dielectric isolation structure are widely used in the high temperature field of 225 °C, but affected by the threshold voltage and carrier mobility, the saturated output current has a rate of change as high as 24.9% at 25 °C–300 °C, which will reduce the working speed and accuracy of the analog circuit. This paper studies the high temperature output current characteristics of ultra-thin body and buried oxide (UTBB) fully-depleted silicon-on-insulator (FDSOI) MOSFETs with the 28 nm low voltage threshold structure. The experimental results show that when the gate voltage of the device is constant, the saturation current change of 28 nm short-channel FDSOI device is 1.93% in the temperature range from 25 °C to 300 °C, which is 12.9 times more stable than that of 0.13 μm PDSOI device, 4.5 times and 8.4 times higher than that of 0.3 μm and 2 μm long-channel FDSOI device. When the gate voltage of the device drifts from the zero-temperature coefficient (ZTC) point by ±10%–±20%, the output current change of the short-channel FDSOI device is still the lowest. It is proved by theory and simulation that the low temperature change rate of the carrier velocity of the short-channel FDSOI device is the main factor affecting the stability of the output current. From the analysis of the saturation current model and the ZTC operating point, reducing the gate operating voltage of the device or increasing the threshold voltage of the device can further improve the stability of the output current at high temperatures. The research in this paper proves that the 28 nm UTBB FDSOI device has good high temperature saturation current stability, which can well meet the output current stability requirements of high temperature analog circuits.

FD-SOI-Based Pixel With Real-Time Frame Difference for Motion Extraction and Image Preprocessing

A frame differencing pixel (FDP) design based on fully depleted silicon-on-insulator (FD-SOI) technology is presented, demonstrating the capability of the FDP to perform pixel-level real-time frame difference (FD) for motion extraction and image preprocessing. The photo charges are collected by the diode under the buried oxide (BOX) and sensed by the MOSFET above. The capacitance of the BOX is used to generate the FD signal without incurring more area costs. TCAD simulations of the FD-SOI FDP were performed to help the analysis. An optimal pixel design model was developed to describe the relationship between noise performance and area allocation. According to the simulation results, the FDP could achieve light sensitivity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25.6 ~\mu \text{A}$ </tex-math></inline-formula> /( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{J}$ </tex-math></inline-formula> /cm2) and a differential signal-to-noise ratio of 35 dB with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4 ~\mu \text{m}$ </tex-math></inline-formula> pixel pitch and 76% fill factor.

A Reconfigurable RF Filter With 1%–40% Fractional Bandwidth for 5G FR1 Receivers

This paper presents a radio frequency front-end (RFFE) for 5G New Radio (NR) receivers operating in Frequency Range 1 (FR1). The core of this RFFE is a synthetic fourth-order Q-enhanced RF filter employing gm-boosting, noise-cancelling, capacitive cross-coupling, and forward body-biasing techniques to achieve 1.7 GHz to 6.4 GHz operating range and 1 adjustable fractional bandwidth (FBW). The function of the filter is based on subtracting out-of-phase signals in the passband and in-phase signals in the stopband. Two Q-enhanced LC resonators are utilized for outphasing. The filter is preceded by a low-noise transconductance amplifier, and it is followed by a programmable gain amplifier and a differential buffer stage for the measurement purposes and gain equalization. The experimental results demonstrate that the voltage gain is tunable between 18 and 47 dB with 0.2 dB steps, which leads to an equalized output power in all the filter configurations. Fabricated in 22 nm Fully Depleted Silicon on Insulator (FD-SOI) technology, the RFFE achieves 4.6 dB NF, -14 dBm IB-IIP3, and 26 dBm IB-IIP2 at 4 GHz. Notably, the fourth-order steep roll-off provides 22 dBm OOB-IIP3 at 2WBW frequency offset. The entire RFFE draws 22-45 mA from a 1 V supply and the filter core occupies 0.11 mm2 chip area.

Mechanism of Random Telegraph Noise in 22-nm FDSOI-Based MOSFET at Cryogenic Temperatures

In the emerging process-based transistors, random telegraph noise (RTN) has become a critical reliability problem. However, the conventional method to analyze RTN properties may not be suitable for the advanced silicon-on-insulator (SOI)-based transistors, such as the fully depleted SOI (FDSOI)-based transistors. In this paper, the mechanism of RTN in a 22-nm FDSOI-based metal-oxide-semiconductor field-effect transistor (MOSFET) is discussed, and an improved approach to analyzing the relationship between the RTN time constants, the trap energy, and the trap depth of the device at cryogenic temperatures is proposed. The cryogenic measurements of RTN in a 22-nm FDSOI-based MOSFET were carried out and analyzed using the improved approach. In this approach, the quantum mechanical effects and diffuse scattering of electrons at the oxide-silicon interface are considered, and the slope of the trap potential determined by the gate voltage relation is assumed to decrease proportionally with temperature as a result of the electron distribution inside the top silicon, per the technology computer-aided design (TCAD) simulations. The fitted results of the improved approach have good consistency with the measured curves at cryogenic temperatures from 10 K to 100 K. The fitted trap depth was 0.13 nm, and the decrease in the fitted correction coefficient of the electron distribution proportionally with temperature is consistent with the aforementioned assumption.

A Compact Model for Single-Event Transient in Fully Depleted Silicon on Insulator MOSFET Considering the Back-Gate Voltage Based on Time-Domain Components

FDSOI (Fully Depleted Silicon On Insulator) devices have a good performance in anti-single-event circuits. However, the bipolar amplification effect becomes a severe problem due to the buried oxide. The previous models for Single Event Transient (SET) of FDSOI did not fully consider the current of all components. Most importantly, they did not take the influence of the back-gate voltage into account. Thus, this paper presents a modeling method for the SET current in FDSOI MOSFET where all three components are modeled individually. The prompt current and diffusion current are modeled with a current source respectively. The Berkeley Short-channel IGFET Model for Silicon-on-Insulator (BSIMSOI) model is integrated into this model to calculate the bipolar amplification current. Compared to using the bipolar transistor model, this method avoids additional current input from the base electrode. It is more consistent with the mechanism of bipolar amplification effect for FDSOI devices without body contact. Instantaneously, an improved model is proposed that considers the influence of the back-gate voltage on the SET of the FDSOI devices. All models are validated through Technology Computer Aided Design (TCAD)simulation results.

Prospects for applying FD-SOI technology to space applications

In this work, using numerical simulation, the reasons for the occurrence of increased values of leakage currents in NMOS fully depleted SOI (FD-SOI) transistors during interaction with ionizing radiation. It has shown that the main reason for the formation of leakage currents is the charge accumulated in the latent oxide upon interaction with ionizing radiation. The effectiveness of applying a bias on the substrate and the formation of a well under the buried oxide (BOX) to reduce the leakage currents is investigated. Based on the obtained results, it was concluded that it is promising to use transistors made using FD-SOI technology for space applications.

Three-to-one analog signal modulation with a single back-bias-controlled reconfigurable transistor

Reconfigurable field effect transistors are an emerging class of electronic devices, which exploit a structure with multiple independent gates to selectively adjust the charge carrier transport. Here, we propose a new device variant, where not only p-type and n-type operation modes, but also an ambipolar mode can be selected solely by adjusting a single program voltage. It is demonstrated how the unique device reconfigurability of the new variant can be exploited for analog circuit design. The non-linearity of the ambipolar mode can be used for frequency doubling without the generation of additional harmonics. Further, phase shifter and follower circuits are enabled by the n- and p-type modes, respectively. All three functions can be combined to create a 3-to-1 reconfigurable analog signal modulation circuit on a single device enabling wireless communication schemes. Both, the concept as well as the application have been experimentally demonstrated on industrial-scale fully-depleted SOI platform. The special transport physics in those structures has been analyzed by TCAD simulations as well as temperature dependent measurements.

-Band Class-B VCO in 22 nm FD-SOI With Inductive Source Degeneration of the Tail Current Source

In this work, a voltage-controlled oscillator (VCO) in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band has been introduced that uses the proposed technique named “inductive source degeneration of the tail current source.” The contribution of this work is that the auxiliary resonator is placed differently than the conventional works so that it leads to a more compact solution without affecting the phase noise (PN). Based on the simulation results, for the same device sizes and power consumption, the proposed Class-B method reduces the PN by 1.5 dB than the conventional one at 1 MHz offset from 24 GHz center frequency. VCO has been fabricated on a die area of 0.026 mm2 in the 22 nm fully depleted silicon on insulator (FD-SOI) technology. The measurement was done in the free-running mode, and the results show a PN of −122.4 dBc/Hz at 10 MHz offset from the center frequency of 23.8 GHz. The power consumption of the VCO core is 14.4 mW with 1 V supply voltage. According to the measurement results, this work achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\text {FoM}_{A}}$ </tex-math></inline-formula> , a figure of merit which considers the VCO core area, of −194.2 dBc/Hz at 10 MHz offset from the center frequency, featuring state-of-the-art among the CMOS VCOs in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band.