Characteristics and deviation of low-temperature FD-SOI-MOSFETs using a sputtering SiO2 gate insulator

Abstract

A fully depleted silicon-on-insulator (FD-SOI) MOSFET using a low-temperature sputtering SiO2 gate insulator (GI) was fabricated via a resistless process without a cleanroom. The resultant average characteristics with standard deviations were field-effect mobility (μ n) and subthreshold swing (ss) values of 612 ± 37 cm2 Vs−1 and 135 ± 18 mV dec−1, respectively. These were compared with our previous single-crystal thin-film transistors (TFTs) on glass substrates with μ n of 339 ± 116 cm2 Vs−1 and ss of 255 ± 24 mV dec−1, and it was inferred that the inferior ss in TFTs originated from poor bottom Si/SiO2 interface quality with a trap density of 1 × 1012 cm−2 V−1. Furthermore, it was demonstrated that to achieve TFT characteristics similar to those of the FD-SOI-MOSFET, the top interface trap density and bottom interface quality had to be lower than 1 × 1011 cm−2 V−1.