Full Search Block Matching Research Articles

Modified block-matching algorithm for moving object tracking in video surveillance

Video surveillance has risen as one of the most promising methods for people who live alone in their dwellings. Few video surveillance innovations have recently been introduced. However, due to various changes in illumination, abrupt shifts in target appearance, identical non-target artifacts in the background, and occlusions, developing a reliable video surveillance algorithm remains a difficult challenge. This work attempts to introduce a new framework for moving object detection and tracking by following four major phases: “Video-to-Frame Conversion, Pre-Processing, Background Subtraction, Feature-Based Multi-object Detection, Multi-object Tracking by Filtering”. Initially, in the Video-to-Frame Conversion process, the recorded input video clips are transformed into distinct frames. During pre-processing, the noise is removed from the video frame using a filtering approach, and thereby the nature of the images will be enhanced. In the proposed work, a Weiner filter is used to remove noise and other undesirable features during the pre-processing. Then, to distinguish the frontal areas of objects, background subtraction is performed using the neutrosophic set in noiseless video frames (pre-processed frames). The objects in the background-subtracted frames are separated using Improved Region Growing (IRG) segmentation model in the Feature-Based Multi-object Detection phase. The objects in the frames are determined from this segmented image. The Modified Full Search Algorithm is being used to track the object (motion estimation) on the video frame after it has been identified in the segmented phase. The Modified full search block matching algorithm (MFSA) is introduced in this research work to find the appropriate mobility. Promising results have been obtained by the proposed work, and also the mathematical excellence of the new method is also proven over other state-of-the-art models.

A Novel Improved Multi-Point Matching Based Coronary Disease Quantitative Analysis for Speckle Tracking in Ultrasound Image

Ultrasonic imaging technology is one of the most direct and effective methods, which can prevent, treat cardiovascular disease, and it can make noninvasive observation and detection of cardiac motion. To calculate accurate myocardial motion parameters more directly, effectively and accurately, speckle tracking algorithm is put forward. However, the performance of speckle tracking is directly related to the diagnosis effect of coronary disease. Compared with the speckle tracking algorithm based on optical flow algorithm, the speckle tracking algorithm based on block matching algorithm has advantages of higher tracking accuracy and faster computation speed and better anti-interference immunity. According to the requirements of clinical application, the full search block matching algorithm whose accuracy is the highest is adopted as the basic algorithm of the speckle tracking algorithm. In paper, In view of the shortcomings of the full search block matching algorithm, the algorithm based on calculating tracking error is proposed. The speckle tracking algorithm based on calculating tracking error has good tracking results, which shows that this algorithm can effectively improve the applicability, stability and accuracy of tracking in different ultrasound images and multi-point tracking in the same ultrasound images.

Energy efficient processing of motion estimation for embedded multimedia systems

Visual sensor networks require low power compression techniques of large amount of video data in each camera node due to the energy-constrained and bandwidth-limited environments. In this paper, energy-efficient architecture for Variable Block Size Motion Estimation is proposed to fully utilize dynamic partial reconfiguration capability of programmable hardware fabric in distributed embedded vision processing nodes. Partial reconfiguration of FPGA is exploited to support run-time reconfiguration of the proposed modular hardware architecture for motion estimation. According to the required search range, hardware reconfiguration is performed adaptively to reduce the hardware resources and power consumption. A reconfigurable ME ranging from simple 1-D to a complex 2-D Sum of Absolute Differences (SAD) array to perform full search block matching is selected in order to support different search window size. The implemented scalable SAD array can provide different resolutions and frame rates for real time applications with multiple reconfigurable regions.

A speed FPGA hardware accelerator based FSBMA-VBSME used in H.264/AVC

Image and video processing applications represent major challenge concerning real-time embedded systems. In video coding, adjacent frames are similar; this correlation can be exploited to reduce the amount of data to be transmitted, in this case reducing temporal redundancies. Actually, H.264/AVC is the most popular standard; the high performance that offers magnifies the difficulty of a real-time implementation. This complexity is mainly related to the operation of the motion estimation and requires high computational power. This paper presents an efficient hardware implementation of integer motion estimation for H.264/AVC encoder. The considered methodology is based on full search block matching algorithm for its regular algorithm implementation. The proposed architecture enables variable block size motion estimation and computes 41 motion vectors values (MVs) resulted from each 16 × 16 bloc and its derived sub-blocks. The proposed architecture calculates the best MV using a parallel process composed of three processor modules and a set of comparators three values. Implementation results based on field-programmable gate arrays devices uses Xilinx Virtex7 XC7VX550T show performance characteristics like low latency reduced up to 80 %, high processing speed reaching 443 MHz of frequency. The processing capacity is up to 1920 × 1088 HD video streams with a search range of 48 × 48.

Conservative Approximation–Based Full-Search Block Matching Algorithm Architecture for QCIF Digital Video Employing Systolic Array Architecture

This paper presents a power-efficient hardware realization for a motion estimation technique that is based on the full-search block matching algorithm (FSBMA). The considered input is the quarter common intermediate format of digital video. The mean of absolute difference (MAD) is the distortion criteria employed for the block matching process. The conventional architecture considered for the hardware realization of FSBMA is that of the shift register-based 2-D systolic array. For this architecture, a conservative approximation technique is adapted to eliminate unnecessary MAD computations involved in the block matching process. Upon introducing the technique to the conventional architecture, the power and complexity of its implantation is reduced, while the accuracy of the motion vector extracted from the block matching process is preserved. The proposed architecture is verified for its functional specifications. A performance evaluation of the proposed architecture is carried out using parameters such as power, area, operating frequency, and efficiency.

English

Movement of hands or camera while capturing video leads to unstable video. To stabilize those unstable videos many approaches are proposed. Out of those, Digital Video Stabilization consists of Motion Estimation, Padding & Histogram Equalisation and Motion Compensation. In the block based method the frame is divided into 16*16 square block called Macroblock. Motion Estimation is the process of finding particular macroblock of previous frame into current frame. For this block matching criterion are used. This paper uses Sum of Absolute Difference (SAD). Block Matching Algorithms suggests where to apply this SAD in the macroblock. This paper uses Full Search or Exhaustive Block matching Algorithm (EBMA). Using this block matching algorithm, motion vectors are calculated. Padding is the process of keeping these motion vectors within certain range. Histogram equalisation of motion vectors try to uniform these motion vectors.In motion compensation macroblocks are adjusted according to motion vectors to obtain stabilized frame.

A Generalized Frame-Level FSBM FLSA Architecture

Block-based motion estimation plays important roles in video applications such as video compression to detect movements as well as remove temporal redundancies between successive frames. Full-search block-matching (FSBM) is the preferred algorithm for accurate motion estimation. Frame-level pipelined systolic array (FLSA) FSBM architectures have advantages over block-level pipelined architectures in their simpler control and reduced number of memory accesses. In this paper, a frame-level pipelined FSBM motion estimation architecture using array processor for any square, N×N, block size is presented in full detail.

A Systolic Array for High-Speed Computing of Full Search Block Matching Algorithm

This paper proposes a high speed systolic array architecture for full search block matching algorithm (FBMA). The pixels of the search area for a reference block are input only one time to find the matched candidate block and reused to compute the sum of absolute difference (SAD) for the adjacent candidate blocks. Each row of designed 2-dimensional systolic array compares the reference block with the adjacent blocks of the same row in search area. The lower rows of the designed array get the pixels from the upper row and compute the SAD with reusing the overlapped pixels of the candidate blocks within same column of the search area. This designed array has no data broadcasting and global paths. The comparison with existing architectures shows that this array is superior in terms of throughput through it requires a little more hardware.

Expert system based parallel multi-1D block matching algorithm with implementation for motion estimation

In this paper, we propose an expert-system based parallel multi-1-dimensional block matching algorithm (ESPM-1D-BMA) for motion estimation (ME). Instead of the conventional 2D block matching, we employ the parallel multi-1D blocks matching to improve the computing speed. To improve the ME accuracy, we design a knowledge base and inference engine to determine the true motion vector (MV) from the results of parallel multi-1D blocks matching. To speed up the computing speed further, we present a hardware architecture for implementing the ESPM-1D-BMA. We have demonstrated that the MV estimation accuracy achieved by the proposed ESPM-1D-BMA is much better than the comparing fast block matching algorithms and is close to the 2 dimensional full search block matching algorithm (2D-FSBMA). We also demonstrate that the computing speed of the proposed ESPM-1D-BMA is about two times as fast as the mixed-signal 2D-FSBMA (MS-2D-FSBMA).

A Low Cost Architecture for Variable Block Size Motion Estimation

Variable block size motion estimation is adopted in MPEG-4 AVC/H.264. This paper presents a new VLSI and FPGA architecture using full search block matching algorithm and online arithmetic. Several ways for data refreshing are described. There is not any increment in the number of clock cycles to process all sub-block formats. Only 54K gates are used, allowing to implement this architecture in devices with low hardware requirements. Moreover, low power consumption is obtained. A qualitative analysis of other designs is reported. Early termination of SAD calculation is analysed. Real-time video processing can be achieved for HDTV using early termination or increasing the parallelism.

Activity-Based Motion Estimation Scheme for H.264 Scalable Video Coding

This paper proposes a motion estimation scheme to reduce the computational complexity of multilayer motion estimation for scalable video coding. Based on the result of the motion estimation of the lower resolution layer referred to as base layer, we developed a new approach for exploring the search range of the enhancement layer with high coding efficiency. This approach is based on the activity defined as the absolute difference between the motion vector predictor and the final motion vector. Based on the correlation of the activities between neighboring layers, an inter-layer activity model was developed using a curve-fitted linear equation to exploit the activity in the base layer for deciding the search center and the search range of the enhancement layer. Each activity pair in the neighboring layers is used to associate the relevant macroblock to one of two groups; boundary region and interior region. The base-layer motion vector predictor is basically selected over all the activity regions; for each activity region, the proposed motion estimation algorithm decides whether to include the median motion vector predictor or not. Minimal sufficient search range is also decided from the inter-layer activity prediction factor that is adjusted to the given sequence. The proposed scheme reduced the execution time of motion estimation by 99.26% at the cost of 1.56% bit-rate increase and 0.048 dB peak signal-to-noise ratio (PSNR) decrease on average compared with the conventional full-search algorithm. The fast full-search block matching algorithm can also be incorporated to obtain the extra CPU time reduction in the motion estimation process. By adopting the fast full-search block matching algorithm (FFSBMA) in JSVM reference software, the CPU time was reduced by up to 91.84% and the memory bandwidth was reduced by 90% at the sacrifice of 1.27% bit-rate increase and 0.041 dB PSNR decrease on average compared with the FFSBMA only.

An FFT-Based Full-Search Block Matching Algorithm with Sum of Squared Differences Criterion

An FFT-based full-search block matching algorithm (BMA) is described that uses the sum of squared differences (SSD) criterion. The proposed method does not have to extend a real signal into complex one. This reduces the computational load of FFT approaches. In addition, if two macroblocks share the same search window, they can be matched at the same time. In a simulation of motion estimation, the proposed method achieved the same performance as a direct SSD full search and its processing speed is faster than other FFT-based BMAs.

Adaptive Motion Estimator Based on Variable Block Size Scheme

This paper presents an adaptive motion estimator that can be dynamically reconfigured by the best algorithm depending on the variation of the video nature during the lifetime of an application under running. The 4 Step Search (4SS) and the Gradient Search (GS) algorithms are integrated in the estimator in order to be used in the case of rapid and slow video sequences respectively. The Full Search Block Matching (FSBM) algorithm has been also integrated in order to be used in the case of the video sequences which are not real time oriented. In order to efficiently reduce the computational cost while achieving better visual quality with low cost power, the proposed motion estimator is based on a Variable Block Size (VBS) scheme that uses only the 16x16, 16x8, 8x16 and 8x8 modes. Experimental results show that the adaptive motion estimator allows better results in term of Peak Signal to Noise Ratio (PSNR), computational cost, FPGA occupied area, and dissipated power relatively to the most popular variable block size schemes presented in the literature. Keywords—H264, Configurable Motion Estimator, Variable Block Size, PSNR, Dissipated power.

Fast block matching using prediction and rejection criteria

In this paper, we present a fast block matching algorithm by making use of the correlation between layers of the sum pyramid for a block. To speed our method, an algorithm is also developed to predict the initial motion vector for a template block. Using the elimination criteria and predicted motion vector, our method can further reduce the computational complexity significantly. Compared with the full search block matching algorithm, our approach can reduce the computing time by a factor of 9.9–28.2 with the peak signal-to-noise ratio (PSNR) degradation of 0.00–0.03 dB. Compared to WinUpMI, which is the fastest block matching algorithm preserving global optimality as far as we know, our method can reduce the computing time by 4.9–52.5% with the PSNR degradation of 0.00–0.03 dB. Our method can reduce the computing time of predictive search area approach for fast block motion estimation (PSAFBME) by 50–96% with about the same PSNR.

Content-Aware Prediction Algorithm With Inter-View Mode Decision for Multiview Video Coding

3-D video will become one of the most significant video technologies in the next-generation television. Due to the ultra high data bandwidth requirement for 3-D video, effective compression technology becomes an essential part in the infrastructure. Thus multiview video coding (MVC) plays a critical role. However, MVC systems require much more memory bandwidth and computational complexity relative to mono-view video coding systems. Therefore, an efficient prediction scheme is necessary for encoding. In this paper, a new fast prediction algorithm, content-aware prediction algorithm (CAPA) with inter-view mode decision, is proposed. By utilizing disparity estimation (DE) to find corresponding blocks between different views, the coding information, such as rate-distortion cost, coding modes, and motion vectors, can be effectively shared and reused from the coded view channel. Therefore, the computation for motion estimation (ME) in most view channels can be greatly reduced. Experimental results show that compared with the full search block matching algorithm (FSBMA) applied to both ME and DE, the proposed algorithm saves 98.4-99.1% computational complexity of ME in most view channels with negligible quality loss of only 0.03-0.06 dB in PSNR.

Efficient Hierarchical Motion Estimation Algorithm and Its VLSI Architecture

This paper addresses the development and hardware implementation of an efficient hierarchical motion estimation algorithm, HMEA, using multiresolution frames to reduce the computational complexity. Excellent estimation performance is ensured using an averaging filter to downsample the original image. At the smallest resolution, the least two motion vector candidates are selected using a full-search block matching algorithm. At the middle level, these two candidate motion vectors are employed as the center points for small range local searches. Then, at the original resolution, the final motion vector is obtained by performing a local search around the single candidate from the middle level. HMEA exhibits regular data flow and is suitable for hardware implementation. An efficient VLSI architecture that includes an averaging filter to downsample the image and two 2-D semisystolic processing element arrays to determine the sum of absolute difference in pipeline is also presented. Simulation results indicate that HMEA is more area-efficient and faster than many full-search and multiresolution architectures while maintaining high video quality. This architecture with 59K gates and 1393 bytes of RAM is implemented for a search range of [ -16.0, +15.5].

A high-performance reconfigurable VLSI architecture for vbsme in H.264

VBSME (variable block size motion estimation) is adopted in the MPEG-4 AVC/H.264 standard. In order to increase the hardware utilization for VBSME with FSBMA (full search block matching algorithm), this paper proposed a new high-performance reconfigurable VLSI architecture to support meander-like scan format for a high data reuse of search area. The architecture can support the three data flows of the scan format through a reconfigurable computing array and a memory of the search area. The computing array can achieve 100% processing element (PE) utilization and can reuse the smaller blocks' SADs to calculate 41 motion vectors (MVs) of a 16X16 block in parallel. The design is implemented with TSMC 0.18 mum CMOS technology. Under a clock frequency of 180 MHz, the architecture allows the real-time processing of 1280 x 720 at 45 fps in a search range [-16, +16].

Low-power systolic array processor architecture for FSBM video motion estimation

A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

A Fast Multi-Resolution Block Matching Algorithm for Multiple-Frame Motion Estimation

In this paper, we propose a fast multi-resolution block matching algorithm with three resolution levels (upper, middle, and lower levels) for multiple-frame motion estimation (MFME). The main concept of the algorithm is to perform a fast search while maintaining a PSNR performance similar to a full search block matching algorithm (FSBMA). The algorithm combines motion vector prediction using the spatial correlation of motion vectors and a multiple candidate search based on a multi-resolution search. To further reduce the computational complexity, we propose two temporal reduction schemes. To reduce the number of previous reference frames to be processed, the first scheme is applied to the upper level by using the information obtained from the search results of the spatio-temporally adjacent macroblocks (MBs) and the result from the current MB in the middle level of the first reference frame. The other scheme is applied to the lower level by using statistical information. Experimental results show that the proposed algorithm guarantees an average PSNR loss of less than 0.23 dB with dramatically reduced computational complexity as compared to the FSBMA. In particular, for sequences with fast motion or frame skipping, the proposed method provides a more prominent PSNR performance than those of existing fast schemes with a comparable computational complexity.

De-interlacing algorithms based on motion compensation

Motion estimation (ME) and motion compensation (MC) based deinterlacing has been become the mainstream technology of industry. The existing ME/MC algorithms are mostly based on block matching (BM) strategy, in which various BM algorithms are proposed with different tradeoff between the matching accuracy and the CPU time. Aiming at the dilemma between the performance and the efficiency of the available deinterlacing algorithms, two adaptive ME/MC algorithms are presented in this paper. Compared with the full search BM algorithm, the proposed algorithms greatly reduce the computational amount with keeping the performance approximately. However, the inherent drawbacks of the BM limit the farther improvement of the deinterlacing performance. For this purpose, a new deinterlacing algorithm based on motion object is developed, in which it is natural motion object rather than contrived block that is taken as the basic cell for ME/MC. In the new algorithm, a more reliable technique is adopted for accurate motion region detection, and immune clonal selection algorithm is employed to accelerate the matched object searching. Meanwhile, many advanced deinterlacing methods, such as motion compensation, median filtering, Weave and Bob, are integrated into the new algorithm, so it is more adaptive to the various video sequences. The experimental results with several available test databases illustrate that the new algorithm based on motion object is better than those based on motion block on the whole.