A Low Cost Architecture for Variable Block Size Motion Estimation

Abstract

Variable block size motion estimation is adopted in MPEG-4 AVC/H.264. This paper presents a new VLSI and FPGA architecture using full search block matching algorithm and online arithmetic. Several ways for data refreshing are described. There is not any increment in the number of clock cycles to process all sub-block formats. Only 54K gates are used, allowing to implement this architecture in devices with low hardware requirements. Moreover, low power consumption is obtained. A qualitative analysis of other designs is reported. Early termination of SAD calculation is analysed. Real-time video processing can be achieved for HDTV using early termination or increasing the parallelism.