Full Adder Subtractor Research Articles

Multi-Layer QCA Reversible Full Adder-Subtractor Using Reversible Gates for Reliable Information Transfer and Minimal Power Dissipation on Universal Quantum Computer

The effects of quantum mechanics dominate nanoscale devices, where Moore’s law no longer holds true. Additionally, with the recent rapid development of quantum computers, the development of reversible gates to overcome the problems of energy and information loss and the nano-level quantum-dot cellular automata (QCA) technology to efficiently implement them are in the spotlight. In this study, a full adder-subtractor, a core operation of the arithmetic and logic unit (ALU), the most important hardware device in computer operations, is implemented as a circuit capable of reversible operation using QCA-based reversible gates. The proposed circuit consists of one reversible QCA gate and two Feynman gates and is designed as a multi-layer structure for efficient use of area and minimization of delay. The proposed circuit is tested on QCADesigner 2.0.3 and QCADesigner-E 2.2 and shows the best performance and lowest energy dissipation. In particular, it shows tremendous improvement rates of 180% and 562% in two representative standard design cost indicators compared to the best existing studies, and also shows the highest circuit average output polarization.

A novel efficient coplanar QCA full adder and full subtractor design

ABSTRACT Quantum-dot Cellular Automata (QCA) nanotechnology is an alternative technology with high speed, high density and low power for designing nanoscale circuits. A novel design of Full Adder-Subtractor based on full subtractor using single layer is proposed. The proposed architecture has a major advantage in terms of complexity, area, latency, and power consumption as compared to previous designs. The proposed QCA full subtractor showed higher performance concerning area with a reduction of 66%, and complexity with a reduction of 51% over best existing circuit designs. However, the proposed design of full Adder-Subtractor achieved a reduction of 74% in area, with 70% improvement in complexity, 33% reduction in latency by using two clock phases, and 95% improvement in cost needed over the best reported circuits using single-layer design. Total cell area and cost for the Full Adder-Subtractor were 0.01 μm2 and 0.07, respectively. Results showed that power consumption for the novel design was minimal. Therefore, the suggested Full Adder-Subtractor provides 86% less total energy consumption for 0.5Ek tunnelling energy level. These designs were tested and simulated using the freely known QCA Designer tool version 2.0.3. The energy dissipation result was realised by using the QCAPro energy estimation tool.

Reliable Domain‐Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors

Domain-Specific In-Memory Logic Gates As the total amount of data in computation rapidly increases, in-memory logic gates gain great attraction to address the von-Neumann bottleneck problem. In article number 2100267, Cheol Seong Hwang and co-workers present a new type of in-memory logic gates with a low voltage-stress level to execute exclusive-OR logic operations. The proposed logic gates have high compatibility with other logic gates in a crossbar array, which is utilized to implement a full adder-subtractor and multiplier. [Correction added on May 26, 2022, after first online publication: the inside back cover image and description were changed.]

Reliable Domain‐Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors

The development of memristor‐based stateful logic circuits can minimize data movement during the computing process to achieve in‐memory computing, mitigating the von Neumann bottleneck in the current computing architecture. Herein, a method to combine resistance–resistance (R–R) and voltage–resistance (V–R) logic gates to implement exclusive logic gates composed of APMR‐two‐2(XOR, IMP, RIMP) and APMR‐three‐4XOR, where APMR means antiparallel memristors with a series resistor, is suggested. The proposed gates can accelerate XOR logic operation in a single cycle and expand for the n‐bit input. The performance of the proposed logic gate is then demonstrated with a 1‐bit full adder–subtractor along with the comparison of an n‐bit ripple carry adder. It shows that the implementation for the n‐bit adder takes 4n+1 memristors within 2n+1 steps, which significantly improves the optimization in terms of space‐ and time‐related costs compared with other memristive logic gates. Subsequently, the improved adder circuit can be further utilized to implement an n‐bit multiplier. In addition, the evaluation of the device stress on the various logic gates confirms that the proposed logic gates are reliable.

Design and Implementation of Novel Efficient Full Adder/Subtractor Circuits Based on Quantum-Dot Cellular Automata Technology

One of the emerging technologies at the nanoscale level is the Quantum-Dot Cellular Automata (QCA) technology, which is a potential alternative to conventional CMOS technology due to its high speed, low power consumption, low latency, and possible implementation at the atomic and molecular levels. Adders are one of the most basic digital computing circuits and one of the main building blocks of VLSI systems, such as various microprocessors and processors. Many research studies have been focusing on computable digital computing circuits. The design of a Full Adder/Subtractor (FA/S), a composite and computing circuit, performing both the addition and the subtraction processes, is of particular importance. This paper implements three new Full Adder/Subtractor circuits with the lowest number of cells, lowest area, lowest latency, and a coplanar (single-layer) circuit design, as was shown by comparing the results obtained with those of the best previous works on this topic.

Efficient design and implementation of a robust coplanar crossover and multilayer hybrid full adder–subtractor using QCA technology

Quantum dot cellular automaton (QCA) is a novel emerging nanometer-scale-based circuit design using nanocomputing technology, which overcomes the limitations of complementary MOS technology in the precondition of the circuit design area, power, and latency/delay. This paper presents an efficient design of crossover single-layer (coplanar) and multilayer novel hybrid full adder–subtractor circuits by implementing majority gate minimization functional J-map technique. The proposed circuits have been found more efficient in terms of minimum number of QCA cells, low latency, required area in µm2, and reduced quantum cost as compared to existing QCA adder–subtractor designs and also avoid the thermodynamics problems occurring due to long QCA wires with the applied synchronization clocking method. In this paper, we have introduced 14 nm × 14 nm and 16 nm × 16 nm cell size QCA circuits and compared with an existing and proposed novel 18 nm × 18 nm single-layer and multilayer designs. Both designs are implemented by the QCADesigner-E tool with bistable vector and coherent vector energy setup in the Euler method and the Runge–Kutta method.

Design and analysis of novel QCA full adder-subtractor

ABSTRACT Quantum-dot Cellular Automata is an evolving post-CMOS paradigm that can be used for designing nanoscale circuits. Digital circuits are implemented in QCA using majority logic. Adder and subtractor are used widely in almost every data processing system. For efficient hardware implementation, a single hardware can be used to perform both addition as well as subtraction. In this paper, a novel majority logic-based adder-subtractor architecture is proposed. The proposed architecture is implemented in QCA and validated using the coherence vector simulation engine in QCADesigner tool. The results show that the proposed design has fewer cell count, area and latency compared to the existing designs. During fabrication, QCA circuits can face manufacturing defects. A detailed fault analysis is made for the proposed design for different manufacturing defects. Parameters to calculate the fault tolerant ability of QCA circuits are introduced and calculated for the proposed design.

A compressed-sensing-based compressor for ECG.

Electrocardiogram (ECG) data compression has numerous applications. The time for generating compressed samples is a vital factor when we consider ambulatory devices, with the fact that data should be sent to the physician as soon as possible. In addition, there are some wearable ECG recorders that have limited power, and may only be capable of doing simple algorithms. With the aim of increasing the speed and simplicity of the compressors, we propose a system architecture that can generate compressed ECG samples, in a linear method and with CR 75%. We used sparsity of the ECG signal and proposed a system based on compressed sensing (CS) that can compress ECG samples, almost in real-time. We applied CS in a very small size in order to accelerate the compression phase and accordingly reducing the power consumption. Also, in the recovery phase, we used the recently developed Kronecker technique to improve the quality of the recovered signal. The system designed based on full-adder/subtractor (FAS) and shift registers, without using any external processor or any training algorithm.

Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology

This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic design. The ternary logic benefit of reduced circuit overhead is exploited by embedding multiple modules within a block. The existence of symmetric literals among various single shift and dual shift operators in addition and subtraction operations results in the optimized realization of adder/subtractor modules. The proposed design is based on the notion of multiplexing either arithmetic, logical or miscellaneous operations, depending upon the status of input selection trits. The results obtained by the synopsis HSPICE simulator with the Stanford 32 nm CNFET technology illustrate that the proposed processing modules outperform their counterparts in terms of power consumption, energy consumption and device count. The proposed methodology leads to saving in power consumption and energy consumption (PDP) of 62% and 58%, respectively, on the benchmark circuit of the ALU [full adder/subtractor (FAS)]. Furthermore, for the 2-trit multiplier design, the enhanced performance at the architecture and circuit level is achieved through the optimized designs of various adder and multiplier circuits.

Design of an ultra-efficient reversible full adder-subtractor in quantum-dot cellular automata

By the progressive scaling of the feature size and power consumption in VLSI chips the part of energy dissipated due to information loss in irreversible computations will become a serious limitation in the near future. Quantum-dot cellular automata (QCA) is an emerging nanotechnology with extremely low energy dissipation which facilitates new computation paradigms such as reversible computing. In this paper a novel reversible full adder-subtractor circuit based on QCA is proposed. Our proposed design is implemented using only one layer and does not require any rotated cells which significantly improves the manufacturability of the design. In addition, it improves the cell count, area and total energy dissipation by almost 45% and 50% and 48%, respectively, as compared to the existing QCA-based single-layer and multilayer reversible full adders.

Design of CNTFET-based 2-bit ternary ALU for nanoelectronics

This article presents a hardware-efficient design of 2-bit ternary arithmetic logic unit (ALU) using carbon nanotube field-effect transistors (CNTFETs) for nanoelectronics. The proposed structure introduces a ternary adder–subtractor functional module to optimise ALU architecture. The full adder–subtractor (FAS) cell uses nearly 72% less transistors than conventional architecture, which contains separate ternary cells for addition as well as subtraction. The presented ALU also minimises ternary function expressions with utilisation of binary gates for optimisation at the circuit level, thus attaining a simple design. Hspice simulations results demonstrate that the ALU ternary circuits achieve great improvement in terms of power delay product with respect to their CMOS counterpart at 32 nm.

Controlled full adder–subtractor by vibrational computing

The implementation of a quantum-controlled full adder-subtractor of two binary digits and of a "carry in" or a "borrow in" is simulated by encoding four qubits in the vibrational eigenstates of a tetra-atomic molecule (trans-HONO). The laser field of the gate is computed using optimal control theory by treating dynamics in full dimensionality. A controlled qubit enforces the addition or the subtraction. The global unitary transformation that connects the inputs to the outputs is driven by a single laser pulse. This decreases the duration of the operation and allows for a better use of the optical resources and for an improvement of the fidelity (>97%). Initialization and reading out are discussed. The timescale of the sequence initialization, gate and read out is<100 ps.