Full Adder Design Research Articles

Design of Baugh–Wooley multiplier in quantum-dot cellular automata using a novel 1-bit full adder with power dissipation analysis

Complementary metal oxide semiconductor (CMOS) is a low-power technology typically used in the efficient implementation of digital circuits. However, at nanodimensions, CMOS has problems due to its short channel effects and subthreshold leakage currents. These drawbacks can be overcome with quantum-dot cellular automata (QCA) which is one of the fastest nanotechnologies operated at THz rate. Thus, all digital circuits can now be implemented by QCA at the required nanoscale. This paper proposes a novel, energy-efficient and area-optimized 1-bit full adder design using QCA which provides efficient clocking, reduced cell count and reduced energy dissipation. The proposed design utilizes only 26 quantum cells in 0.02 µm2 area and has a reduction of 8% in number of cells, 75% in delay and 4% in energy dissipation at 1 K compared to the existing works. This innovative full adder design is used to implement a 4 × 4 Baugh–Wooley multiplier. The simulation results of the multiplier observed on QCADesigner 2.0.3 tool validate that the Baugh–Wooley multiplier designed with the novel 1-bit full adder yields better performance in terms of 9% reduction in area, 17.4% reduction in quantum cells used and reduced power dissipation of 2.44nW.

Quantum legitimacy of reversible gate and a new design of multiplier based on R gate**Project supported by the National Natural Science Foundation of China (Grant No. 11861031).

Quantum full adders play a key role in the design of quantum computers. The efficiency of a quantum adder directly determines the speed of the quantum computer, and its complexity is closely related to the difficulty and the cost of building a quantum computer. The existed full adder based on R gate is a great design but it is not suitable to construct a quantum multiplier. We show the quantum legitimacy of some common reversible gates, then use R gate to propose a new design of a quantum full adder. We utilize the new designed quantum full adder to optimize the quantum multiplier which is based on R gate. It is shown that the new designed one can be optimized by a local optimization rule so that it will have lower quantum cost than before.

Inverted Gate Vedic Multiplier in 90nm CMOS Technology

This paper proposes the design and implementation of an enhanced binary multiplication technique. Vedic Mathematics is a system of mathematics that was discovered by Indian mathematician Jagadguru Shri Bharathi Krishna Tirthalji in the period between 1911 and 1918. The main objective of this paper is to design an improved binary multiplier which is faster and low-powered. The performance of our proposed full adder design is proven to be more effective in comparison with the standard full adder cell both designed in 90nm. The proposed modified 2-Bit and 4-Bit Vedic multipliers also beat the existing Vedic multiplier based in Urdhva Tiryagbhyam sutra in terms of operating frequency, energy and area. ThedesignsareimplementedoncadenceVirtuoso90nmCMOStechnology operating at 2V supply. Comparedtotheexisting standard fulladderdesigns in 90nm, the proposed implementation has shown that it offers significant improvements in terms of power and speed consuming 60% less power and is able to operate 20% faster. The proposed 2-Bit multiplier operated at 2V is proven to be more effective. The design was further extended to realise a 4-Bit multiplier. The power consumed by the standard 4- Bit multiplier designed using standard 90nm cells was 361.2µW and the power consumed by the proposed 4-Bit multiplier design was found to be 290.2µW, which reflectsa 20% decrease in the power usage.

Cost-efficient full adder designs in quantum-dot cellular automata

Quantum-dot cellular automata has all the vital characteristics needed by a post-complementary metal oxide semiconductor technology. Adder is a key constituent in any digital circuit system. Several full adder designs are proposed in quantum-dot cellular automata. The different existing techniques used in quantum-dot cellular automata adders are analysed in this work and two cost-efficient full adder designs are proposed using different crossover techniques. The proposed designs have minimum cells and are faster compared to the adders in the literature. They also have the ability to be extended to realise adders of any word length. Missing cell defect analysis is done for the proposed designs and compared with the other adder designs. The designs are validated using QCADesigner.

Cost-efficient full adder designs in quantum-dot cellular automata

Quantum-dot cellular automata has all the vital characteristics needed by a post-complementary metal oxide semiconductor technology. Adder is a key constituent in any digital circuit system. Several full adder designs are proposed in quantum-dot cellular automata. The different existing techniques used in quantum-dot cellular automata adders are analysed in this work and two cost-efficient full adder designs are proposed using different crossover techniques. The proposed designs have minimum cells and are faster compared to the adders in the literature. They also have the ability to be extended to realise adders of any word length. Missing cell defect analysis is done for the proposed designs and compared with the other adder designs. The designs are validated using QCADesigner.

Synthesis and simulation study of non-restoring cell architecture layout in perpendicular nano-magnetic logic

Nano-magnetic logic is one of the most competitive technologies of conventional metal oxide semiconductor-based designs. There is no current flow, and information is transferred via the magnetic force between the magnets. Because of this phenomenon, it has low power dissipation and operating in the megahertz frequency range. In this paper, perpendicular nano-magnetic logic (pNML) technology is used for designing a non-restoring divider circuit. First, a new three-dimensional layout of the Exclusive-OR (XOR) gate is proposed. This layout is extended to a new 1-bit full adder circuit, 1-bit non-restoring cell and a 4-bit non-restoring divider. According to our insight, the proposed non-restoring divider circuit in the pNML layout and use of the multilayer is the first time in the literature. The areas of the proposed layouts are 9.72 µm2, 45.9 µm2, 61.2 µm2 and 3955.95 µm2 for the XOR gate, full adder, non-restoring cell and non-restoring divider designs, respectively. The proposed FA consumes 44.25% less latency and 60% fewer layers than the existing state-of-the-art work. All the proposed layouts are implemented using the MagCAD tool.

A High-Speed, Low-Power, and Area-Efficient FGMOS-Based Full Adder

Full adder is one of the fundamental components of very large-scale digital integrated systems, capable of performing all arithmetic operations. High-performance full adders are always desired to meet the challenges of ever growing integration technology. This paper presents the design of a full adder using floating-gate MOSFET (FGMOS). FGMOS is a multi-input transistor where the input signals are capacitively coupled to the floating gate, and the effective threshold voltage can be lowered from its conventional value. The voltage on the floating-gate is the weighted sum of the input voltages applied at the multiple input gates. This feature of FGMOS has been exploited in this paper for designing a high-speed, low-power, and area-efficient full adder. The performance of FGMOS-based full adder has been compared with other full adder designs available in the literature. It has been observed that FGMOS-based full adder exhibits better performance in terms of propagation delay, power consumption, and power delay product besides consuming less chip area due to the reduced transistor count compared with existing full adder designs. The workability of these circuits has been verified by PSpice simulations carried out using level 7 parameters in 0.13 µm CMOS technology with supply voltage of 1 V. The simulation results have been found to be in good conformity with the mathematical formulations.

Performance Evaluation of an Efficient Five-Input Majority Gate Design in QCA Nanotechnology

Quantum-dot cellular automata (QCA) is the imminent transistor less technology, considered at nano-level with high speed of operation and lower power dissipation features. The present paper proposes a novel and an efficient five-input coplanar majority gate (PMG) with improved structural and energy efficiency. The proposed gate consumes an occupational area of 0.01 µm2 with 17 QCA cells which is 50% less in comparison with the best designs reported in the literature. The proposed structure is also more energy efficient because it dissipates 21.1% less energy than the best reported designs. The correctness of a proposed majority gate is verified by designing a single-bit full adder. The new one-bit full-adder design is structural efficient and robust in terms of gate count and clock delay. It consumes occupational area of 0.05 µm2 with 58 QCA cells showing 16.6% improvement in structural efficiency as compared to the best design reported. It is having a gate count of 4 with the delay of 1 clock cycle. Here, the QCADesigner and QCAPro tools are utilized for the simulation and energy dissipation analysis of proposed majority gate and full-adder design.

Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor

The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

Design of Advanced 64-bit Full Adder in 45-nm Technology

This paper presents the design of a 64-bit parallel adder with 45_nm technology using cadence virtuoso tool. The proposed method uses the designed 1-bti full adder and the performance is compared with the other cadence virtuoso technologies i.e. 180-nm and 90-nm. Performance parameters such as average power, delay, PDP and transistor count are calculated and compared with the 180-nm and 90-nm technologies. The proposed method based on 45-nm technology at 1V supply exhibits the average power consumption as low as 0.114μW and less delay of 3.503ps which is obtained from the absorption of extremely feeble CMOS inverters together with physically powerful transmission gates. The full adder is designed by using XNOR module and transmission gates. The XNOR module is used to produce the output SUM and the transmission gates are used to produce the output Carryout.

Novel efficient full adder and full subtractor designs in quantum cellular automata

In this study, two new full adder/full subtractor designs based on quantum-dot cellular automata technology have been proposed. By means of the presented equation for SUM and SUBTRACT operations, the new high-speed, low power, and cost efficient designs have been achieved. Even if the three-level design has a lower cell count, occupies less area, and operates at a higher speed, the one-layer design is far more feasible. Analysis of the temperature and energy consumption of the proposed design indicates that the proposed approaches are superior to those of previous works.

Performance evaluation of an efficient five input majority gate design in QCA nanotechnology

Quantum-dot-cellular-automata (QCA) is the imminent transistor less technology, considered at nano level with high speed of operation and lower power dissipation features. The present paper proposes a novel and an efficient 5-input coplanar majority gate (PMG) with improved structural and energy efficiency. The proposed gate consumes an occupational area of 0.01μm2 with 17 QCA cells which is 50% less in comparison to the best designs reported in literature. The proposed structure is also more energy efficient because it dissipates 21.1% less energy than the best reported designs. The correctness of a proposed majority gate is verified by designing a single bit full adder. The new 1-bit full adder design is structural efficient and robust in terms of gate count and clock delay. It consumes occupational area of 0.05μm2 with 58 QCA cells showing 16.6% improvement in structural efficiency as compared to the best design reported in. It is having a gate count of 4 with the delay of 1 clock cycle. Here, the QCADesigner and QCAPro tools are utilized for the simulation and energy dissipation analysis of proposed majority gate and full adder design.

Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation

A novel design of a hybrid Full Adder (FA) using Pass Transistors (PTs), Transmission Gates (TGs) and Conventional Complementary Metal Oxide Semiconductor (CCMOS) logic is presented. Performance analysis of the circuit has been conducted using Cadence toolset. For comparative analysis, the performance parameters have been compared with twenty existing FA circuits. The proposed FA has also been extended up to a word length of 64 bits in order to test its scalability. Only the proposed FA and five of the existing designs have the ability to operate without utilizing buffer in intermediate stages while extended to 64 bits. According to simulation results, the proposed design demonstrates notable performance in power consumption and delay which accounted for low power delay product. Based on the simulation results, it can be stated that the proposed hybrid FA circuit is an attractive alternative in the data path design of modern high-speed Central Processing Units.

New 3-D CMOS Fabric With Stacked Horizontal Nanowires

As 2-D CMOS reaches its fundamental scaling limits due to device, manufacturing, and interconnect bottleneck related constraints at the nanoscale, migration to 3-D provides a possible alternative to continue technology scaling in future. Toward that goal, several 3-D integration approaches with multi-die, multichip, and sequential layers stacking are pursued. However, these approaches only show incremental density benefits and exhibit new challenges, such as lack of thermal management, increasing cost, and reliability issues. In contrast to these, we proposed a radically different fabric concept, called stacked horizontal nanowire-based 3-D CMOS (SN3D), on a single die that can offer a paradigm shift in technology scaling as well as design. Using prefabricated and doped stacked horizontal nanowires as fundamental building blocks, the fabric is assembled using architected connectivity and insulation features. Innovations in circuit style for mapping to SN3D’s physical framework, and bottom-up material filling-based manufacturing techniques are also central to our approach. In this paper, we detail, fabric’s core constructs, logic circuits implementation in SN3D fabric, benchmarking methodology and results, and finally the manufacturing aspects. Our circuit analysis reveals tremendous benefits; for a 4-bit full adder design, SN3D shows $11\times $ , 19%, 18%, and 6.7 $\times $ , 8.69%, 9% benefits over state-of-art 2-D CMOS and transistor-level monolithic 3-D in terms of density, power, and performance, respectively. In addition, our step-by-step TCAD emulation of manufacturing flow establishes feasibility. If realized, the SN3D fabric can be transformative for the semiconductor industry.

FPGA Implementation of Fault Tolerant Full Adder Design for High Speed VLSI Architectures

The essential goal is to distinguish and diminish the deficiencies in full Adder configuration making use of Self checking and Self Repairing Adder Block. The tempo of chip disappointment is straightforwardly relative to chip thickness. A framework should be flaw tolerant to diminish the frustration rate. The nearness of different troubles can demolish the usefulness of complete snake. This paper displays a region proficient flaw tolerant complete snake shape that may repair issues without interfering with the everyday assignment of a framework. The combo and duplicate is finished through way of making use of Xilinx ISE 14.7 and actualized on FPGA Spartan three..

Design and Simulation of Low Power 10T Full Adder using Cadence 16nM Technology

Design and Simulation of Low Power 10T Full Adder using Cadence 16nM Technology

Deeper Insight of Various Full-Adder Designs with Various Techniques and Technology

In this paper various type of full adder circuits with high speed operation have been analyzed. Power Consumption, Speed and Area are important factors of the design aspect of full adder circuit. Many researchers have worked on full adder designs using various technologies. Present paper deals with literature analysis based on full adder designs.

Two novel inverter-based ternary full adder cells using CNFETs for energy-efficient applications

ABSTRACTCarbon nanotube field effect transistors (CNFETs) exhibit great promise and extensions to silicon MOSFET due to their excellent electronic properties and extremely small size. Implementable CNFET circuits have operational characteristics to approach the advantage of using multiple-valued logic (MVL) in voltage mode. In MVL implementation computation for the system will be faster than the binary system with improved density of digital circuits. This paper presents two novel 1-bit inverter-based ternary full adder cells which second design cell uses only 37 CNFET transistors in its structure. These designs have been proposed using a new definition of Majority-not based full adder, and are compared to the other adders based on power consumption, speed and power-delay product (PDP). Proposed designs are evaluated using simulation run on HSPICE with 32 nm CNFET standard technology under various operational conditions, including different supply voltages, output load variation and different operating temperatures. According to simulation results, all proposed ternary full adder designs in compare to the state of the art circuits in literature have been demonstrated up to 81% and 80%, respectively, improvement in power consumption and PDP.

Novel Design of Full Adders using QCA Approach

Novel Design of Full Adders using QCA Approach