Full Adder Design Research Articles

Design and Implementation of 1-bit Full Subtractor Using FinFET

Abstract: A full subtractor is a digital combinational circuit that performs subtraction involving three bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout (borrow out). Unlike a half adder, which adds only two binary digits and produces a sum and carry, a full adder considers an additional carry input from a previous less significant bit addition. The full adder's design includes three inputs: A, B, and Cin (carry-in), and two outputs: Sum (sum) and Cout (carry-out). The sum output Sum is derived by XOR-ing the three inputs, while the carry-out Cout is obtained by considering the majority function of the inputs. This means Cout is set when any two or more of the three inputs are high (logical 1). Full subtractors are fundamental components in the construction of arithmetic logic units (ALUs), binary adders, and other computational circuits in digital systems, enabling the handling of multi-bit binary addition by cascading multiple full adders.

Comparative Analysis of High Speed and Area Efficient Full-Adder using CMOS and MGDI Techniques

Extremely quick processing is crucial for very large-scale integrated (VLSI) circuits in the arithmetic logic unit. Complementary metal oxide semiconductor (CMOS) and modified gate diffusion input (MGDI) are beneficial technologies for designing high-speed circuits with better reliability and performance with regard to area and power consumption. This research work provides a comparative performance analysis of a full adder that is implemented with CMOS and MGDI technology. This work aims to develop a CMOS-based full-adder and a MGDI-based full-adder circuit for area-efficient and high-speed applications. First, the analysis and implementation of the XOR and NAND logic gates are designed using CMOS technology and the MGDI technique to create a full-adder design. The comparative analysis of integrated circuits in CMOS and MGDI technologies is primarily determined by the number of transistors and delay time. The full-adder is designed and analyzed using 90 nm technology, with performance characteristics evaluated using Cadence Virtuoso Tools.

DAFA: Dynamic approximate full adders for high area and energy efficiency

As the number of transistors on a chip surface increases, power consumption becomes more and more a serious concern. A promising solution to bridge the gap between resource-constrained gadgets and computation-intensive applications could be the approximate computing paradigm. This paper presents four efficient approximate full adder cells based on dynamic logic and carbon nanotube field-effect transistors (CNFETs). To the best of our knowledge, dynamic logic has never been deployed in the design of approximate full adders before. Comprehensive simulations and analyses are conducted to study the efficacy of the new circuits. Simulation results indicate remarkable improvements compared to state-of-the-art circuits. For instance, at 0.9 V power supply, our final proposed design improves the power-delay-area product (PDAP) metric by at least 63% compared to its peers. Moreover, the applicability of the proposed adders in the image sharpening application is examined by measuring peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) using the MATLAB tool. The proposed designs have also a reasonable performance in this regard.

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

<p>The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.</p>

Design and Implementation of CMOS and Transmission Gate Based Full Adder Using 45nm Technology

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied, and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Transmission gate based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Transmission gate based Full adder circuits. The entire circuit is simulated in Cadence Tools at 45nm CMOS process.

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Pass Transistor Logic based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Pass Transistor Logic based Full adder circuits. The entire work is simulated in 180nm CMOS technology.

A novel lightweight CNN-based error-reduced carry prediction approximate full adder design for multimedia applications

A novel lightweight CNN-based error-reduced carry prediction approximate full adder design for multimedia applications

Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

High Performance and Scalable Hybrid Memristor-CMOS Based Full Adder

The field of digital computation has recently drawn attention to the memristor as a circuit element due to its nanoscale structure and integration capabilities with MOSFETs. As a result, there have been various attempts to use hybrid memristor-CMOS circuits to rebuild the fundamental digital building blocks. This paper presents a new hybrid memristor-CMOS-based full adder (HMC-FA) design. This design aims to minimize propagation delay, power dissipation, power delay product (PDP), and device count (memristor and transistor count). The proposed design is implemented in Cadence Virtuoso toolset utilizing CMOS gpdk 180nm process technology parameters. Comparative investigation demonstrates that the proposed HMC-FA improves PDP by 71.95%−99.83%. The proposed circuit is designed with 12 transistors and 6 memristors. The proposed design consumes 8.24µW of total power while the propagation delay is 112.71ps at 1.8V supply voltage. To verify the scalability of the HMC-FA cell, full adders up to 32-bit word length are designed, and performance parameters are evaluated at 1.8V, 100MHz supply voltage.

FPGA Implementation of High-Performance Truncated Rounding based Approximate Multiplier with High-Level Synchronous XOR-MUX Full Adder

In research and development, the most emerging field in digital signal processing and image processing is rounded-based approximated signed and unsigned multipliers. In the present research, we propose some cutting-edge, Preformation, and logic simplification technology connected to processing the Discrete cosine transform (DCT) and Discrete wavelet transform (DWT) images for sharpening. This technology will yield a truncated shifter incorporated with logical XOR-MUX Full adder techniques. A reliable and cost-effective approximate signed and unsigned multiplier was created for the rounding method. While this more advanced technology includes many approximate multipliers, it sacrifices the ability to find the closest integer of a rounded value when combining signed and unsigned capabilities, resulting in higher absolute errors than other approximate multipliers based on rounding. This proposed work will introduce a novel method of Truncated Shifter Rounding-based Approximate Multiplier integrated with a High-Level Synchronous XOR-MUX Full Adder design to minimize the number of logic gates and power consumption in the multiplier architecture. The Truncated RoBA (Rounding-based Approximate Multiplier) with XOR MUX Full Adder will reduce the logic size in the shifter and the arithmetic circuit. The work will modify this rounding-based approximate multiplier to minimize area, delay, and power consumption. This proposed architecture will be integrated with two fundamental changes: firstly, its Barrel shifter method will be replaced with a truncated shifter multiplier with XOR MUX Full Adder, and secondly, the parallel prefix Brent Kung adder will be replaced with a carrying-save adder with XOR MUX Full Adder. Finally, this architecture was designed using Verilog-HDL and synthesized using the Xilinx Vertex-5 FPGA family, targeting the device Xc7Vx485tFFg1157-1. It resulted in a reduction of area LUT (34%), power (1%), delay (32%), and error analysis (75%) when compared to the existing RoBA.

WITHDRAWN: Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed

In this paper, we propose a hybrid full-swing adder (HFSA) circuit that uses the hybrid full-swing logic (HFSL) technique, which consists of 20 transistors. This circuit relies heavily on a 12-transistor XOR-XNOR circuit to optimize the area and power. Our novel XOR-XNOR circuit plays a crucial role in achieving high-efficiency HFSA circuits. It integrates 2-to-1 multiplexers, pass transistor logic, and inverters to deliver glitch-free full-swing outputs. We compared the efficiency and practicality of our design with those of 10 alternatives by considering their performances and characteristics. Our novel XOR-XNOR circuit surpassed its counterparts with an exceptional chip area reduction of 14.14–28.01 %, an average power of 2.44 μW, and remarkably low delays of 25.88 and 24.87 ps. Notably, the proposed full adder achieved a chip area reduction of 11.30–49.69 %, 3.582 μW power, and a 72.66 ps delay. It emphasizes large-scale structures, such as 4-bit to 64-bit full adders, implemented using cascaded designs with a novel ripple carry adder. Using multipoint and Monte Carlo analysis in the ADEXL design suite to ensure the reliability of all circuits using the Cadence Virtuoso with the GPDK45 nm technology. The proposed method is an alternative to high-speed electronic systems with potential benefits.

Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination

Quantum dot cellular automata (QCA) stands as a highly promising nanotechnology, capable of outperforming conventional CMOS technology. Leveraging its advantages, this paper addresses the challenges in adder circuits related to size, delay, and cost by integrating QCA technology. A novel layout for a co-planar full adder in QCA is introduced, featuring a half-adder design with 23 cells in a single layer without any crossover, achieving a delay of 0.25 clock cycles. By utilizing inter-cellular effects inherent in QCA technology, the presented designs offer significant improvements in a variety of design metrics, and a cost efficiency of 64.3%, distinguishing them from traditional logic design approaches. Additionally, in order to ensure an efficient routing channel and a consistent structure of the adder design, a Universal, Scalable, and Efficient (USE) clocking scheme has also been employed. The adder design is further used to build 4-bit and 8-bit Ripple Carry Adders. An extensive study on energy dissipation using QCADesigner-E and QCAPro tools is conducted for three tunneling energies (0.5 Ek, 1 Ek, and 1.5 Ek). The full adder design showcases substantial improvement in energy to delay cost when compared to the closest reported design, achieving improvements of 91.66%, 89.03%, and 88% at 0.5 Ek, 1 Ek, and 1.5 Ek, respectively. The results highlight enhanced circuit efficiency and streamlined layouts, outperforming existing models and offering substantial benefits to high-performance and energy-efficient computing systems.

1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages

1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages

Design of ternary full-adder and full-subtractor using pseudo NCNTFETs

Now-a-days, the binary logic system has intensified by scaling the field effect transistor (FET). However, due to the effectiveness of scaling the FET, ternary logics became more popular. Out of numerous ternary logic devices, carbon nanotube (CNT) FET (CNTFET) is considered a good candidate over silicon FETs. Hence, in this study, ternary schematics are developed based on Pseudo N-type CNTFETs. The ternary basic designs such as standard ternary inverter (STI), AND and OR gates are presented. Then, using the proposed basic logic gates, the complex designs such as full adder and full subtractor are also proposed. The HSPICE simulator is utilized to design proposed circuits and analyze different performance parameters. The performance such as delay, power and power delay product (PDP) are analyzed for the proposed circuits. Moreover, the proposed schematics performances are also compared to complementary schematics. It investigated that Pseudo N-type CNTFET schematics improved the overall performance on an average up to 65.82% over the complementary ternary circuits.

An efficient memristive alternating crossbar array and the design of full adder

An efficient memristive alternating crossbar array and the design of full adder

Design and simulation of reversible one-bit full adders using QCA technology

Design and simulation of reversible one-bit full adders using QCA technology

Design of Low Power 64-Bit Hybrid Full Adder

Abstract: In the realm of Computer Science, integrated circuits (ICs) have propelled microprocessor and digital signal processor development, hinging on the 1-bit full adder's significance for mathematical tasks. To amplify overall efficiency, enhancing this adder is pivotal. As demand surges for power-efficient devices like smartphones and MP3 players, maintaining a balance between speed, size, and power usage becomes imperative. Engineers tackle this challenge while bridging battery technology gaps. We propose advanced 1-bit full adder designs, evaluated via Cadence Virtuoso. A hybrid version merges Pass-Transistor Logic (PTL), Transmission Gates (TGs), and static CMOS logic. An optimized alternative incorporates efficient 3T-XOR logic. The comparative study considers crucial metrics: the existing FA’s 8.83µW power vs. the proposed's 8.49µW; the proposed's shorter delay of 64.53ps vs. the existing FA’s 83.1ps (18 vs. 22 transistors). At 64 bits, the existing FA’s consumes 66.8µW with a 470.94ps delay (1408 transistors), while the proposed maintains 35.05µW, 64.53ps, and fewer transistors (1152). In summary, the proposed adder excels in efficiency, delay, and transistor use for energy-efficient arithmetic operations.

A low-power high speed full adder cell using carbon nanotube field effect transistors

The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1- bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model is simulated using 32 nm with CNTFET technology, a voltage supply of +0.9V. Performance comparisons between various proposed designs and existing 1-bit full adder design have been made in terms of the delay, power, and power delay product (PDP). The proposed CNFET logic also design for n-bit carry look adder (CLA) and compare it to other CLAs to evaluate performance and reliability. The simulation results shows that the proposed adder consume less power than existing adders.

Ternary Full Adder Designs Employing Unary Operators and Ternary Multiplexers.

The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with 55 CNFETs, that use unary operator gates with two voltage supplies (Vdd and Vdd/2) to reduce the transistor count and energy consumption. In addition, this paper proposes two 4-trit Ripple Carry Adders (RCA) based on the two proposed TFA1 and TFA2; we use the HSPICE simulator and 32 nm CNFET to simulate the proposed circuits under different voltages, temperatures, and output loads. The simulation results show the improvements of the designs in a reduction of over 41% in energy consumption (PDP), and over 64% in Energy Delay Product (EDP) compared to the best recent works in the literature.