Low-noise Front-end Amplifier Research Articles

A compact sub-Hertz local field potential amplifier for implantable biomedical devices

Local field potentials (LFPs) are the ensemble of low frequency neural signals recorded invasively via microelectrodes implanted into brain tissues. The LFP signals acquired by micro-electrodes are very small in amplitude, typically in the range of 1 μV to 0.5 mV, depending on the distance from the electrode and on the size of a cell and contain the signal energy below 1 Hz. These weak signals are required to be amplified by an analog front-end amplifier. In this paper, the design methodology of a local field potential amplifier for an implantable neural recording system is presented. The LFP amplifier is implemented through a low power, low noise front-end instrumentation amplifier. In order to suppress large electrode-induced DC offset voltages, a modified pseudo-resistor is employed in the amplifier’s feedback. The enlarged resistance offered by the pseudo resistor realizes a high-pass cut-off frequency which is well suited for capturing the neural signals occurring in the sub-Hertz frequency range. As a case study, the instrumentation amplifier featuring modified pseudo resistor configured for LFP recording applications is fabricated in a standard 0.18μm CMOS process technology. The measurement results show the proposed LFP amplifier has a low-pass corner frequency of 300 Hz and achieves a high-pass corner frequency of 0.009 Hz with a maximum gain of 37 dB. The LFP circuit fully integrated on-chip occupies an active area of 0.056 mm2 and a power consumption of 1.8 μW from a 1.5-V supply.

A novel front-end amplifier for gain-less charge readout in high-pressure gas TPC

This paper presents a novel low-noise front-end amplifier manufactured in a standard 130 nm CMOS process. The front-end amplifier is part of an integrated sensor, with an array of which, forms a charge readout plane in a high-pressure gaseous Time Projection Chamber (TPC) for 0νββ search. The novel front-end amplifier composed of a source-drain follower and a common-source amplifier is proposed. The potential of both the source and drain node of the input transistor follows its gate. Hence the effective input capacitance contributed by the input transistor is significantly reduced. A hexagon charge collection electrode with a diameter of 1 mm is connected to the input node of the front-end amplifier. The shielding technique is applied and the shielding metal is connected to the source or drain node of the input transistor. Therefore, the effective input capacitance contributed by the charge collection electrode is decreased. The extraction result shows that the input capacitance is decreased from the 4 pf down to 7.4 fF. A test chip has been designed and an equivalent noise charge of 33 e− is achieved from the simulations.

A 1.8-2.7 GHz Triple-Band Low Noise Amplifier with 31.5 dB Dynamic Range of Power Gain and Adaptive Power Consumption for LTE Application.

This paper presents a multi-gain radio frequency (RF) front-end low noise amplifier (LNA) utilizing a multi-core based on the source degeneration topology. The LNA can cover a wide range of input and output frequency matching by using a receiver (RX) switch at the input and a capacitor bank at the output of the LNA. In the proposed architecture here, to avoid the saturation of RX chain, 12 gain steps including positive, 0 dB, and negative power gains are controlled by a mobile industry processor interface (MIPI). The multi-core architecture offers the ability to control the power consumption over different gain steps. In order to avoid the phase discontinuity, the negative gain steps are provided using an active amplification and T-type attenuation path that keeps the phase discontinuity below ±5 degrees between two adjacent power gain steps. Using the multi-core structure, the power consumption is optimized in different power gains. The structure is enhanced with the adaptive variable cores and reactance parameters to maintain different power consumption for different gain steps and remain the output matching in an acceptable operating range. Furthermore, auxiliary linearization circuitries are added to improve the input third intercept point (IIP3) performance of the LNA. The chip is fabricated in 65 nm complementary metal-oxide semiconductor (CMOS) silicon on insulator (SOI) process and the die area is 0.308 mm2. The proposed architecture achieves the IIP3 performance of −10.2 dBm and 8.6 dBm in the highest and lowest power gains, which are 20.5 dB and −11 dB, respectively. It offers the noise figure (NF) performance of 1.15 dB in the highest power gain while it reaches 14 dB when the power gain is −11 dB. The LNA consumes 16.8 mA and 1.33 mA current from a 1 V power supply that is provided by an on-chip low-dropout (LDO) when it operates at the highest and lowest gains, respectively.

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Analysis and Design of a Broadband Output Stage With Current-Reuse and a Low Insertion-Loss Bypass Mode for CMOS RF Front-End LNAs

This article presents a comprehensive analysis of a novel broadband output stage for external RF front-end low-noise amplifiers (eLNAs). Both variants of the output stage are manufactured using a 130nm bulk CMOS technology. They utilize a common-drain output stage with current-reuse topology, switchable resistive feedback, and source-degeneration. Also, a novel inductor-less low insertion-loss bypass mode is implemented for enhanced bypass functionality. The LNAs are implemented with 4 gain modes achieving excellent RF performance in all possible mobile communication scenarios. Furthermore, an auxiliary linearization circuitry (NMOS IMD sinker) is implemented for variant β to improve linearity performance in low gain mode. Besides, the LNAs support all frequency bands between 1.4GHz and 2.7GHz by only changing the external matching component, allowing easy adaption to different frequency bands. Two offered solutions are realized with a die size of only 0.16mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.11mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. The power consumption is 6.0mW in high gain, 3.6mW in low gain and active-bypass and 0.12mW in bypass mode using a supply voltage of 1.2V. Moreover, a 5.15GHz LNA with high-Q on-chip matching and the broadband output stage is realized and manufactured using a 60nm RF SOI technology. A NF performance of only 1.15dB is achieved consuming only 6.0mW power.

Miniaturized 0.13-μm CMOS Front-End Analog for AlN PMUT Arrays.

This paper presents an analog front-end transceiver for an ultrasound imaging system based on a high-voltage (HV) transmitter, a low-noise front-end amplifier (RX), and a complementary-metal-oxide-semiconductor, aluminum nitride, piezoelectric micromachined ultrasonic transducer (CMOS-AlN-PMUT). The system was designed using the 0.13-μm Silterra CMOS process and the MEMS-on-CMOS platform, which allowed for the implementation of an AlN PMUT on top of the CMOS-integrated circuit. The HV transmitter drives a column of six 80-μm-square PMUTs excited with 32 V in order to generate enough acoustic pressure at a 2.1-mm axial distance. On the reception side, another six 80-μm-square PMUT columns convert the received echo into an electric charge that is amplified by the receiver front-end amplifier. A comparative analysis between a voltage front-end amplifier (VA) based on capacitive integration and a charge-sensitive front-end amplifier (CSA) is presented. Electrical and acoustic experiments successfully demonstrated the functionality of the designed low-power analog front-end circuitry, which outperformed a state-of-the art front-end application-specific integrated circuit (ASIC) in terms of power consumption, noise performance, and area.

An overview of the effects of out‐of‐band interference on GNSS receivers

<h3>Abstract</h3> This paper addresses the wide range of mechanisms through which out-of-band interference can disrupt the functioning of GNSS receivers. These mechanisms include saturation and desensitization of front-end low noise amplifiers, mixers and other circuitry; reciprocal mixing effects that arise from the fact that receivers cannot generate a perfect tone to down-convert the desired signals; intermodulation products; aliasing of out-of-band emissions that remain after filtering into the receiver’s passband; and the reception of in-band (to GNSS) emissions that are always present due to imperfections in the signal generation and filtering of the interfering system. These mechanisms are described in detail and mitigation approaches for each are discussed.

A super-regenerative-oscillator wake-up receiver for underwater applications with improved PVT immunity

A novel super-regenerative wake-up receiver for underwater communication systems is presented. Optimized wake-up receiver design for underwater communications plays an important role in increasing the deployment duration of sensor nodes through reduced power consumption. In this work, the super-regenerative oscillator (SRO) based receiver is designed to receive 20 kHz underwater acoustic signal. To enable high sensitivity without compromising the loop gain, a novel current-reuse SRO architecture is proposed using adaptive bulk biasing to increase negative transconductance $$ - G_{m} $$ under the same biasing current with improved sensitivity and start-up time. Differential input transistors with dynamic threshold control techniques are used to increase input transconductance and improve the gain without the need of a front-end low noise amplifier. A differential switch-controlled charge-pump is adopted to provide the quenching mechanism for the SRO. Furthermore, additional digital automatic gain control, frequency-lock loop, and common mode feedback are designed to improve the SRO immunity under process–voltage–temperature variations. The proposed super-regenerative receiver is implemented in TSMC 180 nm CMOS technology with center frequency of 20 kHz. It achieves sensitivity of − 83 dBm with data rate of 100 kbps and power consumption of 114 μW.

Gallium arsenide 0.5–18 GHz antenna front‐end with integrated limiter and differential to single ended low‐noise amplifier

In this study, the authors present a 36:1 relative bandwidth active front-end low-noise amplifier (LNA) with power limiter that has been developed for airborne ultra-wideband receiver systems. The proposed system is driven by an external antenna with a balanced mode with an input impedance of 150 Ω. The whole microwave monolithic integrated circuit (MMIC) embeds a protection from the presence of high-level signals, an ultra-wideband amplifier circuit, an active balun and an impedance transformer. It has a bandwidth ranging from 0.5 to 18.0 GHz with 14 dB gain, 4.5 dB noise figure (NF), 20 dB common-mode rejection and 30 dBm input overload protection. The circuit has a single bias from the output port greatly simplifying its use within a receiving system and can be directly integrated into the antenna mechanical support. Test measurements are also provided.

The AD and ELENA orbit, trajectory and intensity measurement systems

This paper describes the new Antiproton Decelerator (AD) orbit measurement system and the Extra Low ENergy Antiproton ring (ELENA) orbit, trajectory and intensity measurement system. The AD machine at European Organization for Nuclear Research (CERN) is presently being used to decelerate antiprotons from 3.57 GeV/c to 100 MeV/c for matter vs anti-matter comparative studies. The ELENA machine, presently under commissioning, has been designed to provide an extra deceleration stage down to 13.7 MeV/c. The AD orbit system is based on 32 horizontal and 27 vertical electrostatic Beam Position Monitor (BPM) fitted with existing low noise front-end amplifiers while the ELENA system consists of 24 \\gls{BPM}s equipped with new low-noise head amplifiers. In both systems the front-end amplifiers generate a difference (delta) and a sum (sigma) signal which are sent to the digital acquisition system, placed tens of meters away from the AD or ELENA rings, where they are digitized and further processed. The beam position is calculated by dividing the difference signal by the sum signal either using directly the raw digitized data for measuring the turn-by-turn trajectory in the ELENA system or after down-mixing the signals to baseband for the orbit measurement in both machines. The digitized sigma signal will be used in the ELENA system to calculate the bunched beam intensity and the Schottky parameters with coasting beam after passing through different signal processing chain. The digital acquisition arrangement for both systems is based on the same hardware, also used in the ELENA Low Level Radio Frequency (LLRF) system, which follows the VME Switched Serial (VXS) enhancement of the Versa Module Eurocard 64x extension (VME64x) standard and includes VITA 57 standard Field Programmable Gate Array Mezzanine Card (FMC). The digital acquisition Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) firmware shares many common functionalities with the LLRF system but has been tailored for this measurement application in particular. Specific control and acquisition software has been developed for these systems. Both systems are installed in AD and ELENA. The AD orbit system currently measures the orbit in AD while the ELENA system is being used in the commissioning of the ELENA ring.

Electrical Rhythms Revealed by Harmonic Analysis of a High-Resolution Cardiogram.

The front-end low-noise electronic amplifiers and high-throughput computing systems made it possible to record ECG with a high resolution in the low-frequency range including the respiration and Mayer frequencies and to analyze ECG with digital filtering technique and harmonic analysis. These tools yielded ECG spectra of narcotized rats, which contained the characteristic pulsatile triplets and pentaplets with splitting constant equal to respiration rate, as well as the peaks at respiration and Mayer frequencies. The harmonic analysis of ECG determined the frequency parameters employed to tune the software bandpass filters, which revealed the respiratory (R) and Mayer (M) waves in the time domain with the amplitudes of 20-30 μV amounting to 5% ECG amplitude. The depolarizing myorelaxant succinylcholine chloride capable to trigger various types of arrhythmias, transiently increased R-wave, inhibited M-wave, and provoked a negative U-wave within a heartbeat ECG cycle synchronously with inspiration. It is hypothesized that M-, R-, and U-waves in ECG reflect cardiotropic activity of autonomic nervous system. The respective spectral peaks in ECG can be employed to assess intensity of sympathetic and parasympathetic cardiotropic influences, their balance, and the risk of arrhythmias.

Spectrum Sensing Under RF Non-Linearities: Performance Analysis and DSP-Enhanced Receivers

Intermodulation products arise as a result of low noise amplifier (LNA) and mixer non-linearities in wideband receivers. In the presence of strong blockers, the intermodulation distortion can deteriorate the spectrum sensing performance by causing false alarms and degrading the detection probability. We theoretically analyze the impact of third-order non-linearities on the detection and false alarm probabilities for both energy detectors and cyclostationary detectors under front-end LNA non-linearities. We show that degradation of the detection performance due to nonlinearities of both energy and cyclostationary detection is strongly dependent on the modulation type of the blockers. We then propose two DSP-enhanced receiver architectures to compensate the impact of nonlinearities. The first approach is a post-processing technique which compensates for nonlinearities effect on the test statistic by adapting the sensing time and detection threshold. The second approach is a pre-processing method that compensates by correcting received samples prior to computing the test statistic. This approach is based on adaptively estimating the intermodulation distortion, weighting it by a scalar constant and subtracting it from the subband of interest. We propose a method to adaptively compute the optimal weighting coefficient and show that it depends on the power and modulation of the blockers. Our results show that the pre-processing sample-based compensation method is more effective and that clear dynamic range extension can be obtained by using intermodulation compensation without resorting to increasing the sensing time. We also study the impact of uncertainties about the knowledge or estimates for nonlinearity parameters.

A 15 &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\mu{\rm W}$&lt;/tex&gt;&lt;/formula&gt; 5.5 kS/s Resistive Sensor Readout Circuit with 7.6 ENOB

A low power SAR logic-based resistive sensor readout circuit is proposed. A high sensitivity thermistor is used for local temperature measurements. The need for a low-noise front-end voltage amplifier is avoided by employing time-domain operation. In each operation step the sensor resistance is compared with the value of a reference resistive DAC which is implemented on chip. Therefore no stable, temperature compensated reference voltage is needed for operation. Furthermore the chip is operational with supply voltages ranging from 1.2 to 1.8 volts. Detailed analyses of the circuit gain and noise are provided. In addition, the effect of circuit topology on the noise performance is discussed. The effect of 1/f noise on accuracy of the circuit is also negligible due to resetting the charge-integrating capacitor after each comparison. A prototype chip is fabricated in 0.18- μm CMOS. The circuit dissipates 15 μW with 5.5 kS/s conversion rate from a 1.5 V supply. The complete interface circuit has 14 pJ/c-s figure of merit and 7.6 effective number of bits.

A 0.5 &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;${\rm cm}^{3}$&lt;/tex&gt;&lt;/formula&gt; Four-Channel 1.1 mW Wireless Biosignal Interface With 20 m Range

This paper presents a self-contained, single-chip biosignal monitoring system with wireless programmability and telemetry interface suitable for mainstream healthcare applications. The system consists of low-noise front end amplifiers, ADC, MICS/ISM transmitter and infrared programming capability to configure the state of the chip. An on-chip packetizer ensures easy pairing with standard off-the-shelf receivers. The chip is realized in the IBM 130 nm CMOS process with an area of 2×2 mm(2). The entire system consumes 1.07 mW from a 1.2 V supply. It weighs 0.6 g including a zinc-air battery. The system has been extensively tested in in vivo biological experiments and requires minimal human interaction or calibration.

A 0.5 V &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$&amp;lt; \hbox{4}\ \mu$&lt;/tex&gt;&lt;/formula&gt;W CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor

A 0.5 V CMOS light-to-digital converter (LDC) based on a nonuniform quantizer and off-chip photodiode enables a photodiode bias current (Ibias) range spanning 4 nA to 3.5 μA while consuming less than 4 μW of power. Using an off-chip LED as a modulated light source, measurements with a photodiode current signal having modulation frequency of 1.2 Hz (72 beats per minute) and 0.5% peak-to-peak amplitude relative to I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bias</sub> performed at the low and high end of the Ibias range confirm over 30 dB of SNR for an integration bandwidth spanning 0.5 to 5 Hz. Using off-chip digital signal processing of the LDC output, instantaneous period jitter (a proxy for instantaneous heart rate) is measured to be less than 0.45% (rms) of the period, and the high sensitivity of the LDC allows detection of the heart-rate signal from a finger pressed against the off-chip photodiode using only ambient light. Key circuit components of the LDC include a wide range logarithmic digital-to-resistance converter (DRC) utilizing digital multibit ΔΣ modulation to achieve fine resolution and a nonuniform quantizer based on a laddered inverter quantizer (LIQAF) which also acts as a low-noise front-end amplifier and filter.

차세대 항공 감시시스템(ADS-BES) 지상국 수신기 저잡음 증폭기 설계 및 구현

본 논문에서는 차세대 항공 감시시스템에 대하여 소개하고, 지상국 수신기 전단부 저잡음 증폭기 설계에 관하여 연구하였다. 국제 표준 문서와 기존 제품의 성능을 고려하여 수신감도, 신뢰성 등이 경쟁력 있게 전체 시스템을 링크 버짓 하였으며, 이에 적합한 저잡음 증폭기를 얻기 위해 이득, 이득 평탄도, 반사손실 등을 최적이 되도록 설계 규격을 결정하였다. 설계시 저전력, 저잡음, 고이득 특성에 적합한 바이어스 회로를 구성하였으며, 최적 설계 후 실시한 모의실험 결과로 이득은 16.24dB, 잡음지수는 0.36dB, 입출력 반사손실은 각각 -18dB와 -28dB, 주파수 안정도는 1.11을 얻었고, 제작 후 측정 결과는 이득 17dB, 잡음지수 0.51dB, 이득 평탄도 0.23dB, 입출력 반사손실은 각각 -18.28dB, -24.50dB로 전체 시스템 구성에 적합한 결과를 얻었다. This article introduces the next-generation air surveillance system and investigates how to design of front-end low noise amplifier of the ground station receiver. In consideration of the international standard documentation and the performance of existing products, the study conducts the link budget on the entire system so that it can be competitive in terms of receive sensitivity or reliability. To obtain a proper low noise amplifier, standards of design are decided so that such factors as gain, gain flatness, and reflective loss can be optimal. In its design, the bias circuit appropriate for the characteristics of low power, low noise, or high gain was built, and according to the results of the simulation conducted after the optimal design, its gain was 16.24dB, noise factor was 0.36dB, input-output reflective loss was -18dB and -28dB each, and frequency stability was 1.11. According to the results measured after the design, its gain was 17dB, noise factor was 0.51dB, gain flatness was 0.23dB, and input-output reflective loss was -18.28dB and -24.50dB each, so the results gained were suitable for building the overall system.

A Harmonic-Rejecting CMOS LNA for Broadband Radios

The local oscillator harmonics corrupt the desired signal in broadband RF receivers by downconverting interferers. This paper proposes the notion of harmonic rejection in the front-end low-noise amplifier so as to relax the stringent matching required of harmonic-reject mixers. Described are frequency response shaping techniques by feedforward and unilateral Miller capacitance multiplication for a signal bandwidth of 100 MHz to 10 GHz. A calibration algorithm is also proposed for the tuning of the frequency response. An experimental prototype fabricated in 65-nm digital CMOS technology provides at least 20 dB of rejection while consuming 8.64 mW with a 1.2-V supply.

The High-Altitude MMIC Sounding Radiometer for the Global Hawk Unmanned Aerial Vehicle: Instrument Description and Performance

The Jet Propulsion Laboratory's High-Altitude Monolithic Microwave Integrated Circuit (MMIC) Sounding Radiometer (HAMSR) is a 25-channel cross-track scanning microwave sounder with channels near the 60- and 118-GHz oxygen lines and the 183-GHz water-vapor line. It has previously participated in three hurricane field campaigns, namely, CAMEX-4 (2001), Tropical Cloud Systems and Processes (2005), and NASA African Monsoon Multidisciplinary Analyses (2006). The HAMSR instrument was recently extensively upgraded for the deployment on the Global Hawk (GH) unmanned aerial vehicle platform. One of the major upgrades is the addition of a front-end low-noise amplifier, developed by JPL, to the 183-GHz channel which reduces the noise in this channel to less than 0.1 K at the sensor resolution (~2 km). This will enable HAMSR to observe much smaller scale water-vapor features. Another major upgrade is an enhanced data system that provides onboard science processing capability and real-time data access. HAMSR has been well characterized, including passband characterization, along-scan bias characterization, and calibrated noise-performance characterization. The absolute calibration is determined in-flight and has been estimated to be better than 1.5 K from previous campaigns. In 2010, HAMSR participated in the NASA Genesis and Rapid Intensification Processes campaign on the GH to study tropical cyclone genesis and rapid intensification. HAMSR-derived products include observations of the atmospheric state through retrievals of temperature, water-vapor, and cloud-liquid-water profiles. Other products include convective intensity, precipitation content, and 3-D storm structure.

Variable-Gain, Low-Noise Amplification for Sampling Front Ends

This paper presents a low-noise front-end amplifier with configurable gain, targeting the recording of small signals, such as the electrocardiogram (ECG) or electroneurogram (ENG). The circuit consists of a continuous-time input stage using lateral bipolar transistors realized in complementary metal-oxide semiconductor (CMOS) technology followed by a switched-capacitor integrating stage. The voltage gain is adjustable by varying the phase delay between two system clocks. Simulated and measured results for a chip fabricated in 0.35-μm CMOS technology are reported. The amplifier occupies an active area of 0.064 mm(2), yields a nominal gain of 630 V/V with more than a 50-dB tuning range, less than 16 nVrms/√Hz input noise and a common-mode rejection of more than 97 dB. Its power consumption is 280 μW with a ±1.5-V supply.

A 5.4–9.2 GHz 19.5 dB Complementary Metal–Oxide–Semiconductor Ultrawide-Band Receiver Front-End Low-Noise Amplifier

In this work, we present an ultrawide-band (UWB) complementary metal–oxide–semiconductor (CMOS) low-noise amplifier (LNA) for wireless communication in the upper UWB band, that is, from 5.4–9.2 GHz bandwidth with a wide-band 50 Ω input matching network in front of the LNA. A three-stage cascode-topology-based LNA with high-transconductance MOS transistors, was employed to improve the voltage gain up to 23 dB at 7.5 GHz, with 4.5–9.2 GHz 3 dB bandwidth. The maximum output power S21 was 19.5 dB at 7.3 GHz, with 5.4–9.2 GHz 3 dB bandwidth. The input matching circuit was designed with a reduced number of passive elements, resulting in an input reflection coefficient S11 of less than -10 dB from 4.5–9.2 GHz. The noise figure of the LNA was as low as 3.5 dB and the input-referred third-order intercept point (IIP3) was -8 dBm. The LNA has output reflection coefficient S22 of less than -10 dB from 5–7 GHz and a good reverse isolation, that is, S12 of < -45 dB in the entire UWB, due to a cascode topology. The LNA was fabricated using 180 nm CMOS technology, which consumes 56 mW power at 1.8 V power supply. In this paper, we also demonstrate a wireless communication of 7 GHz Gaussian monocycle pulse (GMP) by horn antennas and the LNA from 20 cm transmission distance.