Front-end Board Research Articles

Effects of the electronic threshold on the performance of the RPC system of the CMS experiment

Resistive Plate Chambers have a very important role for muon triggering both in the barrel and in the endcap regions of the CMS experiment at the Large Hadron Collider (LHC) . In order to optimize their performance, it is of primary importance to tune the electronic threshold of the front-end boards reading the signals from these detectors. In this paper we present the results of a study aimed to evaluate the effects on the RPC efficiency, cluster size and detector intrinsic noise rate, of variations of the electronics threshold voltage.

Design and hardware evaluation of the optical-link system for the ATLAS Liquid Argon Calorimeter Phase-II Upgrade

An optical link system is being developed for the ATLAS Liquid Argon Calorimeter Phase-II upgrade. The optical link system is responsible for transmit the data of over 182 thousand detector channels from 1524 Front-End Boards (FEBs) through 26 optical fibers per FEB over 150 meters to the counting room and brings clocks, bunch crossing reset signals and slow control/monitoring signals back to the FEBs. The optical link system is based on the Low-Power GigaBit Transceivers (lpGBTs) and the Versatile optical Transceiver (VTRx+) modules, which both are being developed for the High-Luminosity LHC upgrade. An evaluation board is designed and the major functions of the optical link system are being evaluated. The design of the optical link system and the evaluation of major functions are presented in the paper.

Clock-Centric Serial Links for the Synchronization of Distributed Readout Systems

Detector readout systems for medium to large scale physics experiments, and instruments in some other fields as well, are generally composed of multiple front-end digitizer boards distributed over a certain area. Often, this hardware has to be synchronized to a common reference clock with minimal skew and low jitter. Today's mainstream solutions to precise clock distribution and deterministic latency messaging rely on the capabilities of high speed serial transceivers (a.k.a. SerDes) embedded in modern Field Programmable Gate Arrays (FPGAs). An alternative option uses distinct clock and data links. This can potentially reach higher synchronization accuracy, at significant hardware expenses. This work reports some first steps to explore a third scheme for clock and synchronous message distribution. Like the standard approach, the same media is used to convey clock and data, but instead of using today's "data-centric" links where the recovered clock is only a by-product of a SerDes, this paper defines and investigates "clock-centric" links where, at the opposite, a clock is carried by the link, and synchronous data are embedded into it by a modulation technique. After defining the concepts and principles of data-centric links, experimental studies are presented. Finally, the merits and limitations of the proposed approach are discussed.

Packaging strategies for large SiPM-based cryogenic photo-detectors

The DarkSide program aims to a WIMP direct detection using a dual phase argon time projection chamber. The next generation experiment, DS-20k, will be a detector in excess of 20 tonnes of fiducial mass. A pivotal aspect to the sensitivity of the experiment is its light detection technology. The DarkSide collaboration decided to adopt Silicon Photomultipliers for its Photo Detector Module (PDM). Each PDM includes a total active surface of 25 cm2 of SiPMs read-out by a front-end board capable of aggregating all the signals in a single analog output with a signal-to-noise ratio larger than 8. In this talk an overview of the silicon packaging strategies adopted by the DarkSide collaboration will be introduced with attention to the mass-production of about 10000 PDMs, corresponding to 200000 SiPMs and to the material selection in terms of cryogenic operation and high radio-purity.

Electronics performance of the ATLAS New Small Wheel Micromegas wedges at CERN

A series of upgrades are planned for the LHC accelerator to increase its instantaneous luminosity to 7.5 × 1034 cm−2s−1. The luminosity increase drastically impacts the ATLAS trigger and readout data rates. The present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector which is expected to be installed in the ATLAS underground cavern by the end of the Long Shutdown 2 of the LHC . With the final micromegas (MM) quadruplets (modules) already produced the activities concerning the integration of the modules into the final, fully equipped MM wedges, that will then be installed on the wheel structure on surface, are currently in full swing at CERN. One crucial part of the integration procedure concerns the installation, testing and validation of the on-detector electronics and readout chain for a very large system with more than 2.1 millions electronic channels in total. These include ∼4 thousands MM Front-End Boards (MMFE8), custom printed circuit boards each one housing eight 64-channel VMM Application Specific Integrated Circuits (ASICs) that interface with the ATLAS Trigger and Data Acquisition (TDAQ) system through ∼1 thousands data-driver cards (ADDC & L1DDC, respectively). The readout chain is based on optical link technology (GigaBit Transceiver links) connecting the back-end to the front-end electronics via the Front-End LInk eXchange (FELIX), a newly developed system that will serve as the next generation readout driver for ATLAS. Experience and performance results from the first large-scale electronics integration tests performed at CERN on final MM wedges, including system validation with cosmic-rays, are presented.

The cryogenic electronics for Dark Side-20k SiPM readout

The DarkSide-20k experiment aims to the direct WIMP detection in extremely low background conditions, using a Time Projection Chamber (TPC) filled with 40 tons of Liquid Argon and equipped with more than 200000 Silicon Photomultipliers (SiPMs) operated at cryogenic temperature. Since many years, the Bruno Kessler Foundation has been involved in the development of different kind of SiPMs sensitive to different wavelengths with low dark count rate and correlated noise. After a long and successful R&D, excellent results have been obtained, fully matching the specifications required by a background-free liquid argon experiment. The TPC will be instrumented with 8280 Photo Detection Modules each made by a SiPM tile of 25 cm2 and a Front End Board, in an acrylic mechanical structure. A dedicated cryogenic electronics with an optical transmission of the signal has been developed to read out the large SiPM area and reduce the mass of the cables in the cryostat due to the wide number of independent channels guaranteeing at the same time a high level of radiopurity. Moreover, the assembly of such a huge number of photodetectors demands a dedicated facility: the DarkSide strategy and working plan will be also reported.

The design of China Reconfigurable ANalog-digital backEnd for FAST

The Five-hundred-meter Aperture Spherical radio Telescope (FAST) was launched on 2016 September 25. From early 2017, we began to use the FAST wideband receiver, which was designed, constructed and installed on the FAST in Guizhou, China. The front end of the receiver is composed an uncooled Quad Ridge Flared Horn feed (QRFH) with the frequency range of 270 to 1620 MHz, and a cryostat operating at 10 K. We have cooperated with the Institute of Automation of the Chinese Academy of Sciences to develop the China Reconfigurable ANalog-digital backEnd (CRANE). The system covers the 3 GHz operating band of FAST. The hardware part of the backend includes an Analog Front-end Board, a wideband high precision Analog Digital Converter, and a FAST Digital Back-end. Analog circuit boards, field programmable gate arrays, and control computers form a set of hardware, software, and firmware platforms to achieve flexible bandwidth requirements through parameter changes. It is also suitable for the versatility of different astronomical observations, and can meet specific requirements. This paper briefly introduces the hardware and software of CRANE, as well as some observations of the system.

Spectrum shaping using NC‐OFDM for cognitive radio applications

Cognitive radio (CR) is an innovative technology that supports dynamic spectrum access to utilise the spectrum more efficiently in an opportunistic manner without interfering with the licensed users. Multi-carrier modulation techniques such as orthogonal frequency division multiplexing (OFDM) is identified as one of the suitable candidates for the design of CR systems. To provide high data rates while avoiding interference with licensed users, a variant of OFDM called non-contiguous OFDM (NC-OFDM) is used in CR. NC-OFDM is useful for dynamic shaping of spectrum based on the channel impairments, interference and jamming threats. In this work, the customised NC-OFDM transceiver link is simulated and compared with the customised OFDM link in the MATLAB environment. It is implemented in Zynq-7000 System-on-Chip (SoC) 7Z020 with radio-frequency front-end board, AD-FMCOMMS3-EBZ Software Defined Radio platform. Implementation of this link is carried out on Spartan-3A FPGA and compared the hardware resource utilisation with Zynq platform. It is observed that the Zynq platform utilises less hardware resources for the implementation. The transmitter spectrum, spectrum after de-activating unwanted sub-carriers, the spectrum shaping using raised cosine filtering, spectrum sensing using the correlation of known pattern and FFT-based spectrum sensing are also simulated in the MATLAB.

Design and Performance of Data Acquisition and Control System for the Muon g-2 Laser Calibration

The Muon g-2 Experiment at Fermilab (E989) will measure the muon magnetic anomaly with unprecedented precision (0.14 ppm), which yields a factor of 4 improvement with respect to the previous measurements at Brookhaven National Laboratory (BNL) (E821). To achieve this goal, the relative response of each calorimeter channel must be calibrated and monitored at a level better than $10^{-3}$ in the time window of the muon fill. The calibration system uses a laser source and photodetectors. The data acquisition (DAQ) of the system is designed around two field-programmable gate array (FPGA)-based boards and a custom crate bus. The front-end board manages the photodetector operation and signal processing and performs a first-level data concentration task. Up to 12 FPGA boards can be housed in a 6U crate. A readout master controls the boards, implements event-building functionalities, manages the monitoring interface, and facilitates calibration and debugging tasks. A gigabit-ethernet interface is used to transfer data to the on-line farm for storage and further processing. Presently, the system is working at Fermi National Accelerator Laboratory (FNAL). In this article, we present the DAQ system design, run control user interface, and system evaluation.

Sub-nanosecond synchronization node for high-energy astrophysics: The KM3NeT White Rabbit Node

The first Detection Units of the KM3NeT infrastructure, whose main goal is the detection of cosmic neutrinos, are currently being deployed on the Mediterranean Sea bed. The collaboration has chosen White Rabbit for providing sub-nanosecond synchronization between the Digital Optical Modules, the main detection component of the detector. White Rabbit functionality is provided by the main front-end electronics board, the so called Central Logic Board, that embeds both the White Rabbit firmware, as an IP core on a XILINX Kintex FPGA, and the tunable oscillators, the hardware needed to make White Rabbit to work. The present article describes the Central Logic Board of KM3NeT, focusing on how it provides White Rabbit functionalities.

Automatic test system for pFEB and sFEB mass production

Abstract This paper presents an automatic test system(ATS) for the pad front-end board(pFEB) and strip front-end board(sFEB) of ATLAS small-strip Thin Gap Chamber(sTGC) detector. The pFEB is designed to readout signals of pads and wires of sTGC detector, and the sFEB is designed to readout signals of strips of sTGC detector. There will be thousands of pFEBs and sFEBs produced in mass production (including spare p/sFEBs), and all of them must pass the quality tests before delivery. To reduce the time and man power cost of the quality tests, we developed this automatic test system for mass production tests of p/sFEBs. The test system consists of a FEB Test Board(FTB), a Test Pulse Board(TPB) and a control software. The FTB connects with p/sFEB through mini-SAS cables and communicates with the control software through Gigabit Ethernet. The TPB injects external test signals to p/sFEB through GFZ. The control software provides several interfaces to set configuration parameters for p/sFEB and controls the test processes. The FTB sends configuration data to p/sFEB, and then readouts data from the them. The output data includes 4.8Gbps trigger data, 640Mbps level-1 event data, and so on. They are analyzed in FTB and then sent to the control software. The test system can automatically scan main functions and performances of p/sFEB, including channels performances, the configuration chain, the data chain, the trigger chain, etc. The specific characteristics and implementations are described in detail.

Development of a Time-of-Flight Electronics System for Neutron Beam Profiling at CSNS-WNS

A 256-channel time-of-flight (TOF) electronics system has been developed for a beam line facility called "Back-n WNS" in China Spallation Neutron Source (CSNS). This paper shows the structure and performance of electronics system and the test results in CSNS. A 256-channel photomultiplier tube (PMT) is chosen as the detector in this system. In order to acquire the time information from the PMT, an electronics system has been designed. The electronics system mainly includes one front-end board (FEB), four time-to-digital converter (TDC) boards and one clock distribution module (CDM). There are 256 channels on FEB and 64 channels on each TDC board. The FEB is connected to the PMT with high-density connectors and the TDC boards are connected to the FEB through 2m cables. The TDC boards are 6U size so that they can be PCI extensions for Instrumentation (PXI) cards. Data from TDC boards can be transferred to the PXI control card through the backboard. In order to make four TDC boards work synchronously, a CDM outputs four clock signals to TDC boards which are distributed from one clock source. The TDC boards achieve a timing resolution of 3.5ns by test with a signal generator. The TOF measurement system has been used in CSNS.

The Readout Electronics Research Design and Development for CEPC Scintillators Electromagnetic Calorimeter Prototype

The Circular Electron Positron Collider (CEPC) is a proposing electron–positron collider in China, which aims for generating high center-of-mass energy colliding above 250 GeV. The high-granularity electromagnetic calorimeter (ECAL) is included in a calorimeter system, which is mainly responsible for the measurement of photon. A particle flow algorithm (PFA)-based ECAL solution will utilize about 400k channels/m3. Here, we present the design and development status of readout electronics based on SPIROC2b for the CEPC ECAL with high-granularity scintillants and silicon photomultipliers (SiPMs). The readout electronics consists of front-end electronics (FEE), data interface (DIF) board, and data acquisition (DAQ) board. The front-end board (FEB) carries SiPMs (S12571-010P), scintillants (PSD), and FEB application-specific integrated circuit (ASIC) (SPIROC2b). Two electronics were designed in this paper, one is for ASIC functionality and performance only, and the other is used as a single layer of a further prototype of ECAL. Electronic test and cosmic ray test have been done to electronics. The results indicate that a charge dynamic from 62 fC to 300 pC at S/N = 2 is successfully achieved, and the minimum ionizing particles (MIPs) are separated from the pedestal.

A Scanning Test System of p/sFEB Based on FPGA XADC for the ATLAS Phase-I sTGC Upgrade

The pad front-end board (pFEB) and the strip front-end board (sFEB) are developed to read out signals from pads, wires, and strips of the sTGC detector for the ATLAS Phase-I Trigger Upgrade. The pFEB is used to gather and analyze pad trigger, and the sFEB is developed to accept the pad trigger to define the regions-of-interest for strips readout. The performance of p/sFEB must be confirmed before it is mounted on the sTGC detector. We present a scanning test system that is designed according to the test items of the p/sFEB. In the test system, a test pulse board is applied to generate different types of signals to the p/sFEB. The PC software and field-programmable gate array Xilinx analog-to-digital converter cooperate to achieve the scanning test of the analog parameter. At present, the system is utilized for the p/sFEB prototype performance test.

Development and preliminary results of Xtrim-PET, a modular cost-effective preclinical scanner

We report on development of Xtrim-PET, a prototype low-cost preclinical PET system using high-density analog silicone photomultiplier (SiPM) arrays and pixelated scintillator LYSO:Ce crystals. Channel reduction method is employed to reduce 144 SiPM signals per detector block to 16 energy and 9 fast signals in the detector head. Using these signals, a Digital Front-End (DFE) board calculates energy, position, and time information of incident gamma photon and transmits data packets to a downstream Digital Coincidence Processing Unit (DCPU) in which the coincidence events are extracted in a fully pipelined digital processing fashion for maximum count throughput. The system consists of 10 detector blocks (detector head and DFE board), a DCPU board, and an acquisition computer. Prompt and delayed coincidence events are stored in list mode in the acquisition computer where first hand corrections are applied and 3D sinogram is generated in offline mode. Two-dimensional sinograms are then generated using single-slice rebinning algorithm and iterative image reconstruction methods are employed to generate the 3D image. The developed scanner works in room temperature without additional cooling system and has 180 mm ring diameter. Tomographic image resolution of 1.6, 1.7, and 1.8 mm FWHM was calculated along radial, tangential, and axial directions, respectively. Preliminary investigations were performed using NEMA image quality phantom in addition to rat cardiac and bone scans for preclinical evaluation of the scanner.

Development and application of a modular test system for the HV-CMOS pixel sensor R&D of the ATLAS HL-LHC upgrade

High-voltage CMOS is a promising technology for the pixel sensor of tracking detectors in the collider experiments. Extensive studies are being carried out by the ATLAS Collaboration to investigate the possibility of using the HV-CMOS technology in the HL-LHC upgrade of the ATLAS inner tracker detector. The CaRIBOu (Control and Readout Itk BOards) is a modular test system developed to test the HV-CMOS pixel sensor prototypes and demonstrators. This test system consists of pixel sensor specific front-end chip boards, a control and readout board (CaR board), a central interface board and the back-end DAQ system. Currently, two DAQ solutions are available for the CaRIBOu system, one is based on the FELIX (front-end link eXchange) readout system and the other is based on the Gigabit Ethernet link. Various testbeam experiments have been carried out with the CaRIBOu system since 2015 for the pixel sensors fabricated by the AMS HV-CMOS 180 nm and 350 nm technologies. The test results show that this test system is very flexible and could be adapted to the test of different pixel sensors with minimum effort, and the performance meets the testbeam requirements.

Development of the readout system for a time projection chamber prototype

A new GEM-TPC prototype with a laser calibration system is being designed to study the key issues of high-precision track detection whose aimed spatial resolution is better than 100 μm. Meanwhile, a readout system with scalability for the TPC is also being developed. Design of the readout system is based on the architecture of front-end ASICs and commercial ADCs for its advantages at high count rates. Given the requirement of several hundred channels, the system is composed of multiple front-end cards and DAQ boards. The DAQ boards are daisy-chained via bidirectional optical fibers, which transmit clock, trigger, data and control signals simultaneously. To achieve timing synchronization, the GigaBit Transceiver (GBT) firmware is employed to ensure fixed latency between the boards. This paper is focused on the design and setup of the DAQ system, including clock structure, trigger alignment, high-speed data acquisition, etc. The DAQ system consisting of 512 channels has been built, and tests have proved that the entire system works correctly and meets the expected requirements.

One-dimensional parallax-free position-sensitive detector for diffraction measurements based on a home-made thin THGEM.

A large parallax-free gas diffraction meter based on a thinner-THGEM (thick gaseous electron multiplier) has been developed at the Beijing Synchrotron Radiation Facility (BSRF). A thinner-THGEM of thickness 200 µm is adopted, which can be shaped into a curve to eliminate parallax-error effects. The detector is designed to have a 48° open angle positioned 20 cm from the powder samples. A front-end electronics board with 128 channels direct-current mode was adapted for the 8 keV BSRF beamline with 0.2 ns/100 ns stable duty cycle. Two powder samples, TiO2 and SnO2, were tested separately. The measured spectra with an angular resolution of 0.148 ± 0.081° are consistent with the data from the powder diffraction file. Combining the gas gain of the thinner-THGEM with the electronic circuit dynamic range, a very broad dynamic range of about 107 could be obtained.

Upgrade of the ATLAS Tile Calorimeter for the High Luminosity LHC

The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the central region of the ATLAS experiment. TileCal is a sampling calorimeter with steel as absorber and scintillators as active medium. The scintillators are read-out by wavelength shifting fibers coupled to photomultiplier tubes (PMTs). The analogue signals from the PMTs are amplified, shaped, digitized by sampling the signal every 25 ns and stored on detector until a trigger decision is received. The High-Luminosity phase of LHC (HL-LHC) expected to begin data taking in 2026 requires readout electronics suitable for a 1 MHz trigger rate, higher ambient radiation, and for better performance under high pileup. Both the on- and off-detector TileCal electronics will be replaced during the shutdown of 2024-2025. PMT signals from every TileCal cell will be digitized and sent directly to the back-end electronics, where the signals are reconstructed, stored, and sent to the first trigger level at a rate of 40 MHz. This will provide better precision of the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. Changes to the electronics will also enhance the data integrity and reliability of the system. Three front-end board options were built and investigated both in laboratory and in several beam test campaigns. The final version has been chosen after evaluating the results. A hybrid Demonstrator for the new readout architecture and compatible with the present system has been developed, adopting the new chosen front-end option. The Demonstrator is undergoing extensive testing and is planned for future insertion in ATLAS.

Front-end electronics of the Belle II aerogel ring imaging detector

A proximity focusing RICH detector with an aerogel radiator is used for charged particle identification in the forward end-cap of the Belle II spectrometer. The detector, consisting of a 4 cm aerogel radiator, a 16 cm expansion volume and a photon detector with 420 Hybrid Avalanche Photo Detectors, is mounted in a very confined space between Central Drift Chamber and Electromagnetic Calorimeter, allowing only 5 cm of space for the readout electronics. In our solution, low power front-end read-out boards are mounted at the back side of each of the HAPD photosensors. These boards have each been tested individually before their installation onto the photosensors and into the spectrometer. Most important design issues and first experiences with the aforementioned front-end read-out boards are presented in this contribution.