Front-end ASIC Research Articles

First experimental results on Ignite0: A prototype pixel front-end ASIC with timing in 28 nm

This contribution presents the results of the first test activity on the Ignite-0 ASIC. The main challenge of this microelectronics development is to reach an overall time resolution of at least 50 ps, on a pixel front-end ASIC within the constraints defined by high-luminosity HEP experiments.Ignite-0 has been developed during 2023 in order to test individually the building blocks for the future developments on the front-end ASIC. It contains mainly the pixel front-end electronics such as the Analog Front-End and the Time to Digital Converter, but it also integrates various service blocks. All the integrated blocks have been designed to satisfy the desired requirements and constraints both in terms of power, performance and form-factor.

Beam test performance studies of CMS Phase-2 Outer Tracker module prototypes

A new tracking detector will be installed as part of the Phase-2 upgrade of the CMS detector for the high-luminosity LHC era. This tracking detector includes the Inner Tracker, equipped with silicon pixel sensor modules, and the Outer Tracker, consisting of modules with two parallel stacked silicon sensors. The Outer Tracker front-end ASICs will be able to correlate hits from charged particles in these two sensors to perform on-module discrimination of transverse momenta (p T). The p T information is generated at a frequency of 40 MHz and will be used in the Level-1 trigger decision of CMS. Prototypes of the so-called 2S modules were tested at the Test Beam Facility at DESY Hamburg between 2019 and 2020. These modules use the final front-end ASIC, the CMS Binary Chip (CBC), and for the first time the Concentrator Integrated Circuit (CIC), optical readout and on-module power conversion. In total, seven modules were tested, one of which was assembled with sensors irradiated with protons. An important aspect was to show that it is possible to read out modules synchronously. A cluster hit efficiency of about 99.75 % was achieved for all modules. The CBC p T discrimination mechanism has been verified to work together with the CIC and optical readout. The measured module performance meets the requirements for operation in the upgraded CMS tracking detector.

Characterisation studies of two front-end electronics chips designed for SiPM readout

A new front-end ASIC named ”PIST” (pico-second timing) has been successfully developed using 55 nm CMOS technology for the silicon photomulplier (SiPM) readout with a single channel with a major aim of fast timing. We performed extensive tests to evaluate the timing performance of a dedicated test stand equipped with a PIST chip. The results show that the system timing resolution can reach sub 10 ps for large SiPM signals, while the PIST intrinsic timing resolution is better than 5 ps. The PIST dynamic range has been further extended using the time-over-threshold (ToT) technique. Meanwhile, we fully characterised a new commercially available SiPM-readout 32-channel ASIC for developments of future high-granularity crystal calorimetry, including the single photon calibration and the dynamic range of different gain regions. Other promising potentials include fast timing resolution, fast readout speed and low power dissipation. Comprehensive measurements were made with a laser beam and high-energy particle beams with crystals and SiPMs. First testing results show that this chip has an excellent signal-to-noise and a large dynamic range. This contribution will introduce the ASICs as well as dedicated test stands and also present highlighted results including the timing resolution, single photon calibration and dynamic range.

Construction and performance of the precision tracking chambers for the ATLAS muon spectrometer upgrade for high-luminosity LHC

For the operation at the High-Luminosity (HL) LHC, the Monitored Drift Tube (MDT) chambers of the inner barrel layer (BIS) of the ATLAS muon spectrometer will be replaced by small-diameter Muon Drift Tube (sMDT) chambers which will be integrated with triplets of thin-gap Resistive Plate Chambers (RPC) in order to improve the acceptance and robustness of the barrel muon trigger system. The sMDT chambers have half the drift tube diameter of the MDT chambers and about one order of magnitude higher background rate capability. The construction of the 96 new sMDT chambers was performed between January 2021 and September 2023 at two production sites at a continuous rate of one chamber every two weeks. The sense wire positioning accuracy guaranteed by precision assembly jigs was measured to be around 5μm over the whole construction period. Stringent performance tests had to be passed during the production which have been successfully repeated after delivery of the chambers to CERN. The chambers have been tested with the new MDT front-end ASICs developed for operation at HL-LHC which improve the spatial resolution of the drift tubes by 10% compared to readout with the legacy electronics.

The ATLAS RPC Phase-II upgrade for High Luminosity LHC era

Resistive Plate Chambers (RPC) detectors play a crucial role in triggering events containing muons in the central region of ATLAS. In view of the High Luminosity-LHC program, the existing RPC system, consisting of six independent cylindrical detector layers each providing a full space time localization of hits, is currently undergoing a significant upgrade. In the next few years, 306 triplets of new generation RPCs will be installed in the innermost region of the ATLAS Muon Barrel Spectrometer, increasing from 6 to 9 the number of tracking layers, doubling the trigger lever arm. This allows a substantial enhancement of the present trigger redundancy, increasing the coverage from 76% to approximately 96%. Fitting new chambers in the narrow space left in ATLAS inner barrel was a challenge, achieved by optimizing RPC materials and thickness, featuring a 1 mm gas gap (instead of 2 mm), and 1.4 mm resistive electrodes (instead of 1.8 mm) while reaching an high rate capability. To achieve such results, a 100 ps precise Time-to-Digital Converter (TDC) has been integrated in the front-end electronics ASIC. The expected time resolution of a single 1 mm RPC gas gap is approximately 300 ps, and the possibility of a stand-alone Time of Flight measurement will have a huge impact on ATLAS searches for massive long-lived particles. An overview and the present status of the ATLAS RPC Phase-II project will be presented.

Charge-sensitive amplifier design for high-speed interface readout front-end ASICs

The design of Charge-Sensitive Amplifiers (CSAs) and the peaking time impact on high-speed interface readout front-end ASICs for 3D pixel detectors with high timing precision, is addressed in this work. The performance of the CSAs is extracted for several architectures, implemented in 180 nm CMOS, 130 nm SiGe BiCMOS, 65 nm CMOS and 22 nm FD-SOI CMOS process nodes for comparison purposes versus technology scaling. The peaking time, the charge gain, the noise and the bandwidth are simulated for all implemented CSAs, while the best CSA candidate performance-wise for high-speed and high timing precision readout ASICs is designated. Furthermore, a full readout chain, capable of resolving particles with a time precision of <200 ps, is implemented and simulated. The designed readout ASIC exhibits a Time-Walk performance of ≤180 ps, for input charges of 6.3−10ke−, while inducing an equivalent noise charge of ≈570e−.

SET sensitivity of a VCRO-based PLL for HL-LHC ATLAS HGTD

We report the characterization of the Single Effect Transient (SET) sensitivity of an analogue Phase Locked Loop (PLL) based on a Voltage Controlled Ring Oscillator (VCRO) under a proton beam. The clock generator is embedded in a front-end ASIC, namely ALTIROC designed in CMOS 130 nm, reading out Low-Gain Avalanche Diode (LGAD) matrices for the High-Luminosity Large Hadron Collider (HL-LHC). We detail the methodology developed to study such events that could degrade the targeted time resolution of 35 ps per hit. Observed SET-induced phase jumps allow the estimation of the total cross-section of the PLL. The results are extrapolated to the HL-LHC radiation conditions.

Characterization of the ATLAS Liquid Argon Front-End ASIC ALFE2 for the HL-LHC upgrade

ALFE2 is an ATLAS Liquid Argon Calorimeter (LAr) Front-End ASIC designed for the HL-LHC upgrade. ALFE2 comprises four channels of pre-amplifiers and CR-(RC)2 shapers with adjustable input impedance. ALFE2 features two separate gain outputs to provide 16-bit dynamic-range coverage and an optimum resolution. ALFE2 is characterized using a Front-End Test Board (FETB) based on a Zynq UltraScale+ MPSoC and two octal-channel 16-bit high-speed ADCs. The test results indicate that ALFE2 fulfills or greatly exceeds all specifications on gain, noise, linearity, uniformity, and radiation tolerance.

Development of the Beam Conditions Monitoring Prime system for beam abort and luminosity monitoring in ATLAS based on a segmented polycrystalline CVD diamond system and dedicated front-end ASIC

The High Luminosity upgrade of Large Hadron Collider (HL-LHC) will increase the LHC luminosity and with it the density of particles on the detector by an order of magnitude. For protecting the inner silicon detectors of the ATLAS experiment and for monitoring the delivered luminosity, a radiation hard beam monitor was developed based on polycrystalline Chemical Vapor Deposition (pCVD) diamond detectors and a new dedicated rad-hard front-end ASIC. Due to the large range of particle flux through the detector, flexibility is very important. To satisfy the requirements imposed by the HL-LHC, our solution is based on segmenting diamond sensors into devices of varying size and reading them out with new multichannel readout ASICs divided into two independent parts — each of them serving one of the tasks of the system. This paper describes the system design including detectors, electronics, mechanics and services and presents preliminary results from the most recent detectors fabricated, using our prototype ASIC with data from beam tests at CERN.

FELIX: First operational experience with the new ATLAS readout system and perspectives for HL-LHC

The Front-End Link eXchange (FELIX) readout system is deployed as the new interface connecting detector front-end electronics with the data acquisition and Timing, Trigger and Control (TTC) systems. FELIX functions as a router between custom serial links from front-end ASICs and FPGAs to data collection and processing components via a commodity switched network. FELIX uses commodity server technology in combination with FPGA-based PCIe I/O cards. FELIX servers run a software routing platform serving data to network clients performing a number of data preparation, monitoring and control functions. This paper covers the design of FELIX as well as the first operational experience gained during the Run 3 start, including the challenges faced commissioning the system for each ATLAS sub-detector. Over the next decade, the ATLAS detector will be required to operate in an increasingly harsh collision environment and challenging data taking conditions. To maintain physics performance, the detector will undergo a series of upgrades. In particular, the readout system capabilities will be improved. The planned evolution of FELIX for High-Luminosity LHC will be described, including architectural changes and status of early integration with detector development projects.

The CMS HGCAL trigger data receiver

As part of the CMS Phase-2 upgrade, a prototype receiver for the HGCAL endcap front end has been implemented using the Serenity ATCA platform. The receiver firmware was developed to test the unpacking of data from the front-end endcap trigger concentrator ASIC (ECON-T) and measure its performance and stability. The firmware was integrated with prototype DAQ firmware as well as ancillary blocks to generate a trigger using ECON-T data, process scintillator trigger and timing distribution system, to evaluate the complete HGCAL vertical slice. The data was read out using custom 10G UDP links and upgraded to CMS DTH system at 25 Gbps. The system successfully achieved prototype TPG Stage-1 and DAQ path readout using generated beam triggers and delivered ~20 TB of data containing physics events at an average trigger rate of about 100 kHz.

Microstrip Silicon Detector for Study of Ultra-Fast Processes at the Synchrotron Radiation Beam

Present status of the development of the prototype of the Detector for imaging of explosions (DIMEX) based on silicon microtrip sensor is discussed. The prototype includes silicon p-in-n sensor with metal strips in direct contact with p-implants. Strips are 30 mm long and have 50 um pitch. Signals from the strips are read out with specially developed ASICs DMXS6A, that include 6 channels with DC compensation circuit at the input, four integrators, 32 analogue memory cells and output analogue shift register. The prototype detector has 96 registration channels provided with 16 DMXS6A ASICs. Each strip of the sensor is connected to the guard-ring through a 400 Ohm resistor and through 100 kOhm resistor to the input of the front-end ASIC. This resistive divider allows to adapt the dynamic range of the integrator of the ASIC to the full flux range of the beam line 8 at the VEPP-4M storage ring that includes 9-pole wiggler with 1.9 T B-field as SR source. The measurements of the dynamic range of the DIMEX-Si prototype demonstrate that maximum photon flux from one bunch that can be measured by this detector exceeds 100 000 photons per channel. For these measurements the sensor was inclined at an angle of 1.7 degrees with respect to the beam plane in order to increase quantum efficiency. The possibility to work in multi-bunch mode with bunches following in 55 ns is demonstrated, that proves that this detector can be successfully exploited at new SR-source SKIF that is under construction in Novosibirsk region.

Study experimental time resolution limits of recent ASICs at Weeroc with different SiPMs and scintillators

Medical applications, such as Positron Emission Tomography (PET), and space applications, such as Light Detection and Ranging (LIDAR), are in need of highly specialized ASICs. Weeroc, in collaboration with different partners, is highly involved in developing a new generation of front-end ASICs. In the context of a joined LIDAR project among Weeroc, CNES, and Airbus, Weeroc is working on the development of Liroc, an ASIC for space LIDAR application. Weeroc is also working on advancing ASICs for medical applications with Radioroc under development and intended to be used for PET applications. This study experimentally evaluates the time resolution limits of these ASICs in different configurations, with some of the most recent silicon photomultiplier (SiPM) technologies available on the market, coupled to different scintillation crystals. The best single-photon time resolution (SPTR) was achieved using FBK NUV-HD SiPMs with an FWHM of 90 ps with Liroc and 73 ps with Radioroc. Furthermore, the coincidence time resolution (CTR) of Radioroc was studied with different crystal sizes. Using a large LYSO:Ce,Ca crystal of (3 × 3 × 20 mm3) with Broadcom Near UltraViolet-Metal in Trench (NUV-MT) yields a CTR of 127 ps (FWHM). The best CTR of Radioroc was determined to 83 ps (FWHM) with Broadcom NUV-MT SiPMs coupled to LYSO:Ce,Ca (2 × 2 × 3 mm3)) from Taiwan Applied Crystal (TAC).

Performance of a front-end prototype ASIC for the ATLAS High Granularity timing detector

This paper presents the design and characterisation of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector, which is planned for the High-Luminosity phase of the LHC. This prototype, called ALTIROC1, consists of a 5 × 5-pad matrix and contains the analog part of the single-channel readout (preamplifier, discriminator, two TDCs and SRAM). Two preamplifier architectures (transimpedance and voltage) were implemented and tested. The ASIC was characterised both alone and as a module when connected to a 5 × 5-pad array of LGAD sensors. In calibration measurements, the ASIC operating alone was found to satisfy the technical requirements for the project, with similar performances for both preamplifier types. In particular, the jitter was found to be 15 ± 1 ps (35 ± 1 ps) for an injected charge of 10 fC (4 fC). A degradation in performance was observed when the ASIC was connected to the LGAD array. This is attributed to digital couplings at the entrance of the preamplifiers. When the ASIC is connected to the LGAD array, the lowest detectable charge increased from 1.5 fC to 3.4 fC. As a consequence, the jitter increased for an injected charge of 4 fC. Despite this increase, ALTIROC1 still satisfies the maximum jitter specification (below 65 ps) for the HGTD project. This coupling issue also affects the time over threshold measurements and the time-walk correction can only be performed with transimpedance preamplifiers. Beam test measurements with a pion beam at CERN were also undertaken to evaluate the performance of the module. The best time resolution obtained using only ALTIROC TDC data was 46.3 ± 0.7 ps for a restricted time of arrival range where the coupling issue is minimized. The residual time-walk contribution is equal to 23 ps and is the dominant electronic noise contribution to the time resolution at 15 fC.

A membrane, pseudo-vertical p-i-n diamond detector

ABSTRACT We report on the membrane diamond detector, which consists of 5 µm-thick p-i-n diodes and a dedicated front-end ASIC, fabricated in a 65-nm CMOS technology. The p-i-n diode has an attractive feature for low -ray sensitivities due to its extremely thin drift layer, which is difficult to form by etching of bulk diamond with a Metal−Insulator−Metal structure. The pseudo-vertical p-i-n diode structure was formed on the single crystal diamond {111} substrate by MPCVD and dry-etching process. The readout electronics was designed to meet specifications for real-time neutron monitoring in harsh -ray environments. The prototype system was evaluated in charge distribution measurements induced by -particles from Am. The charge spectra were successfully obtained from multi-channels, each of which has a diameter of 250 µm aligning in a pixel matrix. By combining with neutron converters, e.g. B or Li, we expect the detector system as a good candidate for detecting spontaneous fission neutrons, emitted from submerged fuel debris at the Fukushima Daiichi Nuclear Power Plant in Japan.

Performance of the new RD51 VMM3a/SRS beam telescope — studying MPGDs simultaneously in energy, space and time at high rates

The RD51 collaboration maintains a common infrastructure at CERN for its R & D activities, including two beam telescopes for test beam campaigns. Recently, one of the beam telescopes has been equipped and commissioned with new multi-channel and charge-sensitive front-end electronics based on the ATLAS/BNL VMM3a front-end ASIC and the RD51 Scalable Readout System (SRS). This allows to read out the detectors at high rates (up to the MHz regime) with electronics time resolutions of the order of 1 ns and the ability to handle different detector types and sizes, due to a larger dynamic range compared to the previous front-end electronics based on the APV25 ASIC. Having studied and improved the beam telescope's performance over the course of three test beam campaigns, the results are presented in this paper.

CIC: a radiation tolerant 65 nm data aggregation ASIC for the future CMS tracking detector at LHC

For the Phase II upgrade at HL-LHC, CMS needs a new Outer Tracker detector able to cope with reduced material budget, increased radiation tolerance and higher pile-up conditions with respect to LHC. The main feature of the Outer Tracker will be its inclusion at the first level of the CMS trigger system with data readout at 40 MHz. Two types of modules, Pixel-Strip and Strip-Strip will equip the Outer Tracker. Each module consists of a superposition of two silicon layers, able to detect charged particles, and an innovative readout electronics, allowing a significant data rate reduction. The Concentrator Integrated Circuit (CIC) is a 65 nm CMOS radiation tolerant front-end ASIC for both modules. It is considered a fundamental element of the future detector front-end chain due to its role in aggregating and compressing data from 8 front-end ASICs on each module. It reduces the data throughput by an order of magnitude. Two first version of the CIC were previously developed and tested. This paper will present the pre-production version, called CIC2.1, together with the functional and wafer test results.

LHCb VELO fast calibration

During the long shutdown 2 of the LHC, the LHCb Experiment was upgraded to a trigger-less system reading out the full detector at 40 MHz bunch crossing rate with all selection algorithms executed in a CPU farm. The upgraded Vertex Locator (VELO) of the LHCb is a hybrid pixel detector read out by the “VeloPix” front-end ASIC with on-chip zero-suppression. This paper describes a novel way of calibrating the VELO detector based on dedicated threshold scan firmware. The firmware is implemented in the control and data acquisition back-end boards of the detector. This threshold scan method has multiple advantages compared with the default one: it is faster as the algorithm was moved from software to firmware, it is more deterministic by minimizing software interruptions and data transfer and it is more precise by reducing noise due to ASIC operation.

Electronics for the far-forward CMS muon detector upgrade, ME0

With the High Luminosity upgrade of the Large Hadron Collider (LHC) we expect increased instantaneous luminosities up to 7.5 × 1034 cm−2 s−1, or five times more than the original values. In order to maintain performance of the Compact Muon Solenoid (CMS) experiment under these conditions, ME0 is one of three new muon sub-detectors being added, along with GE1/1 and GE2/1, which use the triple Gas Electron Multiplier (GEM) technology. ME0 is designed to cover the forward region of 2.0 < |η| < 2.8, thus improving muon reconstruction at high background rates by supplementing other overlapping muon subsystems up to |η| = 2.4, while also extending the acceptance for the first time to |η| = 2.8. The readout electronics for ME0 must be designed to accommodate high data rates and be sufficiently radiation hard to operate close to the beamline. The Optohybrid (OH) board for ME0, which reads out data from the front-end VFAT3b ASICs, has therefore been designed to operate without an FPGA (unlike GE1/1 and GE2/1) to ensure radiation hardness. The ME0 OH uses the radiation-hard CERN-designed lpGBT ASIC and VTRx+ optical transceiver module for high bandwidth optical links up to 10.24 Gb/s. The backend system is based on the ATCA standard. The design and development status of the readout electronics for ME0 is presented, along with recent results from integration tests performed using the first prototypes.

H2GCROC: Design and performance of a dedicated very front-end ASIC for SiPM readout of the CMS High Granularity Calorimeter

The HGCROC ASICs are dedicated very front-end electronics designed to read out the High Granularity Calorimeter (HGCAL), which will replace the present end-cap calorimeters of the Large Hadron Collider (LHC) for the Compact Muon Solenoid collaboration (CMS). The H2GCROC ASIC was especially designed to read out the SiPMs coupled to the scintillating tiles of the back hadronic sections, where the radiation constraints are less severe. Inside the chip, the front-end preamplifier is adapted for the SiPM’s higher signal level, expecting pC/MIP rather than fC/MIP ranges. The chip was received end of 2020 and extensively tested in the lab and test beam. This work examines the very front-end design and performance, including its performance with the sensor.