Fringing Capacitance Research Articles

HIGH RESOLUTION CAPACITIVE SENSOR FOR ACTIVE MAGNETIC BEARINGS

To obtain high precision rotation with active magnetic bearings, high resolution sensor are needed. From a literature study, finite element modeling and mathematical derivations, the electrostatic principle of fringe capacitance is investigated. It is used for the design of an optimized sensor pattern. For a fixed sensing area of 75 [(mm)^2], different fringe capacitances have been realized on flexible and rigid PCBs varying the distance between two conductors (from 0.1 to 0.3 [mm]) and the width of the conductors (also from 0.1 to 0.3 [mm]).

A physical frequency-dependent compact model for RF integrated inductors

A frequency-dependent compact model for inductors in high ohmic substrates, which is based on an energy point-of-view, is developed. This approach enables the description of the most important coupling phenomena that take place inside the device. Magnetically induced losses are quite accurately calculated and coupling between electric and magnetic fields is given by means of a delay constant. The later coupling phenomenon provides a modified procedure for the computation of the fringing capacitance value, when the self-resonance frequency of the inductor is used as a fitting parameter. The model takes into account the width of every metal strip and the pitch between strips. This enables the description of optimized layout inductors. Data from experiments and electromagnetic simulators are presented to test the accuracy of the model.

Sub-100 nm CMOS circuit performance with high- K gate dielectrics

In this paper we look at the effect of fringing fields on the circuit performance by use of high permittivity ( K) gate dielectrics in 70 nm CMOS technologies, from Monte-Carlo and mixed-mode simulations. Our results clearly show a decrease in the external fringing capacitance and an increase in the internal fringing capacitance, when the conventional SiO 2 is replaced by high- K gate dielectrics. It also indicates an optimum K value for a given technology generation in terms of circuit and device short-channel performance.

Charge based modeling of the inner fringing capacitance of SOI-MOSFETs

In this paper we focus on the quasi-static modeling of SOI-MOSFETs. First we discuss general considerations of charge based modeling in semiconductor devices. Advantages and disadvantages of charge based formulations will be discussed. Next a compact SOI model which has been developed by our group will be introduced. This model includes the description of the smooth transition between fully depleted and partially depleted operating modes. Utilizing this model a charge based formulation of the inner fringing capacitance in an SOI-MOSFET will be presented. Results of this new model will be compared to those gained by numerical device simulation.

Cut-off frequency and transit time analysis in short geometry polysilicon thin-film transistors

An accurate model for the drain characteristics, transconductance, cut-off frequency and transit time of a short geometry polysilicon thin film transistor (poly-Si TFT) is presented. An accurate threshold voltage and field dependent mobility are the key parameters in determining the above-threshold characteristics. The current-voltage characteristics of the device show an excellent agreement with experimental results. The transconductance for both linear and saturation regions is calculated and its variation with channel length, drain and gate voltages is studied. The total gate capacitance including the geometric capacitance and the fringing capacitance is also evaluated and simple closed form expressions for the cut-off frequency and transit time are obtained. A high cut-off frequency is achieved, which is important in realizing the device for millimetre and microwave frequency applications.

A methodology and model for the pull-in parameters of electrostatic actuators

This paper presents a generalized model for the pull-in phenomenon in electrostatic actuators with a single input, either charge or voltage. The pull-in phenomenon of a general electrostatic actuator with a single input is represented by an algebraic equation referred to as the pull-in equation. This equation directly yields the pull-in parameters, namely, the pull-in voltage or pull-in charge and the pull-in displacement. The model presented here permits the analysis of a wide range of cases, including nonlinear mechanical effects as well as various nonlinear, nonideal, and parasitic electrical effects. In some of the cases, an analytic solution is derived, which provides physical insight into how the pull-in parameters depend upon the design and properties of the actuator. The pull-in equation can also yield rapid numerical solutions, allowing interactive and optimal design. The model is then utilized to analyze analytically the case of a Duffing spring, previously analyzed numerically by Hung and Senturia, and captures the variations of the pull-in parameters in the continuum between a perfectly linear spring and a cubic spring. Several other case studies are described and analyzed using the pull-in equation, including parallel-plate and tilted-plate (torsion) actuators taking into account the fringing field capacitance, feedback and parasitic capacitance, trapped charges, an external force, and large displacements.

An antifuse EPROM circuitry scheme for field-programmable repair in DRAM

An antifuse EPROM and 3-V programming circuit has been demonstrated in an existing 0.22-/spl mu/m DRAM process technology and is fully compatible with 64-Mb SDRAM specifications. The antifuse circuitry uses an internal high-voltage generator for programming and a dynamic sense and static latch scheme that appropriately enables redundant DRAM address decoders at power-up. For efficient high voltage generation, a high-voltage-tolerant capacitor structure was formed by using the high fringing capacitance available between intralevel and interlevel polysilicon and metal lines. Furthermore, the programmable EPROM element was realized without any process modifications by utilizing destructive dielectric breakdown of the thin, highly reliable oxide-nitride-oxide (ONO) dielectric in the basic DRAM cell capacitor structure. This antifuse EPROM circuit enables implementation of field-programmable DRAM features such as memory repair, output impedance matching, and data encryption.

Verification of overlap and fringing capacitance models for MOSFETs

Parasitic capacitance and resistance limit the VLSI device performance. Hence, a circuit model is needed to treat these effects correctly. This article focuses on the circuit models for the overlap capacitance ( C gd,overlap) and the fringing capacitance ( C gd,fringe) of MOSFETs. Comparisons between the models and the device simulations are carried out for verification of the models. Also, a limitation of C gd,fringe model for a future device miniaturization is found based on SIA Road Map. We propose a modified C gd,fringe model. The effectiveness of the modified model is demonstrated using two circuits.

Tradeoff between interconnect capacitance and RC delay variations induced by process fluctuations

This paper describes the influence of the process fluctuations such as the critical dimension (CD) variation upon the interconnect capacitance C and RC delay. It is found that there is a tradeoff between C and RC delay variations because of the fringing capacitance. An interconnect design guideline to reduce C and/or RC delay variations is proposed. Also, C and RC delay variations for Cu interconnect are discussed.

A Multilevel Metal Interconnect Technology with Intra-Metal Air-Gap for Quarter-Micron-and-Beyond High-Performance Processes

AbstractA multilevel metal interconnect with air-gap has been developed to reduce RC delay time for quick turn-around-time foundry manufacturing. The air-gap method has been successfully applied to 0.25 νm foundry technology. Measurements on ring oscillators confirm that the smallest delay time is indeed achieved with the air-gap method, compared with that using either conventional high-density-plasma (HDP) oxide or low-dielectric-constant spin-on-glass (SOG). In addition, we have also developed fitting equations for the delay time, thus provide a handy method for predicting the RC delay time. The oscillator delay time is also found to be critically dependent on not only the size, but also the position of the air-gap. Best delay time reduction is obtained when the air-gap is positioned in extended both above and below the metal lines to effectively reduce the fringing capacitance.

Capacitance-voltage characteristics and cutoff frequency of pseudomorphic (AlGaAs/InGaAs) modulation-doped field-effect transistor for microwave and high-speed circuit applications

A two-dimensional analytical model for the capacitance–voltage characteristics of a pseudomorphic AlGaAs/InGaAs modulation-doped field-effect transistor is developed using charge-control analysis for its microwave frequency applications. The model includes the effect of various fringing field capacitances, and a cutoff frequency of 94.8 GHz is obtained for an L=0.25 μm device. The effect of traps has been included, which decreases the cutoff frequency. The results so obtained are compared with experimental data, and show excellent agreement, thereby proving the validity of the model. ©1999 John Wiley & Sons, Inc. Microwave Opt Technol Lett 23: 312–318, 1999.

A Multilevel Interconnect Technology with Intrametal Air Gap for High-Performance 0.25-µm-and-Beyond Devices Manufacturing

A multilevel interconnect technology with an intra metal air gap has been developed to reduce the interconnect delay time for versatile, and quick turnaround-time foundry manufacturing. The air-gap method has been successfully applied to 0.25 µm IC technology and shown to be effective in reducing the parasitic interconnect capacitance. Measurements of various ring oscillators confirm that the smallest delay time is indeed achieved with the air-gap method, compared with other methods using either conventional high-density-plasma (HDP) oxide or low-dielectric-constant spin-on-glass (SOG) as the gap-filling insulating materials. Moreover, the oscillator delay time is found to depend critically on not only the size of the air gap, but also the position of the air gap. Best results in terms of delay time reduction are obtained when the air-gap is positioned in the middle between the two metal lines, and extends both above and below the metal lines to effectively reduce the fringing capacitance. We have also measured the leakage current between adjacent metal lines and confirmed that our new metal interconnect structure with an air gap does not exhibit any appreciable leakage and appears to be suitable for high-performance foundry applications. Lastly, the polarization and thermal characteristics of the air-gap structure were compared with conventional gap-filling methods.

A new analytical model to determine the drain-sourceseries resistance of FOLD MOSFET

An analytical model to determine the intrinsic drain-source series resistance of a fully overlapped lightly doped drain (FOLD) MOSFET is presented. Considering outer and inner fringing capacitances and the depletion of the n- surface caused by the normal electric field from the gate, I-V characteristics, transconductance, drain conductance, channel resistance, cut-off frequency and transit time are studied. It is shown that, because of the lesser parasitic resistance of the FOLD structure, the device provides higher current driving ability than the lightly doped drain and can suppress hot carrier degradation by avoiding degradation due to the depletion of the n- region by electrons trapped in the sidewall. Some of the predictions of the model are verified with experimental data.

Cut off frequency and transit time analysis of lightly doped drain (LDD) MOSFETs

Analytical model for the transconductance, cut off frequency, transit time and fringing capacitance of LDD MOSFETs is presented with a simple approach. The analysis is carried out considering the LDD device as a conventional MOSFET with a series resistance [Z.-H. Liu et al., Threshold voltage model for submicrometer MOSFETs. IEEE Trans Electron Devices 1993; ED-40: 86–94] and a simple closed form expressions for cut off frequency and transit time is obtained. The total gate capacitance, i.e. the geometric and fringing capacitance, is calculated for both LDD and non-LDD devices and lower fringing capacitance is reported in LDD devices. Lower cut-off frequencies and higher transit time are reported in LDD devices for the same channel length.

The in-process surface roughness measurement using fringe field capacitive (FFC) method

The problem of the in-process roughness control is of special importance in case of the finishing process. The analysis of the metrological features methods and the preliminary investigation have shown that the FFC method offers the greatest hope for its implementation into the in-process roughness control. The theoretical and experimental research of fringe field capacitance method for use to the in-process roughness control have been conducted at the Warsaw University of Technology. The measuring signal obtained from FFC-based devices for the measuring system is a function of the surface average height of roughness and of the bearing ratio distribution for non-filtered profile. The capacitance method enables the in-process roughness control of surfaces (Ra>0, 1 μm) revolving with high speeds. It is not sensitive to the type of material and is susceptibility to the influence of the working liquid and other disturbances is very low.

A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation

This paper describes fringing and coupling interconnect capacitance models which include the nonlinear second-order effects of field interactions among multilevel parasitic interconnects for accurate circuit simulations. They are fitted well with numerical solutions by using a Poisson equation solver. A reliable parasitic distributed resistance-inductance-capacitance (RLC) extraction method is identified by using the solver with the bounded local three-dimensional (3-D) numerical analysis to reduce excessive central processing unit (CPU) time compared to full 3-D numerical simulation. We investigate the impact of input slew variations on the traversal clock delay within the slow ramp region of the driver gate as well as in the extracted parasitic interconnect networks. Input slew is found to be a dominant factor affecting clock delay sensitivity. In addition, we use indirect on-chip electron beam probing to confirm that the simulated clock delays are in reasonable agreement with the measured delays.

Design and implementation of capacitive proximity sensor using microelectromechanical systems technology

This paper presents an innovative proximity sensor using microelectromechanical systems (MEMS) technology. The proximity sensor works on the principle of fringe capacitance. The target object does not need to be part of the measuring system and could be either a conductor or nonconductor. Modeling of the proximity sensor is performed and closed-form analytical solution is obtained for a ring-shaped sensing pattern. The proximity sensors could be batch fabricated using MEMS technology, and the fabrication process is relatively simple. Measurement of the prototype sensors revealed promising results. The size of the proximity sensor could vary from a few hundred micrometers to the size of the substrate. The flexibility on sensor size, sensing patterns, and sensing pattern geometrical parameters makes the sensor very versatile and capable of precision measurement of proximity in the range from micrometers to centimeters. The small size of the sensor makes it possible to surface mount the sensor in many space-constrained places. This advantage is vital in many areas, such as MEMS, microrobotics, precision engineering, machine automation, inspection tools, and many other applications. The ability of the proximity sensor in measuring relative permittivity of materials also finds the sensor useful applications in biomedical and tissue engineering. In addition, this micro proximity sensor is an ideal building block for many other types of sensors, such as force, tactile, and flow sensors.

New Methodologies for Characterization of Low Dielectric Constant Thin Films

AbstractNew methodologies are being developed in our laboratory that allow measurements of the Young's modulus (E) and thermal expansion coefficient (TEC) for materials that cannot be prepared as free standing films. The first employs a bending beam measurement of stress versus temperature. We measure the thermal stress of a given film on two substrates, Si and GaAs. The use of two substrates allows the determination of both E and TEC. A TEOS film is used to demonstrate the technique. Another technique is a variation of the stress-strain measurement of E. The brittle material of interest is coated onto a polymer substrate, and the composite film is elongated to obtain the stress-strain curve of the composite film. Subtraction of the polymer substrate contribution to this curve yields the stress-strain behavior of the brittle film and allows calculation of E.The in-plane dielectric constants of potential interlayer dielectrics (ILD) are determined from the interline capacitance between metal lines passivated with the material. We have developed a finite difference simulation to account for the fringe capacitance, and it allows the extraction of the in-plane dielectric constant from the measured capacitance. The method was used to measure the anisotropies in two polymer ILDs. A flexible chain polymer showed the same anisotropy in both a blanket film and on patterned lines, but a rigid rod-like polymer was found to be much less anisotropic on the patterned lines relative to the blanket film. This result indicates that the molecular orientation of the film is different on the patterned lines.

An empirical fringing capacitance dependent threshold voltage model for non-uniformly doped submicron MOSFETs

A simple and closed-form expression for the threshold voltage of non-uniformly doped submicron MOSFET is developed. The main features of this model are: (1) non-equipotential surface of the device which includes the non-uniformity effect along the channel; (2) charge screening effects to explain the weak substrate bias dependence for short channel devices; and (3) total gate capacitance of MOS structures (the geometric capacitance and the fringing capacitance which is calculated using the conformal transformation considering the effects of electrode thickness and lateral gate dimensions). Comparisons between the present model and experimental data show good agreement for a wide range of channel lengths and applied substrate biases.

An accurate gate length extraction method for sub-quarter micron MOSFET's

By comparing measured and simulated gate-to-source/drain capacitances, C/sub gds/, an accurate gate length extraction method is proposed for sub-quarter micron MOSFET's applications. We show that by including the 2-D field effect on the fringing capacitance, the polysilicon depletion and the quantum-well effects in the C/sub gds/ simulation, the polysilicon gate length, L/sub poly/, can be accurately determined for device lengths down to the 0.1 /spl mu/m regime. The accuracy of this method approaches that of cross-sectional TEM on the device under test, but without destroying the device. Furthermore, we note that as a result of accurate L/sub poly/ extraction, the source/drain lateral diffusion length, L/sub diff/, and effective channel length, L/sub eff/, can also be determined precisely. The accuracy of L/sub diff/ is confirmed by examining their consistency with experimentally obtained 2-D source/drain profile.