Sub-100 nm CMOS circuit performance with high- K gate dielectrics

Abstract

In this paper we look at the effect of fringing fields on the circuit performance by use of high permittivity ( K) gate dielectrics in 70 nm CMOS technologies, from Monte-Carlo and mixed-mode simulations. Our results clearly show a decrease in the external fringing capacitance and an increase in the internal fringing capacitance, when the conventional SiO 2 is replaced by high- K gate dielectrics. It also indicates an optimum K value for a given technology generation in terms of circuit and device short-channel performance.