Frequency-to-digital Converter Research Articles

An 11.36-Bit 405 μW SAR-VCO ADC with single-path differential VCO-based quantizer in 65 nm CMOS

In this paper, a low-power, small-area SAR-VCO ADC is proposed using a highly linear and single-path differential VCO-based quantizer. Compared to conventional digital solution or analog design, proposed digital synthesizable dynamic voltage comparator (DVC) employs a two-stage structure, which reduces the comparator delay and offset and saves chip area. Furthermore, improved differential voltage-to-current (V–I) converter enables the realization of a single-path differential VCO-based quantizer. Trimming circuits enhance the robustness of VCO, compensating for variations induced by process variations. Additionally, a novel frequency-to-digital converter (FDC) is used as the fine quantization to directly measure the frequency. Finally, a SAR-VCO ADC is realized in 65 nm CMOS process. The simulation results show that the signal-to-noise distortion ratio (SNDR) is 70.16 dB under sampling rate of 7.8 MHz at oversampling rate (OSR) of 8. The proposed ADC has a supply voltage of 1.2V and a power consumption of 405 μW. It occupies an area of 0.16 mm2, and achieves an area figure of merit (FoMA) of 25.12 fJ*mm2/conversion-step.

Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra-Low-Voltage VCO-Based ADCs

A frequency-to-digital converter (FDC) performs the role of precise frequency digitization within a voltage-controlled oscillator (VCO)-based ADC. To be compatible with energy-harvesting (EH) Internet-of-Things (IoT) devices, the development of ultra-low-voltage (ULV) FDCs is crucial, where the primary focus must be directed towards the maximization of data throughput under dramatic constraints of reliability and timing variability associated with deep-subthreshold operation. This article investigates the speed maximization of a 0.2V full-custom ULV FDC design, consisting of an array of several parallel XOR-based FDC units, and the multi-rate decimation-filtering digital back-end. At the core of this broad exploration is a high-speed sense-amplify phase sampler (PS) featuring hardware redundancy, capable of sampling the phase of low-voltage-swing inputs. Particular focus is placed on the yield-based reliability-driven design methodology for the sense-amplify phase-sampling circuits running up to 40MS/s and practical variability-mitigation strategies. To overcome the speed bottleneck in the digital back-end, a fully parallel bitstream-processing architectural composition of the computations for summation and decimation are proposed. Experimental verification through measurements of the FDC integrated within a 10-bit 160kHz bandwidth (BW) open-loop VCO-based ADC across clock frequency with supply variations demonstrate robust operation of the first 0.2V multi-phase FDC in the advanced 28nm CMOS process.

An all-digital CMOS temperature sensor with a wide supply voltage range

This paper proposes a MOSFET-based all-digital temperature sensor fabricated in a standard 55-nm CMOS process. The temperature sensing elements of the sensor are composed of ring oscillators, which convert temperature information into frequency information. The frequency ratio’s proportional to absolute temperature (PTAT) feature is generated by using two separate frequency oscillators with varied temperature sensitivity. The frequency-to-digital converter (FDC) converts frequency information into digital representation without introducing any overhead reference clock. A die area of 1915µm2 is occupied, owing to the all-digital architecture. After two-point calibration, the proposed sensor achieves an error of -0.4°C∼+0.6°C throughout a temperature range of -40°C∼125°C. With the help of class-adjustable oscillators, the sensor can function in a wide supply voltage range from 0.5V to 1.2V. It obtains a resolution of 0.166°C at room temperature with a dissipation of 2.5µW.

A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL

This article presents a wide input-range delay chain based time amplifier (TA) and its application to a 6.5-GHz digital fractional- N phase-locked loop (PLL). The TA includes a delay-averaging linearity enhancement technique and the PLL is based on an improved dual-mode ring oscillator (DMRO) delta-sigma (ΔΣ) frequency-to-digital converter (FDC). The TA mitigates contributions to the PLL's phase noise from DMRO flicker noise, which would otherwise degrade the PLL's in-band phase noise, and from ΔΣ FDC quantization error, which would otherwise degrade the PLL's phase noise at high bandwidth settings. This paper also presents a delay-free asynchronous DMRO phase sampling scheme, and the first experimental demonstration of a recently-proposed ΔΣ FDC digital gain calibration technique. The TA-assisted PLL achieves a random jitter of 145 fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , a total jitter that ranges from 151 to 270 fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> as a result of fractional spurs, and a worst-case fractional spur of -49 dBc without requiring nonlinearity calibration.

A 5GHz Digital Fractional- $N$ PLL Using a 1-bit Delta–Sigma Frequency-to-Digital Converter in 65 nm CMOS

A highly digital two-stage fractional- $N$ phase-locked loop (PLL) architecture utilizing a first-order 1-bit $ \Delta \!\Sigma $ frequency-to-digital converter (FDC) is proposed and implemented in a 65nm CMOS process. Performance of the first-order 1-bit $ \Delta \!\Sigma $ FDC is improved by using a phase interpolator-based fractional divider that reduces phase quantizer input span and by using a multiplying delay-locked loop that increases its oversampling ratio. We also describe an analogy between a time-to-digital converter (TDC) and a $ \Delta \!\Sigma $ FDC followed by an accumulator that allows us to leverage the TDC-based PLL analysis techniques to study the impact of $ \Delta \!\Sigma $ FDC characteristics on $ \Delta \!\Sigma $ FDC-based fractional- $N$ PLL (FDCPLL) performance. Utilizing proposed techniques, a prototype PLL achieves 1 MHz bandwidth, −101.6 dBc/Hz in-band phase noise, and $ {\textrm {1.22 ps}_{\textrm {rms}}}$ (1 kHz–40 MHz) jitter while generating 5.031GHz output from 31.25MHz reference clock input. For the same output frequency, the stand-alone second-stage fractional- $N$ FDCPLL achieves 1MHz bandwidth, −106.1dBc/Hz in-band phase noise, and $ {\textrm {403 fs}_{\textrm {rms}}}$ jitter with a 500MHz reference clock input. The two-stage PLL consumes 10.1mW power from a 1V supply, out of which 7.1 mW is consumed by the second-stage FDCPLL.

A Linearized Model for the Design of Fractional-&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$N$&lt;/tex&gt;&lt;/formula&gt; Digital PLLs Based on Dual-Mode Ring Oscillator FDCs

A digital fractional- N phase-locked loop (PLL) frequency synthesizer based on a second-order ΔΣ frequency-to-digital converter (FDC) without conventional analog components was recently proposed and demonstrated experimentally to have performance in line with state-of-the-art analog PLLs. However, unlike analog PLLs or prior PLLs based on second-order ΔΣ FDCs, it is highly digital and does not require an analog charge pump or ADC, so it is well-suited to implementation in highly-scaled CMOS technology. This paper derives a linearized model of the new architecture and key equations which are necessary for the design of PLLs based on the architecture.

A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO

This paper presents the first published fully-integrated digital fractional- N PLL based on a second-order frequency-to-digital converter (FDC) instead of a time-to-digital converter (TDC). The PLL's quantization noise is nearly identical to that of a conventional analog delta-sigma modulator based PLL (ΔΣ-PLL). Hence, the quantization noise is highpass shaped and is suppressed by the PLL's loop filter to the point where it is not a dominant contributor to the PLL's output phase noise. However, in contrast to a ΔΣ-PLL, the new PLL has an entirely digital loop filter and its analog components are relatively insensitive to non-ideal analog circuit behavior. Therefore, it offers the performance benefits of a ΔΣ-PLL and the area and scalability benefits of a TDC-based digital PLL. Additionally, the PLL's digitally controlled oscillator (DCO) incorporates a new switched-capacitor frequency control element that is insensitive to supply noise and parasitic coupling. The PLL is implemented in 65 nm CMOS technology, has an active area of 0.56 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , dissipates 21 mW from 1.0 and 1.2 V supplies, and its measured phase noise at 3.5 GHz is -123, -135, and -150 dBc/Hz at offsets of 1, 3, and 20 MHz, respectively. The PLL's power consumption is lower than previously published digital PLLs with comparable phase noise performance.

A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-μm 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are 400 × 450 μm2 and 6 mW, respectively.

A 1.9–3.8 GHz $\Delta \Sigma$ Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency

A fast and high-precision all-digital automatic calibration circuit that is highly suited for ΔΣ fractional-N synthesizers is designed to achieve a constant loop bandwidth and fast lock time over an octave tuning range. A high-speed frequency-to-digital converter (FDC) measures VCO frequency on-chip with a sub-fREF frequency resolution of fREF/k in a time period of k·TREF. The on-chip detected VCO frequency is then used for calibrating the loop bandwidth and the VCO frequency. The loop bandwidth calibration circuit measures the VCO gain KVCO and uses it to precisely control the charge pump current, hence making the loop bandwidth constant. For the VCO frequency calibration, a minimum error code finding block significantly enhances the calibration accuracy by finding the truly closest code to the target frequency. Moreover, this method does not need to activate ΔΣ modulator to achieve sub- fREF calibration resolution, which makes this technique much accurate and faster than the conventional ones. A 1.9-3.8 GHz ΔΣ fractional-N synthesizer is implemented in 0.13 μm CMOS, demonstrating that the loop bandwidth calibration is completed in 1.1-6.0 μs with ±2% accuracy and the VCO frequency calibration is completed in 1.225-4.025 μs, all across the entire octave tuning range.

Design Considerations for Autocalibrations of Wide-BandΔΣFractional-NPLL Synthesizers

Autocalibration of VCO frequency and loop gain is an essential process in PLL frequency synthesizers. In a wide tuning-range fractional-NPLL frequency synthesizer, high-speed and high-precision automatic calibration is especially important for shortening the lock time and improving the phase noise. This paper reviews the design issues of the PLL auto-calibration and discusses on the limitations of the previous techniques. A very simple and efficient auto-calibration method based on a high-speed frequency-to-digital converter (FDC) is proposed and verified through simulations. The proposed method is highly suited for a very wide-bandΔΣfractional-NPLL.

Innovative frequency measurement technique used in the design of a single channel frequency to digital converter ASIC

The frequency to digital converter (FDC) is an application specific integrated circuit (ASIC). The chip has been designed to handle one input channel but can easily be expanded to handle multiple channels of frequencies. The channel is capable of measuring frequencies from 100 Hz to 100 kHz. The power consumption of the chip is very low. The frequency measurement accuracy is better than 0.1%. The conversion rate per channel is 100 samples which can be varied too. The chip has built in test equipment (BITE) to verify its operation. It is able to generate frequencies like 8, 4, 2 and 1 MHz which can be fed as optional clock frequencies depending on the accuracy desired. The FDC chip can be interfaced to a 16 bit bus. To meet these stringent specifications of the FDC chip an innovative frequency measurement technique has been devised called the hybrid technique of frequency measurement. The technique proves to be very accurate and it is found that by varying the sampling rate the range of input frequencies over which this accuracy can be achieved also changes. The specifications are particularly strict so that it is possible to use the chip for any military application for which a very reliable operation is demanded. The FDC chip is hence ideal for control and guidance purposes. The chip has wide ranging applications. In conjunction with sensors such as accelerometers it can be used to design smart sensors. The chip can play a vital role in engine controllers and in pressure measurements using vibration type transducers. Sometimes to isolate (galvonic) transducers, the output is converted to frequency and isolation is achieved using opto-isolators; then by measuring the frequency using this chip this can be converted to digital information.