Frequency Shift Keying Receiver Research Articles

A Low Power Frequency Tunable FSK Receiver Based on the N-Path Filter

This brief presents a low power frequency tunable frequency shift keying (FSK) receiver based on N-path filter. The N-path filter serves as the first stage of the receiver and converts the frequency difference between two tones to amplitude difference. To evaluate the maximum achievable data rate of the proposed receiver, we studied the behavior of N-path filter under two-tone input condition. With linear periodically time-variant theory, the equations for transient response between two tones are derived for differential two-port N-path filters and verified by the simulation. Based on the analysis, an optimum data rate is obtained for the proposed N-path filter-based FSK receiver. Implemented in 0.13- $\mu \text{m}$ CMOS process, the chip occupies 300 $\times700\,\,\mu \text{m}^{2}$ , achieves data rate of 2.5 Mb/s, and 74 pJ/bit energy per bit at −65 dBm sensitivity. Frequency tuning is also demonstrated.

Area efficient SDR receiver without and with dynamic partial reconfiguration

Dynamic partial reconfiguration (DPR) technique is a very efficient for low-cost field programmable gate array (FPGA) for realising several application categories like signal processing. The present work demonstrates a generic framework for implementing Software Defined Radio (SDR) based communication system using DPR. The work switches contexts with two partial reconfiguration blocks. Namely spectrum estimation and frequency shift keying (FSK) receiver blocks. The former uses the streaming type fast Fourier transform (FFT) and later uses frequency shifting and filtering stages. The completely developed FSK receiver is simulated using Modelsim. Xilinx Zynq 7010 SoC with DPR is used for implementation. An FSK signal with symbol rate 64 Kbps is used to drive the analogue to digital converter (ADC) input. The work demonstrates novel direction for SDR implementation with DPR for low-area FPGAs. The results shows 45% lesser FPGA-DSP48 slices are used compared to without-DPR. Reduced power dissipation is observed as by-product.

Area efficient SDR receiver without and with dynamic partial reconfiguration

Dynamic partial reconfiguration (DPR) technique is a very efficient for low-cost field programmable gate array (FPGA) for realising several application categories like signal processing. The present work demonstrates a generic framework for implementing Software Defined Radio (SDR) based communication system using DPR. The work switches contexts with two partial reconfiguration blocks. Namely spectrum estimation and frequency shift keying (FSK) receiver blocks. The former uses the streaming type fast Fourier transform (FFT) and later uses frequency shifting and filtering stages. The completely developed FSK receiver is simulated using Modelsim. Xilinx Zynq 7010 SoC with DPR is used for implementation. An FSK signal with symbol rate 64 Kbps is used to drive the analogue to digital converter (ADC) input. The work demonstrates novel direction for SDR implementation with DPR for low-area FPGAs. The results shows 45% lesser FPGA-DSP48 slices are used compared to without-DPR. Reduced power dissipation is observed as by-product.

A Low‐Power Low‐Cost 780MHz CMOS FSK Receiver for Short‐Range Wireless Communication

This paper presents a low-power low-cost 780MHz CMOS Frequency shift keying (FSK) receiver for short-range wireless communication. A current-reused Low power amplifier (LNA) and a single-balance passive mixer are employed to cut down the current consumption of the RF frontend in receiver. A 3rd -order active-RC complex filter with reconfigurable bandwidth is implemented and a novel automatic tuning circuit is used in the filter to eliminate the negative effect of the Process, voltage, temperature (PVT) variations. A novel replica-circuit master-slave automatic tuning circuit and a discrete-time differentiator are employed in demodulator to keep the demodulation performances from the PVT variations and the frequency offset of Intermediate frequency (IF). The receiver is fabricated in 0.18µm CMOS and occupies a chip area of about 0.97mm2. It can achieve a sensitivity of –83.7dBm and a tolerance of IF range from 1.5MHz to 3.7MHz with a 4.7mA current consumption under a 1.8V supply.

Low Power FSK Receiver Using an Oscillator-Based Injection-Locked Frequency Divider

This letter presents a novel frequency-shift keying (FSK) receiver using an oscillator-based injection-locked frequency divider (ILFD), thereby achieving high sensitivity, low dc-offset, and low power consumption. The proposed receiver comprises a low-noise amplifier, a divide-by-2 ring-oscillator-based ILFD, and a subharmonic mixer. Moreover, the proposed receiver is fabricated using 0.18 μm CMOS process and consumes 1.1 mW. Measurement results demonstrate that the proposed receiver has a sensitivity of -83 dBm at 10-3 bit error rate with 1 Mb/s data rate in receiving a 2.4 GHz Gaussian FSK signal.

The Design and Implement of a Receiver for FSK Signal

A novel frequency shift keying (FSK) receiver is presented, including receiving antennas, a low noise amplifier (LNA), band-pass filters (BPF) and a novel all-digital 2-level FSK demodulator. The Matlab simulation results of the all-digital FSK demodulator show that it can improve bit error ratio (BER) performance compared with pseudo-coherent FSK demodulation (PCFSK). The novel FSK demodulator defined using Verilog HDL is easy to be implemented on Field Programmable Gate Array (FPGA) and in CMOS integrated circuit. The whole FSK receiver designed and implemented on a PCB board can receive FSK signal and send the recovered data to computer through RS-232 interface.

Highly-sensitive coherent optical detection of M-ary frequency-shift keying signal

We demonstrate M-ary frequency-shift keying (FSK) optical modulation and digital coherent detection, aiming at applications to space communications, where high receiver sensitivity is the most crucial consideration. The proposed FSK transmitter and receiver are based on the coherent orthogonal frequency-division multiplexing (OFDM) technique and feature simple configuration and low computational complexity. By offline bit-error rate measurements using a 256-FSK signal without the forward error-correction code, we obtain the receiver sensitivity as high as 3.5 photons per bit at the bit-error rate of 10(-3). The experimental result is in good agreement with simulations.

A low-power all-digital FSK receiver for space applications

A frequency-shift keying (FSK) receiver has been designed for deep space applications which exhibits potential for ultra low power performance. The receiver is based on a novel, almost all-digital architecture. It supports a wide range of data rates and is very robust against large and fast frequency offsets due to Doppler. The architecture utilizes subsampling and 1-bit data processing together with a discrete Fourier transform-based detection scheme to enable power consumption dramatically lower than implementations reported in the literature. Novel and power-efficient algorithms are derived for frequency and timing tracking. Most of the power saving techniques are applicable to a variety of applications, but some are achieved by taking advantage of the asymmetric power constraints for the receiver and the transmitter as well as the absence of adjacent channel interferers. The worst-case bit-error rate (BER) performance of the receiver is just 2.5 dB below that of the optimal uncoded noncoherent FSK receiver at a BER of 10/sup -6/ and better for lower BERs.

VLSI implementation of a 100-μW multirate FSK receiver

A very low-power frequency-shift keying (FSK) receiver has been designed for dual-purpose operation: deep space applications and general purpose baseband processing. The receiver is based on a novel, almost all-digital architecture. It supports a wide range of data rates and is very robust against large and fast frequency offsets due to Doppler effects. The architecture utilizes subsampling and l-b data processing together with an FFT-based detection scheme to enable power consumption dramatically lower than a conventional implementation., A system/hardware co-design approach allows the use of a number of circuit-level power reduction techniques while still meeting system-level constraints. In particular, we designed a combination of fully parallel and word-serial decimation stages to simultaneously optimize power consumption and silicon area. We also designed a very efficient FFT block that uses approximate arithmetic and pruning to greatly reduce overall complexity. Additional modules, such as direct digital frequency synthesizer (DDFS) and magnitude computation, have also been optimized in view of the targeted system parameters: signal-to-noise ratio and bit-error rate. The entire architecture has been made maximally flexible and power efficient by utilizing local clock gating and simple interstage, handshaking mechanism. The receiver has been implemented in 0.25-/spl mu/m CMOS technology and takes up under 1 mm/sup 2/. The power consumption is below 100 /spl mu/W for data rates below 20 kb/s. Rates up to 2 Mb/s are supported.

Non-coherent FSK receiver for underwater communications

The detection process in underwater communications suffers from a severe degradation in reception due to the existence of fast multipath fading during transmission. Several non-coherent frequency shift keying (FSK) receivers have been proposed to alleviate this problem. However, each receiver is seen to work properly only in certain environmental conditions. A new non-coherent FSK receiver has been developed, based on the utilization of low-order models of parametric spectral estimation. The proposed receiver is found to outperform existing receivers in realistic fading conditions. Simulation results are included to support this claim.

Error probabilities of fast frequency-hopped FSK with self-normalization combining in a fading channel with partial-band interference

Error probability analysis is performed for a binary orthogonal frequency-shift-keying (FSK) receiver using fast frequency-hopped (FFH) spread-spectrum waveforms transmitted over a frequency-nonselective slowly fading channel with partial-band interference. Diversity is performed using multiple hops per data, bit. A nonlinear combination procedure referred to as self-normalization combining is used by the receiver to minimize partial-band interference effects. Diversity is found to completely negate degradation of the self-normalized receiver caused by partial-band interference and offers definite receiver performance improvement when the direct signal component is weak. The self-normalized receiver is sensitive to fading channels. For severe channel fading, the performance of a conventional noncoherent binary FSK receiver is generally either equivalent or superior to that of the self-normalized receiver.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Theoretical analysis of phase diversity optical homodyne receiver with FSK demodulation

A detailed analysis of optical coherent phase diversity single-filtered and dual-filtered frequency-shift keying (FSK) receivers corrupted by shot and phase noise is presented. With delay and cross-product detection, the effect of various parameters, including bandwidths of filters, delay time, frequency deviation and noises, are investigated. The tolerance of phase noise is quite large, when small time delay in the demodulator and appropriately large frequency deviation is selected. It is also shown that there exists an optimal bandwidth for the first filter in the dual-filtered FSK receiver. For a total linewidth equal to half of the bit rate, the power penalty incurred (at BER=10/sup -9/) is 1.92 dB when the modulation index is 4, provided that an optimal filter bandwidth and a frequency deviation-delay product of 0.25 are used.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analytical and practical evaluation of diversity penalties in multi-bit-rate coherent FSK systems

Fully analytical expressions are presented for calculating the bit-error-rate (BER) and sensitivity penalties in frequency-shift-keying (FSK) receivers with noncoherent square-law IF detection. With these results one can directly compute the sensitivity and diversity penalties as a function of the IF filter bandwidth. Postdetection filtering is included in the analysis. The BER of such receivers can be expressed in terms of a sum of generalized Laguerre polynomials, which can easily be evaluated. This yields relations between the IF bandwidth expansion factor and the sensitivity that can be applied directly for practical system analysis. This is illustrated using the results from a coherent multi-bit-rate, multichannel FSK receiver, which was used at bit rates of 140 and 560 Mb/s. The discrepancy between theory and practice is less than 0.15 dB for diversity penalties and 0.4 dB for the bit rate penalty. >

Performance analysis of polarization-insensitive phase diversity optical FSK receivers

A polarization-insensitive phase-diversity optical frequency-shift-keying (FSK) receiver is proposed, and its performance is evaluated. The basic model and signal processing formulation are developed to describe the functions and features of this receiver. Two different approaches (one of which is an upper bound) are used to treat the mixed noise terms, and Gaussian approximation is employed to estimate the receiver performance in terms of the laser linewidth, the modulation index, and the filter bandwidth. The virtually polarization-insensitive property is also verified. As an example, numerical results are presented for a 150-Mb/s receiver, which show that the difference between the upper bound and the other approximation is about 2 to 3 dB. It is also shown that the receiver with small modulation index is less tolerant of the linewidth so that an error floor may appear. When the modulation index is large, the receiver can tolerate linewidths comparable with the bit rate. >

A fully integrated low-power FSK receiver for VHF and UHF paging

The author introduces a very sensitive, highly integrated UHF paging receiver which is based on the offset-receiver principle and is fully compatible with all FSK (frequency-shift-keying) modulated systems (512 b/s and 1200 b/s). The IC is fabricated using an advanced bipolar UHF process, has a typical current consumption of only 3 mA at 2-V supply voltage, and is in a 28-pin SO (small outline) package for automated assembly. Test results are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Extremely Low Frequency (ELF) Communication to Submarines

An ELF (extremely low frequency) communication system has been proposed for communication from land to submerged submarines. We present an analytical study of conceptual feasibility of such a system and discuss some of its properties. We find no fundamental technical reason why such a system is infeasible. The present work yields the general structure of the receiver, and estimates for the important parameters of such a system. Nonlinear processing ahead of the FSK (frequency-shift keying) receiver in the submarine appears essential. Such processing greatly reduces the effects of atmospheric noise due to nearby lightning storms, and hence, makes reliable operation possible at much smaller transmitter power.

The Performance of a Noncoherent FSK Receiver Preceded by a Bandpass Limiter

Many applications of the bandpass limiter involve either coherent or noncoherent demodulation following the limiter. In this paper we study the performance of a noncoherent frequency-shift keying (FSK) receiver when it is preceded by a bandpass limiter. In particular, we obtain expressions for signal suppression- factor, output signal-to-noise ratio (SNR), and error probability from which one can assess the degradation in performance of the receiver due to the presence of the limiter. Both narrow-band and wide-band cases are treated thus covering situations where no frequency uncertainty exists (i.e., known carrier frequency) as well as large-frequency uncertainties. Also discussed is the first-order signal plus noise probability density function (pdf) following noncoherent demodulation.

Bounds on the error probability of FSK and PSK receivers due to non-Gaussian noise in fading channels

This paper derives upper and lower bounds on binary error probability as a function of signal-to-noise ratio for several digital data systems operating over a complex Gaussian fading channel. Bounds of varying degrees of tightness are obtained by placing certain physically meaningful constraints on the allowable detected noise probability distributions. Detailed derivations are given for bounds corresponding to constraints on the "crest-factor" of the detected noise and on the ratio of peak noise power to average signal power. The calculations include the effects of diversity corn-billing and are applicable to frequency-shift keying (FSK), binary and quaternary phase-shift keying (PSK) using a pilot tone as reference, and binary and quaternary PSK using the previous signaling element as a phase reference. It is an interesting result of this paper that for moderate noise crest factors the upper and lower bounds can be rather close. In the particular case of nondiversity operation, for example, the lower bound actually becomes approximately equal to the upper bound at SNR's of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">30</tex> dB or greater for noises with a crest factor as high as <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">20</tex> dB.