Frequency Detector Research Articles

A random pulse modulation approach to modeling the flicker and white noise of the charge pump of a fractional‐N frequency synthesizer

SummaryFlicker noise and white noise from the charge pump (CP) within a phase locked loop (PLL) are key contributors to the close‐in phase noise floor of a fractional‐N frequency synthesizer. The pulse train from the phase frequency detector imposes different types of random pulse modulation on the up and down current sources, which causes different modulation effects to the flicker and white noises at low frequency. This paper rigorously analyzes the underlying noise random modulation mechanisms for the system operating in integer‐N and fractional‐N modes. Transient noise simulation using Verilog‐A behavioral modeling followed by power spectrum analysis is applied to support the mathematical analysis of the random noise modulation.

A Wide-Range FD for Referenceless Baud-Rate CDR Circuits

A wide-range frequency detector (FD) is presented for baud-rate clock and data recovery (CDR) circuits. It achieves a wide frequency capture range, a short lock time, and a low power. By using this FD, a referenceless quarter-rate CDR circuit with a one-tap decision feedback equalizer is fabricated in 40-nm CMOS technology. The active area of this CDR circuit is 0.0999mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and its power is 44mW while the data rate is 16.8Gbps. The calculated energy efficiency of this CDR circuit is 2.62pJ/b.

A Fast Background Frequency Calibration Based on Intermittent Frequency Locked Loop for the Super-Regenerative Receive

The conventional phase-locked loops or frequency-locked loops should take time to calibrate the oscillator’s resonant frequency in a super-regenerative receiver (SRR) and severely disrupts the receiver’s operations. This paper proposes a novel intermittent frequency locked loop (IFLL) as a frequency synthesizer to continuously maintain the resonant frequency equal to the preset target frequency without interruption to the SRR. An analog loop mainly composed of a time-register-based frequency detector and a charge pump is proposed to achieve precise frequency detection during each SRR’s quenching period regardless of the inevitable initial phase error, and adjust SRR’s resonant frequency accordingly. An average fractional division scheme is adopted to improve IFLL’s frequency resolution to the level of the quenching frequency. The operations of the IFLL are analyzed with the z-domain transfer function, including the stability and frequency response. A prototype is built and tested. The measurement results show that the proposed IFLL only needs a calibration cycle of fewer than 50 μs to adjust SRR’s resonant frequency without interruption against its receiving. The real-time frequency error after calibration is smaller than 70 kHz. SRR opposes a sensitivity of -61.2 dBm @ 200 kbps and a 3-dB bandwidth of 2.2 MHz.

A 1.68–23.2-Gb/s Reference-Less Half-Rate Receiver With an ISI-Tolerant Unlimited Range Frequency Detector

This paper presents a reference-less half-rate receiver with an unlimited range frequency detector (URFD) for 13.8X continuous rate operation. To tolerate channel loss induced inter-symbol interference (ISI), the receiver is integrated with a continuous time linear equalizer (CTLE) and a 2-Tap decision feedback equalizer (DFE) on the same chip. Incorporating with the novel pulse width based URFD, the date rate of the receiver is limited by the frequency tuning range of the voltage-controlled oscillator (VCO). The energy efficiencies of the whole receiver and clock data recovery (CDR) are about 2.39 and 0.97 pJ/bit respectively. Implemented in a TSMC 28-nm CMOS process, the active area is 0.056 mm.

A linear range extension phase frequency detector and charge pump for frequency hopping acceleration and cycle slips elimination

AbstractThis paper presents a phase‐locked loop (PLL) with a novel phase frequency detector (PFD) and charge pump (CP) which can extend the linear phase difference detection range and eliminate cycle slips. Thus, the frequency settling time can be effectively reduced compared with the conventional PFD and CP during the frequency acquisition process. The proposed PLL with linear range extension PFD and CP (LEPFD/CP) is designed in 180 nm BiCMOS technology and occupies 3.61 mm2 area. As the LEPFD/CP is disabled when the PLL is locked, the PLL is robust enough and the extra power consumption can be ignored. The measurement results show that a 50 MHz reference frequency acquisition process with 10 μs has been accelerated 3.7 times compared with the conventional PFD/CP PLL with the same 200 kHz loop bandwidth.

Design and Implementation of High Frequency and Low-Power Phase-locked Loop

Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.

Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology

A novel phase frequency detector is designed which is made up of 16 transistors whereas conventional is of 48 transistors. This paper also presented the design of charge pump circuit and current starved VCO (CSVCO). These are the critical blocks that are widely used for applications like clock and data recovery circuit, PLL, frequency synthesizer. The proposed PFD eliminates the reset circuit using pass transistor logic and operates effectively at higher frequencies. The circuits are designed using Cadence Virtuoso v6.1 in 45nm CMOS technology having supply voltage 1V. It was found that the power consumption of PFD is 138.2 nW which is significantly lesser than other designs. CSVCO also analysed at operating frequency of 10 MHz to give output oscillation frequency of 1.119 GHz with power dissipation of 18.91 μW. Corner analysis done for both the PFD and CSVCO for various process variations. Monte Carlo analysis also done for the proposed PFD and presented CSVCO to test the circuit reliableness.

An oscillation damping method for frequency-detector-less virtual synchronous generators

This paper presents an active power oscillation damping method for frequency-detector-less virtual synchronous generator (VSG) to enhance its transient stability and to avoid the ill effect of frequency detector. In the paper, first, the mechanism and the low-frequency oscillation model of a conventional VSG is derived and reduced to a second-order model. Then, a new way to obtain the damping power without using frequency detector is proposed in order to simplify the conventional one, which includes frequency detector. The new approach presents an equivalent third-order model, and based on small-signal state-space analysis, the dominant poles are assigned to the same place as the original one, so that we can fairly compare their dynamic performances. Finally, experimental results are performed to compare the proposed approach with some other VSG control methods. The experimental results show that the proposed approach does better in transient stability and power-sharing ability than other conventional VSG control methods.

Developing neural network model for predicting cardiac and cardiovascular health using bioelectrical signal processing

Coronary vascular disease (CHD) is one of the most fatal diseases worldwide. Cardio vascular diseases are not easily diagnosed in early disease stages. Early diagnosis is important for effective treatment, however, medical diagnoses are based on physician's personal experiences of the disease which increase time and testing cost to reach diagnosis. Physicians assess patients' condition based on electrocardiography, sonography and blood test results. In this research we develop classification model of the functional state of the cardiovascular system based on the monitoring of the evolution of the amplitudes of the first and second harmonics of the system rhythm of 0.1 Hz. We separate the signal to three streams; the first stream works with natural electro cardio signal, the other two streams are obtained as a result of frequency analysis of the amplitude- and frequency-detected electro cardio signal. We use sliding window of a demodulated electro cardio signal by means of amplitude and frequency detectors. The developed NN model showed an increase in accuracy of diagnostic efficiency by 11%. The neural network model can be trained to give accurate early detection of disease class.

Design of a novel polarization insensitive pentaband THz metamaterial

AbstractThis paper presents the design and characterization of a novel metamaterial with five distinct operating bands for THz applications. The proposed metamaterial is constructed using an ultra‐thin polyimide substrate. The proposed metamaterial has a square geometry with metallic patterns suitably designed to obtain the desired frequency characteristics. The metamaterial operates based on surface plasmon hybridization with stopband characteristics at 0.82, 1.96, 2.77, 3.40 and 4.74 THz. The metamaterial has a small geometry 0.082λo × 0.082λo where λo is wavelength calculated under free‐space conditions at 0.82 THz. The operation of the proposed pentaband metamaterial is described using electric field distributions. The metamaterial reported in this paper has rotational symmetry and hence it is polarization independent. The performance of the metamaterial for various angles of incidence has been evaluated and the results reveal that the proposed metamaterial is stable up to ±70 degrees. The THz metamaterial is appropriate for components like frequency selective surface, sensors and detectors.

A Novel Buck Converter with Constant Frequency Controlled Technique

This paper presents a buck converter with a novel constant frequency controlled technique, which employs the proposed frequency detector and adaptive on-time control (AOT) logic to lock the switching frequency. The control scheme, design concept, and circuit realization are presented. In contrast to a complex phase lock loop (PLL), the proposed scheme is easy to implement. With this novel technique, a buck converter is designed to produce an output voltage of 1.0–2.5 V at the input voltage of 3.0–3.6 V and the maximum load current of 500 mA. The proposed scheme was verified using SIMPLIS and MathCAD. The simulation results show that the switching frequency variation is less than 1% at an output voltage of 1.0–2.5 V. Furthermore, the recovery time is less than 2 μs for a step-up and step-down load transient. The circuit will be fabricated using UMC 0.18 μm 1P6M CMOS processes. The control scheme, design concept and circuit realization are presented in this paper.

Double defects-induced elastic wave coupling and energy localization in a phononic crystal

This study aims to investigate elastic wave localization that leverages defect band splitting in a phononic crystal with double defects through in-depth analysis of comparison of numerical and experimental results. When more than one defect is created inside a phononic crystal, these defects can interact with each other, resulting in a distinctive physical phenomenon from a single defect case: defect band splitting. For a phononic crystal consisting of circular-hole type unit cells in a thin aluminum plate, under A0 (the lowest antisymmetric) Lamb waves, both numerical simulations and experiments successfully confirm the defect band splitting phenomenon via frequency response functions for the out-of-plane displacement calculated/measured at the double defects within a finite distance. Furthermore, experimental visualization of in-phase and out-of-phase defect mode shapes at each frequency of the split defect bands is achieved and found to be in excellent agreement with the simulated results. Different inter-distance combinations of the double defects reveal that the degree of the defect band splitting decreases with the increasing distance due to weaker coupling between the defects. This work may shed light on engineering applications of a multiple-defect-introduced phononic crystal, including broadband energy harvesting, frequency detectors, and elastic wireless power transfer.

PFD with improved average gain and minimal blind zone combined with lock-in detection for fast settling PLLs

In this paper, two Phase frequency detector (PFD) architectures and a PFD with lock-in detection (PFD-LID) are proposed that are designed using the new techniques for selectively resetting the outputs to achieve improved average gain with a lower blind zone. The two proposed PFDs are designed and fabricated using 180 nm CMOS process. The circuits are tested with the variations in the supply voltage from 1.3 V to 1.8 V, achieving higher average gain and the measured blind zone of 3 ps, which is around five times less than earlier reported works. Also, the proposed selective reset techniques are used to design the PFD-LID. Both the PFDs and PFD-LID are validated using the traditional phase-locked loop (PLL) architecture by achieving minimal settling time of the PLL.

A soft-error-tolerant, 1.25 GHz to 3.125 GHz, 3.18 ps RMS-jitter CPPLL in 40 nm CMOS process

This paper analyzes the mechanism by which Single-Event-Upsets (SEUs) and Single-Event-transients (SETs) impact on the working condition of the charge-pump-phase-locked-loop (CPPLL) and relevant hardened techniques, and also presents a soft-error-tolerant CPPLL in 40 nm CMOS process. It employs dual-mode interlocking (DMI) and divider-resistance techniques to reduce the soft-error rate caused by natural irradiation. Simulation and laser test results reveal that the DMI and divider resistance techniques could effectively decrease the number of SEU-sensitive nodes in digital parts (frequency divider, phase, and frequency detector) and SET-sensitive nodes in charge pumps. Under 960pJ laser energy, the number of SEU-sensitive nodes in digital parts decreases 96.1%; the number of SET-sensitive nodes in charge pump decline by 83.1%. The proposed soft-error-tolerant CPPLL operates under a 1.1 V power supply, consumes 16.6 mW of power, and achieves 1.25 GHz - 3.125 GHz working frequency range, 3.18 ps RMS-jitter at a 2.5GHz output frequency.

A 33 MHz Fast-Locking PLL with Programmable VCO and Automatic Band Selection for Clock Generator Application

This paper presents a prototype of an auto-ranging phase-locked loop (PLL) with low jitter noise over a wide operating frequency range using the multiband programmable voltage-controlled oscillator (VCO) gain stage with automatic band selection. We successfully reduce the VCO gain (Kvco) and retain the desired frequency band. The proposed PLL comprises a prescaler, phase frequency detector (PFD), charge pump (CP), programmable VCO and automatic band selection circuit. The PLL prototype with all subblocks was implemented using the TSMC 0.18 μm 1P6M process. Contrary to conventional PLL architectures, the proposed architecture incorporates a real-time check and automatic band selection circuit in the secondary loop. A high-performance dual-loop PLL wide tuning range was realized using an ASIC digital control circuit. A suitable way to maintain the Kvco low is to use multiple discrete frequency bands to accommodate the required frequency range. To maintain a low Kvco and fast locking, the automatic frequency band selection circuit also has two indigenous, most probable voltage levels. The proposed architecture provides the flexibility of not only band hopping but also band twisting to obtain an optimized Kvco for the desired output range, with the minimum jitter and spurs. The proposed programmable VCO was designed using a voltage-to-current-converter circuit and current DAC followed by a four-stage differential ring oscillator with a cross-coupled pair. The VCO frequency output range is 150–400 MHz, while the input frequency is 25 MHz. A sequential phase detection loop with a negligible dead zone was designed to adjust fine phase errors between the reference and feedback clocks. All circuit blocks of the proposed PLL were simulated using the EDA tool HSPICE and layout generation by Laker. The simulation and measured results of the proposed PLL show high linearity, with a dead zone of less than 10 pV. The differential VCO was used to improve the linearity and phase noise of the PLL. The chip measured results show rms jitter of 19.10 ps. The PLL prototype also has an additional safety feature of a power down mode. The automatic band selection PLL has good immunity for possible frequency drifting due to temperature, process and supply voltage variations. The proposed PLL is designed for −40 to +85 °C, a wide temperature range.

PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control

This paper presents a phase-locked loop (PLL) based resonator driving integrated circuit (IC) with automatic parasitic capacitance cancellation and automatic gain control. The PLL consisting of a phase frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO) makes the driving frequency to be locked at the resonant frequency. The resonator is modeled by Butterworth–Van Dyke equivalent circuit model with motional resistance of 72.8 kΩ, capacitance of 6.19 fF, inductance of 79.4 mH, and parasitic parallel capacitance of 2.59 pF. To mitigate the magnitude and phase distortion in the resonator frequency response, it is necessary to compensate for the parasitic capacitance. The proposed automatic parasitic capacitance cancellation loop is operated in the open-loop mode. In the automatic parasitic capacitance cancellation phase, the outputs of the transimpedance amplifier (TIA) at the lower and higher frequency than the resonant frequency (VH and VL), are compared, and the programmable compensation capacitor array matches the VH and VL using binary-searched algorithm to cancel the parallel parasitic capacitance. The automatic gain control (AGC) loop keeps the oscillation at the suitable amplitude, and the AGC output can be used as a measurement of the motional resistance. The AGC loop is also digitally controlled. The proposed resonator driving IC is designed in a 0.18-μm bipolar complementary metal oxide semiconductor double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 3.2 mm2. The simulated phase noise is −61.1 dBc/Hz at 1 kHz and the quality factor ( Q-factor) is 59,590.

A New Blind Zone Free PFD in Fractional-N PLL for Bluetooth Applications

This paper presents a new Phase Frequency Detector (PFD) used in the Fractional-N synthesizer PLL for the Bluetooth range frequencies using TSPC based D-FF. The PFD is designed by using 16 transistors. The operating frequency of the PFD can be modelled in between 2.2GHz-3.8GHz with an input reference frequency is applied of about 50MHz. The design of PFD is done by using GPDK 45nm CMOS technology on SPECTRE simulator with 1.8 V supply voltage. The designed PFD is having maximum operating range and free from blind zone. The results reported in this paper are compared and focused on the blind zone and minimum jitter contribution. The designed PFD consumes least power, minimum number of transistors and minimum jitter contributed by the transistors as compared with the reset free based PFD.

Generation-recombination and 1/f noise in carbon nanotube networks

The low-frequency noise is of special interest for carbon nanotubes devices, which are building blocks for a variety of sensors, including radio frequency and terahertz detectors. We studied noise in as-fabricated and aged carbon nanotube networks (CNNs) field-effect transistors. Contrary to the majority of previous publications, as-fabricated devices demonstrated the superposition of generation-recombination (GR) and 1/f noise spectra at a low-frequency range. Although all the devices revealed identical current–voltage characteristics, GR noise was different for different transistors. This effect is explained by the different properties and concentrations of trap levels responsible for the noise. Unexpectedly, exposure of these devices to the atmosphere reduced both the resistance and GR noise due to nanotube's p-doping by adsorbed water molecules from the ambient atmosphere. The presence of the generation recombination noise and its dependences on the environment provides the basis for selective gas sensing based on the noise measurements. Our study reveals the noise properties of CNNs that need to be considered when developing carbon nanotubes-based selective gas sensors.

A New Quasi Open Loop Synchronization Technique for Grid-Connected Applications

Abstract This paper presents an effective quasi open-loop (QOLS) synchronization technique for grid -connected power converters that is organized in two different blocks. The first block is a new flexible technique for extracting the positive and negative sequence voltage under unbalanced and distorted conditions. It is a decoupled double self-tuning filter (DD-STF) or multiple self-tuning filters (M-STF) according to the conditions. The main advantages of this technique are its simple structure and the fact of being able to work under highly distorted conditions. Each harmonic is separately treated and this allows for selective compensation in active filter applications. The second block is the frequency detector; we propose a neural approach based on an ADALINE for online adaptation of the cut-off frequency of the DD-STF and M-STF considering a possible variation in the main frequency. The main advantage of this method is its immunity to the voltage signal amplitude and phase. In order to improve the performance of the frequency estimation under distorted source voltage, a pre-filtering stage is introduced. Experimental tests validate the proposed method and illustrate all its interesting features. Results show high performance and robustness of the method under low voltage ride through.

Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit

This brief presents a static phase offset (SPO) reduction technique through auto-zeroing in a delay-locked loop (DLL). We propose a self-calibrated, digitally programmable, sensing circuit that can measure both the polarity and the magnitude of the SPO. The SPO is suppressed by tuning a pair of digital-to-time converters (DTCs) at the input of the phase frequency detector (PFD). The proposed technique enables run-time background calibration and can suppress the SPO caused by artifacts from the PFD, charge pump, and loop filter capacitor. Monte Carlo simulation results show that the SPO in a conventional DLL implementation improves from 12.92 ps to 0.90 ps when the proposed auto-zeroing technique is employed.