Frequency Detector Research Articles

A 2.4-GHz Multiphase Inductorless PLL With Coupled-Ring Oscillators and Time-Amplifying Phase-Frequency Detector for Low Phase Noise and Robust Locking Performances

A 2.4-GHz Multiphase Inductorless PLL With Coupled-Ring Oscillators and Time-Amplifying Phase-Frequency Detector for Low Phase Noise and Robust Locking Performances

A low power all-digital frequency locked loop with resource-efficient frequency detector and hysteresis lock detector

A low power all-digital frequency locked loop with resource-efficient frequency detector and hysteresis lock detector

A low power low phase noise wide frequency range PLL

This paper presents a low-noise, low-power, wide output frequency range phase-locked loop (PLL) for WLAN/WiFi transceivers. By employing a dual-symmetric CMOS cross-coupled pair differential inductor voltage-controlled oscillator (VCO), the design achieves low phase noise. In addition, an improved phase frequency detector (PFD) and a programmable low-mismatch charge pump (CP) with feedback compensation bias control are used to mitigate bandwidth and noise variations caused by different reference frequencies. The improved charge pump PLL (CPPLL) is designed in 65 nm CMOS process, and the chip layout occupies an area of 0.28 mm2. Post-layout simulation results indicate that the PLL has a tuning range of 4.6 GHz to 6 GHz, a phase noise of 111.7 dBc/Hz at 1 MHz offset at 5 GHz, a total power consumption of 7.14 mW, and a lock time of about 9μs.

Approaches of frequency-dependent squeezing for the low frequency detector of the Einstein Telescope

The quantum noise in gravitational-wave detectors can be suppressed in a broadband by frequency-dependent squeezing. It usually requires one large scale filter cavity and even two, for example in the low frequency detector of Einstein Telescope, which is a detuned dual recycling Fabry-Perot Michelson interferometer. In this paper, we study the feasibility of replacing two filter cavities with a coupled-cavity, aiming to reduce the optical losses with less number of optics. It turns out this approach is only theoretically valid, however, the required parameters of the optics do not support practical implementation, which is consistent with the results in Jones [Implications of the quantum noise target for the Einstein Telescope infrastructure design, ]. Furthermore, we investigate the viability of utilizing Einstein-Podolsky-Rosen (EPR) squeezing to eliminate either one or two filter cavities in the Einstein Telescope. It turns out EPR squeezing would allow us to eliminate one filter cavity, and can potentially improve the detector sensitivity with the allowance of higher input squeezing level, benefiting from the longer length of the arm cavity which serves as one of the filter cavities for frequency-dependent squeezing. Published by the American Physical Society 2024

Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology

This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) in order to optimize the dead-zone effect while dynamically switching an auxiliary charge pump (CP) module to realize fast phase locking. Furthermore, a TDC-controlled three/five-stage dual-mode adaptively continuously switched VCO is proposed to optimize the phase noise (PN) and power efficiency, leading to an optimal performance tradeoff of the PLL. Based on the 180 nm/1.8 V standard CMOS technology, the complete PLL design and a corresponding simulation analysis are implemented. The results show that, with a 1 GHz reference signal as the input, the output frequency is 50–324 MHz, with a wide tuning range of 260 MHz and a low phase noise of −98.07 dBc/Hz@1 MHz. The key phase-locking time is reduced to 1.11 μs, and the power dissipation is lowered to 1.86 mW with a layout area of 66 μm × 128 μm. A significantly remarkable multiobjective performance tradeoff with topology optimization is realized, which is in contrast to several similar design cases of PLLs.

A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD

A dual-loop CDR (Clock and Data Recovery) is presented to recover digital data from 1 to 6.5 Gbps. The presented frequency acquisition technique is based on full rate clock architecture. By utilizing modified Digital Quadri-correlator Frequency Detector (DQFD) and Frequency Increment/Decrement Control circuit, the lock-in range is improved. Furthermore, the issue of state loss during wide frequency range detection is successfully mitigated. The inclusion of two control wires in the Coarse-fine Tuning VCO enables the utilization of separate loop filters in the dual loops, resulting in a more effective reduction of noise and jitter. Utilizing a 40-nm CMOS process, the presented CDR design has been implemented. The post-layout simulation results at 6.5 Gbps shows a P2P and root-mean-square jitter values are 17.1 ps and 5.79 ps, respectively, for the retimed data.

Design and Implementation of PLL with Dead Zone-Less Low-Power Phase Frequency Detector

This project introduces a Phase-Frequency Detector (PFD) that includes a dedicated circuit for removing the dead zone. This design utilizes Pass Transistor Logic (PTL) and Delay Cells (DCs) to effectively address this issue. Additionally, a Low-Pass Filter is integrated into the system and connected with charge pump, employing a technique that replaces resistors with transistors, thereby significantly reducing the overall circuit area. Furthermore, a Phase-Locked Loop (PLL) serves to eliminate the dead zone and significantly reduce the circuit's size. This project aims to advance circuit design methodologies by enhancing performance and minimizing area requirements.

An Energy-Efficient 12-Bit VCO-Based Incremental Zoom ADC with Fast Phase-Alignment Scheme for Multi-Channel Biomedical Applications

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support VCM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s.

The Comparison of the Electromagnetic Radiation (EMR) from Indoor Plants during Daytime and Nighttime using Frequency Detector

The Comparison of the Electromagnetic Radiation (EMR) from Indoor Plants during Daytime and Nighttime using Frequency Detector

The Correlation of Super Brain Yoga (SBY) on Human Electromagnetic Radiation (EMR) using Frequency Detector

The Correlation of Super Brain Yoga (SBY) on Human Electromagnetic Radiation (EMR) using Frequency Detector

Non-destructive Moisture Content Testing for Soil Brick Using Capacitive Measurement With 50 MHz Radio Frequency

This research paper presents a soil brick moisture measurement by capacitive measurement with radio frequency of 50 MHz and the soil brick as the dielectric material sandwiched between the conductive plates of the capacitor. The moisture content of the soil brick was considered from the capacitance storage capacity of the capacitor. The proposed measurement consisted of a voltage-controlled oscillator, capacitance measurement circuit, radio frequency amplifier, radio frequency detector, and microcontroller unit. After that, a circuit was built and assembled to the radio frequency soil moisture meter of soil bricks for evaluate the soil brick with width of 20 cm, length of 40 cm and the thickness of 20 cm. There are four types of soil brick with moisture of 10% to 30% and 10 times of iterations. From measured results, it was found that the dielectric constant and capacitive value are directed variation with moisture content of soil bricks. Therefore, the moisture content of soil bricks can be found by capacitive measurement. From the measured results, it accurate when comparing the standard measurement with an error of 4–16%.

Design and optimization of phase frequency detector through Taguchi and ANOVA statistical techniques for fast settling low power frequency synthesizer

In this work, a novel phase frequency detector (PFD) architecture using pass transistor logic is proposed. The circuit does not have a reset path, resulting in the elimination of blind zone and dead zone. The ϕ-V characteristics of the PFD were found to have better linearity across the range of −π to π due to the absence of blind and dead zones. The Taguchi and ANOVA statistical techniques were used to optimize the PFD. The optimized PFD exhibited a phase noise of −142.24 dBc/Hz, consumed 5.64 μW of power and had a maximum operating frequency of 5.25 GHz, and a delay of 10.65 ps. Using this PFD, a GHz-range synthesizer was designed, and its performance characteristics were obtained from circuit simulations using CADENCE Virtuoso. The synthesizer had a power consumption of 4.25 mW at a supply of 1.8 V, achieved a lock time of 2.95μs, and could generate frequencies ranging from 0.1 GHz to 4.75 GHz while occupying a chip area of 0.013 mm2. Moreover, the work introduced a new figure of merit, FoM. The synthesizer has potential applications in various devices such as radio receivers, televisions, mobile phones, satellite receivers, and GPS systems.

A Novel Frequency and Positive Sequence Detector for Utility Applications and Power Quality Analysis.

Based on multi-dimensional representation and vector calculus definitions, this paper proposes two novel and quite simple algorithms for utility applications and power quality analysis. The first one is a synchronizing procedure, based on a digital PLL (Phase Locked Loop). Its design and dynamic behavior are analyzed for single and three-phase systems. The second one is a positive sequence detector, which uses the proposed PLL to ensure that the positive sequence components can be calculated even under distorted waveform conditions or frequency variations. Since it is not based on Fortescue’s classical decomposition and no special input filtering are needed, its dynamic response may be as fast as one fundamental cycle. In order to validate the proposed models, simulations are shown and experimental results were obtained by means of a DSP-based system and a prototype of Power Quality Monitor. Furthermore, the PLL algorithm was implemented in a selective active filter to confirm the expectations in a closed-loop application.

Optimisation and Performance Computation of a Phase Frequency Detector Module for IoT Devices

The Internet of Things (IoT) is pivotal in transforming the way we live and interact with our surroundings. To cope with the advancement in technologies, it is vital to acquire accuracy with the speed. A phase frequency detector (PFD) is a critical device to regulate and provide accurate frequency in IoT devices. Designing a PFD poses challenges in achieving precise phase detection, minimising dead zones, optimising power consumption, and ensuring robust performance across various operational frequencies, necessitating complex engineering and innovative solutions. This study delves into optimising a PFD circuit, designed using 90 nm standard CMOS technology, aiming to achieve superior operational frequencies. An efficient and high-frequency PFD design is crafted and analysed using cadence virtuoso. The study focused on investigating the impact of optimising PFD design. With the optimised PFD, an operational frequency of 5 GHz has been achieved, along with a power consumption of only 29 µW. The dead zone of the PFD was only 25 ps.

A novel replica technique based dead zone free phase frequency detector and a self-cascode current-splitting charge pump for a low-spur low power phase-locked loop architecture

In a phase-locked loop (PLL), a high reset pulse width in the phase frequency detector (PFD) and current mismatches in the charge pump (CP) are the major contributors to a high reference spur in a clock. This paper presents a novel replica technique based dead zone free PFD to reduce the reset pulse and a self-cascode current-splitting CP to reduce current mismatch. The proposed PFD and CP are designed using the UMC 180 nm CMOS process. The proposed PFD achieves a reset pulse width of 113 ps. The CP is designed for a CP current of 100 μA. It has an output voltage range of 0.4 V–1.2 V, with a current mismatch of 1.3%. A PLL with the proposed PFD+CP achieves a reference spur that is 39.5% lower than the reference spur of the PLL with conventional PFD+CP. The proposed PFD+CP consumes 0.28 mW power in the locked stated. The layout area consumed by the proposed PFD+CP is 46 × 75 μm2.

A 25.8-GHz Integer-N CPPLL Achieving 60-fs rms Jitter and Robust Lock Acquisition Based on a Time–Amplifying Phase–Frequency Detector

This article presents a 25.8-GHz integer-N charge pump phase-locked loop (CPPLL). With the proposed time–amplifying phase–frequency detector (TAPFD), the in-band noise is greatly suppressed by the phase error amplification gain of TAPFD so as to break the stringent power-noise tradeoff in the conventional CPPLL. Moreover, a frequency pull-in capability analysis is carried out to prove that the proposed phase-locked loop (PLL) features a robust lock acquisition performance. The proposed PLL is prototyped in a 65-nm CMOS process, achieving 60-fs rms jitter, 14.48-mW power consumption, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 252.8-dB FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{J}$</tex-math> </inline-formula> with a 0.45-mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> active area.

A 4–5.2 GHz PLL with 74.8 fs RMS jitter in 28 nm for RF Sampling Transceiver application

AbstractThis paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246.

Simple, low-cost, and well-performing optical phase-locked loop for frequency and phase locking of semiconductor lasers.

We demonstrate a simple, low-cost, and well-performing optical phase-locked loop (OPLL) circuit with ADF4007 as the phase frequency detector chip to achieve frequency and phase locking of two semiconductor lasers in both short and long terms. The measured short term performances, determined by fast feedback, show that the spectral width of the beat signal is low, around 1Hz, and the residual phasing error is 0.04r a d 2. The measured long term performances, determined by slow feedback, show that the drift of the central frequency of the beat signal is within 1.1(1)Hz in 2h, and the derived Allan deviation is less than 0.4Hz within all integration times of up to 1000s. The phase noise measurement shows a suppression of phase noise of the beat signal from free running to closed-loop OPLLs in a Fourier frequency of 10Hz-20kHz. These measurements show that the OPLL circuit we modified can fit most scientific experiments requiring a fixed frequency difference and phase coherence.

ИЗМЕРЕНИЕ ФАЗОВЫХ И АМПЛИТУДНЫХ ШУМОВ ПОЛУПРОВОДНИКОВЫХ ЛАЗЕРОВ. МЕТОДИКА ИЗМЕРЕНИЙ. КАЛИБРОВКА. РЕЗУЛЬТАТЫ

The application of the frequency detector method for measuring the phase noise spectrum of semiconductor lasers has been experimentally demonstrated. The frequency detector is based on an unbalanced Mach-Zehnder interferometer and a photodetector. Analytical relations are obtained that allow one to choose the parameters of the Mach-Zehnder interferometer and perform experimental calibration of the measuring system. A technique is proposed for measuring the spectral components of the phase noise of lasers in the presence of a slow drift of the delay in fiber-optic lines and the frequency of the laser under study. The results of measuring the phase noise of a low-noise DX-1 laser module and high-noise laser diodes LSDLD155 (DFB) and LSFLD155 (FP) are presented. A strong correlation between the amplitude and phase noise levels of these lasers is found. The decisive influence of the noise of LSDLD155 and LSFLD155 lasers on the level of phase noise of optoelectronic (OE) microwave generators built using them is shown. It has been suggested that the low-noise laser module DX-1, which has a phase noise level 20–60 dB lower (in different parts of the spectrum), is not decisive in the level of phase and amplitude noise of an optoelectronic microwave generator. The investigated OE generator was built during the research in this work. The generator has low phase noise: −120 dBc/Hz at a frequency detuning of 10 kHz. Oscillation frequency 6.8 GHz; fiber optic delay line length 200 m.

Mathematical modelling and simulation of a wideband PLL for application in frequency synthesizers

In this paper the mathematical modelling of the Voltage Controlled Oscillator, Phase Frequency Detector, Low Pass Filter, Charge pump for designing a PLL circuit is proposed. Based on the modelling schematics are designed and proposed for the application in frequency synthesizer. The main design feature of this modelling is that VCO tunning switches are controlled digitally. The behaviour of PLL under its region of operation is simulated. The effect of temperature variations and insufficient bandgap overlapping on the output frequency of PLL is also presented and discussed. To avoid the current mismatching and residual phase errors the charge pump is modelled as to calibrate by its own circuit. Various simulations are done for the performance analysis of wideband PLL. The proposed design will have its application in frequency synthesizers suitable for multi band transceivers.