FRAM Device Research Articles

Dynamic Testing of a Commercial FRAM Device Under Gamma Ray Dose and Neutron Beam

Dynamic Testing of a Commercial FRAM Device Under Gamma Ray Dose and Neutron Beam

Electrical and Physical Characteristics of Vanadium-Doped Bi4Ti3O12 Ferroelectric Thin Films after Rapid Thermal Annealing

The V2O5-doped Bi4Ti3O12 of Bi3.9Ti2.9V0.08O12 (BTV) ceramic was used as the target, and the BTV thin films were deposited on the Pt/Ti/SiO2/silicon substrate by radio frequency (RF) magnetron sputtering. The physical characteristics of BTV thin films were prepared under different conditions to find the optimal deposited parameters. The electrical characteristics of BTV thin films under the optimal sputtering and annealing parameters were prepared by using metal-ferroelectric-metal structure. Additionally, the remnant polarization of deposited BTV thin films would be improved by rapid thermal annealing process from our study, and 2Pr was about 40μC/cm2. Finally, the nonvolatile and non-destructive characteristics of one transistor-capacitor (1TC) structure FRAM device, using the annealed BTV films as the gate oxide, were be fabricated and discussed.

RELIABLE PZT CMP TECHNOLOGY FOR NOVEL FRAM CAPACITORS

ABSTRACT In this paper, we report novel (TE-free) FRAM capacitors using reliable PZT CMP process in order to improve ferroelectric properties and enhance mass productivity by simplifying integration of processes. FRAM capacitors were prepared using a PZT film for a stopping layer in ILD CMP using a high selective slurry having a very low PZT removal rate relative to oxide removal rate. Noble metal electrode (TE) and contact (TEC) of conventional (TE/FE/BE) capacitors are not desirable for integration of high-density FRAM device and mass production due to contact etch damage and poor etch and deposition properties of Ir. We investigated the structural and electrical characteristics of MOCVD PZT films grown on Ir bottom electrode before and after PZT CMP process. Even though some degradation in polarization hysteresis of polished PZT capacitors was observed compared to as-deposited capacitors due to interface effect between PZT film and top electrode, electrical properties such as leakage current and fatigue were not sensitive to CMP process variables including down pressure, table speed and polishing time, indicating enough process margin in application of PZT CMP technology. In addition, PZT film roughness was dramatically reduced to result in decrease of leakage current due to the reduction of valley area. In this study, we claimed that new CMP technology with high selective slurry to PZT film was a useful approach in achieving novel FRAM capacitors by simplifying integration processes of FRAM device.

ENHANCED RETENTION PROPERTIES OF Pb(Zr,Ti)O3 THIN FILM BY APPLYING PbTiO3 SEED LAYER

ABSTRACT Reliable ferroelectric 100 nm-thick PZT capacitors for 1.6 V operating FRAM device were successfully developed using MOCVD PZT with a PbTiO3 seed layer process. PbTiO3 seed layer process improved the opposite-state retention properties of polycrystalline PZT films by enhancing the (111) texture. We demonstrated that the same sensing-margin of FRAM device was obtained regardless of PbTiO3 seed layer insertion, while the retention properties were considerably improved.

Novel PZT Capacitor Technology for High Density FRAM Device with 0.18 μm D/R

Novel capacitor technologies for high density FRAM device with 0.18 μm D/R (design-rule) have been researched and developed. In order to realize the high-density FRAM device with 0.18 μm D/R, the PZT film was modified by changing Zr/Ti composition and by using PTO seeding layer. Therefore, the crystallization temperature of the PZT film could be successfully lowered to 550°C. The remnant polarization of PTO-used 100 nm thick PZT capacitors measured at 2.7 V was approximately 24 μC/cm 2 , that is 30% higher than that of the PTO-unused PZT capacitors. Necessarily, as the PZT thickness and crystallization temperature are lowered, the thickness of bottom electrode can be reduced as well. Furthermore, by lowering the PZT crystallization temperature and by applying robust TiAlN oxidation barrier, low (300 Ω/contact) and stable contact resistance in a very small size of BC could be obtained. Finally, we successfully developed a capacitor stack height of 270 nm. The capacitor size was 0.26 × 0.44 μm2 and remnant polarization measured at 2.7 V was approximately 11 μC/cm2.

Highly Reliable and Void-Free IMD Technology for High Density FRAM Device

We discuss the correlation between intermetallic dielectric (IMD) processes and electrical properties of fully integrated ferroelectric cells. The best IMD scheme for higher density FRAM devices is proposed regarding gap-filling properties of narrow metal pitches and electrical characteristics. The used oxides were i)HDP, ii)HDP/POX, and iii)PSG/SOG/USG. HDP possesses good gap-filling characteristics due to the simultaneous application of deposition and etching. However it generates large plasma loads to the wafer, resulting in an undesired degradation of the 2Pr values. The HDP/POX stacks employ an additional POX oxide buffer layer in order to minimize damage due to the HDP deposition process, but the application of the double stack structure shows the same degradation as the HDP-only scheme. However, PSG/SOG/USG stack showed good gap-filling characteristics as well as lower 2Pr degradation. In the triple stack, PSG and USG act as a main IMD layer and as an oxide buffer for SOG coating, respectively. In addition, a definite voltage separation exists between data “1” and data “0” when PSG/SOG/USG is used as IMD, which demonstrates good sensing margin for high-density FRAM scheme. In conclusion, we successfully developed a novel 32Mb FRAM with 1T1C COB structure which was successfully fabricated by using a new IMD scheme of USG/SOG/PSG.

Current Status of Fram Development and Future Direction

Current and future FRAM technologies are reviewed and discussed for developing high density FRAM devices as stand-alone memory application. In order to enter into mainstream of memory devices, FRAM devices should achieve such small cell size factor of ∼8F 2 , strong reliability, and design optimization. The low cell size factor can be realized by using etchless capacitor technology, ultra thin capacitor technology, and runner via technology. The reliability can be acquired by Pt-inserting technology. Finally, high density FRAM device can be accomplished by design optimization.

Effects of UV process on high density 1T1C fram device

A ultraviolet (UV) process is commonly used in fabricating memory devices such as DRAM and SRAM without degrading the memory properties. However, in high density FRAM, the effect of UV light on ferroelectric properties has never been confirmed in real functional FRAM devices FRAM. Therefore, in this paper, we investigated the UV effect on ferroelectric properties and established an optimal back-end process for 1T1C 4Mb FRAM. It was found that the UV light illumination has strong influence on the hysteresis loop of ferroelectric capacitors. The polarization of the capacitor decreased and coercive voltage shifted after exposure to the UV light. It might be attributed to the fact that UV light generates free space charges in the ferroelectric layer and these charges are trapped at the electrode/ ferroelctric interface of the ferroelectric capacitor.

Fabrication of Bi3.25La0.75Ti3O12 thin film for FeRAM device using chemical solution deposition method

Recently, ferroelectric bismuth lanthanum titanate (Bi3.25La0.75Ti3O12) thin film has been expected as a novel material for FRAM device since it has a large polarization, is fatigue free, and can be crystallized at low temperature compared to SrBi2Ta2O9 material. The BLT thin film was fabricated successfully on Pt/Ti/SiO2/Si substrate by chemical solution deposition method. The films were crystallized in the temperature range of 600 ∼700°C using rapid thermal process and quartz tube furnace. X-ray diffraction shows a single-phase film. The spontaneous polarization (Ps) and the switching polarization of BLT film annealed at 700°C for 2 min are 16.75 and 26.28 uC/cm2, respectively.

Novel capacitor process using diffusion barrier rounded by Si/sub 3/N/sub 4/ spacer for high density FRAM device

A novel capacitor process was successfully implemented in 4 Mb FRAM device by developing a barrier layer rounded by Si/sub 3/N/sub 4/ spacer (BRS) scheme. Using this process, it is possible to eliminate an undesired barrier etching damage, which is a major role in degrading ferroelectric properties. The novel capacitor process was generated by etching an Ir barrier layer and rounding the barrier by a Si/sub 3/N/sub 4/ spacer before preparing Pb(Zr/sub 1-x/Ti/sub x/)O/sub 3/ (PZT) films. It was observed that uniform sol-gel derived PZT films were prepared on the patterned Ir substrate by using Si/sub 3/N/sub 4/ spacer, which provides a smooth edge of the patterned cell. The contact resistance between bottom electrode and polysilicon plug after full integration was monitored below 700 /spl Omega/ per contact with contact size 0.6/spl times/0.6 (/spl mu/m/sup 2/). Compared to the ferroelectric capacitor damaged by barrier etching, the novel Pb(Zr/sub 1-x/Ti/sub x/)O/sub 3/ (PZT) capacitor exhibited a well-saturated Q-V curve. The fully processed novel capacitor having 1.2/spl times/1.2 (/spl mu/m/sup 2/) effective area displayed remnant polarization of 14 (/spl mu/C/cm/sup 2/) at an operating voltage of 3.0 V. The BRS ferroelectric capacitor showed a reliable retention property until 100 h at 125/spl deg/C. Same state retention (Qss) was stable with time up to 100 h while opposite state retention (Qos) showed a log-linear decay rate at 125/spl deg/C thermal stress.