Fractional Pixel Motion Estimation Research Articles

Fast motion estimation algorithm for HEVC video codec

Subject of Research. The paper considers motion estimation as the most difficult and resource-consuming process in the high efficiency video coding standard. A fast algorithm is proposed that skips the fractional-pixel motion estimation. Method. The fractional-pixel motion estimation, including the half-pixel and quarter-pixel motion estimation, is used as a refinement process for integer-pixel motion estimation to provide better coding efficiency. The proposed algorithm involves skipping the fractional motion estimation for prediction blocks if the block with 2N × 2N dimension, which contains more information than the other block sizes, is encoded with integer motion estimation. The decision can also be made in reference frames, so that motion estimation at half- and/or quarter-pixel levels can be skipped to reduce encoding time. Main Results. The proposed algorithm is implemented in HM-16.20 reference software. Several test sequences recommended by the International Telecommunication Union (ITU) are used to evaluate its effectiveness. Experimental results show that the proposed fast algorithm reduces the encoding time by an average of 64 % with a performance loss of less than 1 %. Practical Relevance. The proposed fast algorithm provides a reduction in coding time with a slight loss in performance. It can replace an existing unit in the H.265 standard speed up the video compression process.

Adaptive Fractional-Pixel Motion Estimation Skipped Algorithm for Efficient HEVC Motion Estimation

High-Efficiency Video Coding (HEVC) efficiently addresses the storage and transmit problems of high-definition videos, especially for 4K videos. The variable-size Prediction Units (PUs)--based Motion Estimation (ME) contributes a significant compression rate to the HEVC encoder and also generates a huge computation load. Meanwhile, high-level encoding complexity prevents widespread adoption of the HEVC encoder in multimedia systems. In this article, an adaptive fractional-pixel ME skipped scheme is proposed for low-complexity HEVC ME. First, based on the property of the variable-size PUs--based ME process and the video content partition relationship among variable-size PUs, all inter-PU modes during a coding unit encoding process are classified into root-type PU mode and children-type PU modes. Then, according to the ME result of the root-type PU mode, the fractional-pixel ME of its children-type PU modes is adaptively skipped. Simulation results show that, compared to the original ME in HEVC reference software, the proposed algorithm reduces ME encoding time by an average of 63.22% while encoding efficiency performance is maintained.

Survey on Algorithm and VLSI Architecture for MPEG-Like Video Coder

Efficient and dedicated hardware architecture and accelerator micro-engines are crucial implementation forms of MPEG-like video coder. It is significant to excavate and generalize the common technologies and design philosophy of hardwired MPEG-like coders behind number of architectures from academic and industrial communities. This paper makes systematic survey on algorithm and architecture of hardwired MPEG-like coders, from microscopic and macroscopic perspectives, taking H.264/AVC as the analysis target. Recent advances in hardware architectures of prevailing H.264/AVC coders are reviewed and summarized. Furthermore, important algorithm modules, such as integer and fractional pixel motion estimation, mode decision, motion vector prediction, intra prediction, rate control, CABAC coder and deblocking filter are reviewed with detailed analysis on algorithm and hardware architecture. In accordance with the intrinsic characteristics of the algorithm flows, the major design constraints and consideration factors of algorithm and architecture are analyzed respectively. The common technologies of the prevailing architectures are summarized from a systematic perspective, coving different levels ranging from algorithm, architecture, to control and data flows, etc. Based on these analysis, this survey further highlights in-depth summarization and perspectives on MPEG-like coder architecture design. First, the design challenges with multiple target performance optimization are analyzed, and the possible solutions for design challenges are systematically summarized. Second, the rate-distortion-complexity constrained algorithm optimization for MPEG-like video encoder is discussed. Third, typical four-level hierarchical architecture model (SoC system, module, inter-connection, memory) is analyzed, and the pivotal memory architecture and inter-connection architecture are emphasized for analysis. Moreover, the algorithm and architecture design suggestions and preferences for the vital modules are discussed. Fourth, the composite performances of prevailing architectures are evaluated. The concerned target parameters including hardware logic cost, SRAM size, external memory bandwidth, throughput efficiency, power dissipation, and rate-distortion performance are taken as comparison factors. Finally, this paper provides explicit perspectives on future trends of video coder architecture design. The proposed paper can be taken as design reference for H.264/AVC coder hardware architecture, and offer further insight into algorithm and architecture optimization for the new emerging HEVC standard.

Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture

The recent High Efficient Video Coding (HEVC) standard introduces a new and complex interpolation filter for fractional-pixel motion estimation and motion compensation. Recent works propose hardware architectures to accelerate the interpolation filter, employing interpolation datapaths with many adders in parallel. Adder compressors are power-efficient operators, that are applied when intermediate additions are not required, which is the case for interpolation filters. This work evaluates the use of different 7-2 and 8-2 adder compressors structures in the interpolation datapaths of a recent HEVC interpolation filter architecture targeting power efficiency. Results show that 7-2 adder compressor (composed with basic 4-2 and 3-2 adder compressors) and 8-2 adder compressor (composed with basic 4-2 adder compressors) reduce power delay product by 16 and 19 %, respectively, compared with adders generated by the synthesis tool. These adder compressors achieved the best results in terms of PDP compared with many classical adders. The full interpolation filter architecture using the best adder compressors dissipates 9967.1 µW of power and consumes 28.21 pJ of energy per operation.

An Efficient Method for Accuracy Motion Estimation

This article proposes a new algorithm applicable to H.264 based on motion vector coding length and high-pixel accuracy filter operator instead of linear interpolation. After half-pixel accuracy motion estimation, a high accuracy motion estimation can be calculated with the intermediate results. This algorithm can achieve high accuracy estimation and compensation while decreasing algorithm complexity. The computer simulation results show that when the new proposed algorithm for 1/8-pixel accuracy is used in QCIF, CIF, CCIR format pictures, total computing time reduces more than 20% and computing time used for fractional-pixel motion estimation reduces more than 50% while coding length only increases less than 10% and PSNR-Y is approximately equal.

Fast directional search algorithm for fractional pixel motion estimation for H.264 AVC

Fractional pixel motion estimation (ME) is required to achieve more accurate motion vectors and higher compression efficiency. This results in an increase in the computational complexity of the ME process because of additional computational overheads such as interpolation and fractional pixel search. Fast algorithms for fractional ME in H.264/AVC are presented. To reduce the complexity of fractional pixel ME, unimodal error surface assumption is used to check only some points in the fractional pixel search window. The proposed algorithm employs motion prediction, directional quadrant and point-based search pattern and early termination to speed up the process. Hence, the proposed algorithm efficiently explores the neighborhood of integer pixel based on high correlation that exists between the neighboring fractional pixels and unimodal property of error surface. The proposed search pattern and early termination reduce computational time by almost 8% to 18% as compared to the hierarchical fractional pixel algorithm employed in the reference software with a negligible degradation in video quality and negligible increase in bit rate.

On Combining Fractional-Pixel Interpolation and Motion Estimation: A Cost-Effective Approach

The additional complexity of the adoption of fractional-pixel motion compensation technology arises from two aspects: fractional-pixel interpolation (FPI) and fractional-pixel motion estimation (FPME). Different from current fast algorithms, we use the internal link between FPME and FPI as a factor in considering optimization by integrally manipulating them rather than attempting to speed them up separately. In this paper, a refinement search order for FPME is proposed to satisfy the criteria of cost/performance efficiency. And then, some strategies, i.e., FPME skipping, early termination and search pattern pruning, are also given for reducing the number of search positions with negligible coding loss. We also propose a FPI algorithm to save redundant interpolation as well as reduce duplicate calculation. Experimental results show that our integrated algorithm significantly improves the overall speed of FPME and FPI. Compared with the FFPS+XFPI and CBFPS+XFPI, the proposed algorithm has already reduced the speed by a factor of 65% and 32%. Additionally, our FPI algorithm can be used to cooperate with any fast FPME algorithms to greatly reduce the computational time of FPI.

Interpolation-Free Fractional-Pixel Motion Estimation Algorithms with Efficient Hardware Implementation

This paper presents interpolation-free fractional-pixel motion estimation (FME) algorithms and efficient hardware prototype of one of the proposed FME algorithms. The proposed algorithms use a mathematical model to approximate the matching error at fractional-pixel locations instead of using the block matching algorithm to evaluate the actual matching error. Hence, no interpolation is required at fractional-pixel locations. The matching error values at integer-pixel locations are used to evaluate the mathematical model coefficients. The performance of the proposed algorithms has been compared with several FME algorithms including the full quarter-pixel search (FQPS) algorithm, which is used as part of the H.264 reference software. The computational cost and the performance analysis show that the proposed algorithms have about 90% less computational complexity than the FQPS algorithm with comparable reconstruction video quality (i.e., approximately 0.2 dB lower reconstruction PSNR values). In addition, a hardware prototype of one of the proposed algorithms is presented. The proposed architecture has been prototyped using the TSMC 0.18 μm CMOS technology. It has maximum clock frequency of 312.5 MHz, at which, the proposed architecture can process more than 70 HDTV 1080p fps. The architecture has only 13,650 gates. The proposed architecture shows superior performance when compared with several FME architectures.

An adaptive and fast fractional pixel search algorithm in H.264

Fractional pixel motion estimation is applied in H.264 to achieve more accurate motion vectors and higher compression efficiency. It, however, distinctly increased complexity in the procedure of motion estimation. In this paper, we propose an adaptive and fast fractional pixel search algorithm (AFFPS) to reduce the computation load of motion estimation in H.264. Since the sum of absolute difference (SAD) surface is unimodal within the range of ±1 pixel, it can be approximated by line functions in a small area around the optimum motion vector. A novel bypass strategy for fractional pixel search based on these line functions is first proposed to skip unnecessary fractional pixel search. Then, an all-zero block (AZB) detection-based strategy is proposed to terminate ineffective fractional pixel search early. The proposed fractional search algorithm is presented, which adopts the two strategies and greatly improves the center-biased fractional pixel search (CBFPS) method. Simulation results show that the proposed algorithm can reduce more than 71% of the fractional pixel search points and still maintain similar coding efficiency.

A quadratic prediction based fractional-pixel motion estimation algorithm for H.264

Motion estimation (ME) and compensation is the most important technique in video coding. In H.264, the motion vector (MV) of a variable size block is determined by performing the ME search procedure on integer-pixel positions, followed by fractional-pixel refinement. For fast integer-pixel ME algorithms, on the average, ME can be done by examining less than 5 search positions. Considering the conventional fractional-pixel ME algorithm, 8, 16, and 24 fractional-pixel search positions are required to be examined for the best MV at 1/2-, 1/4-, and 1/8-pixel accuracy, respectively. That is, the computational complexity of fractional-pixel ME becomes comparable to that of fast integer-pixel ME. Therefore, to develop an efficient fractional-pixel ME algorithm is greatly desirable. In this study, a fast fractional-pixel ME algorithm is proposed. In this study, a “degenerate” quadratic function is used to precisely determine the “best” quantized predictive motion vector (PMV) at 1/4-pixel accuracy for a variable size block. Based on the partial probability distributions of the sum of absolute component differences between the best MV at 1/4-pixel accuracy determined by the conventional 2-stage full search ME search algorithm and the “best” quantized PMV determined by the proposed algorithm, the search range of local fraction-pixel ME can be well determined. If the best quantized PMV determined by the proposed algorithm and that determined by the center biased fractional-pixel search algorithm are identically (0, 0), then (0, 0) is directly determined as the MV at 1/4-pixel accuracy for the variable size block, without applying the small diamond search pattern (SDSP). Otherwise, the SDSP at 1/4-pixel accuracy is used to determine the final result and the SDSP will be applied at most three times. Based on the experimental results obtained in this study, the four ME performance measures of the proposed algorithm are better than that of four comparison approaches, with slight degradations in average PSNR and bit rate.