Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture

Abstract

The recent High Efficient Video Coding (HEVC) standard introduces a new and complex interpolation filter for fractional-pixel motion estimation and motion compensation. Recent works propose hardware architectures to accelerate the interpolation filter, employing interpolation datapaths with many adders in parallel. Adder compressors are power-efficient operators, that are applied when intermediate additions are not required, which is the case for interpolation filters. This work evaluates the use of different 7-2 and 8-2 adder compressors structures in the interpolation datapaths of a recent HEVC interpolation filter architecture targeting power efficiency. Results show that 7-2 adder compressor (composed with basic 4-2 and 3-2 adder compressors) and 8-2 adder compressor (composed with basic 4-2 adder compressors) reduce power delay product by 16 and 19 %, respectively, compared with adders generated by the synthesis tool. These adder compressors achieved the best results in terms of PDP compared with many classical adders. The full interpolation filter architecture using the best adder compressors dissipates 9967.1 µW of power and consumes 28.21 pJ of energy per operation.