Survey on Algorithm and VLSI Architecture for MPEG-Like Video Coder

Abstract

Efficient and dedicated hardware architecture and accelerator micro-engines are crucial implementation forms of MPEG-like video coder. It is significant to excavate and generalize the common technologies and design philosophy of hardwired MPEG-like coders behind number of architectures from academic and industrial communities. This paper makes systematic survey on algorithm and architecture of hardwired MPEG-like coders, from microscopic and macroscopic perspectives, taking H.264/AVC as the analysis target. Recent advances in hardware architectures of prevailing H.264/AVC coders are reviewed and summarized. Furthermore, important algorithm modules, such as integer and fractional pixel motion estimation, mode decision, motion vector prediction, intra prediction, rate control, CABAC coder and deblocking filter are reviewed with detailed analysis on algorithm and hardware architecture. In accordance with the intrinsic characteristics of the algorithm flows, the major design constraints and consideration factors of algorithm and architecture are analyzed respectively. The common technologies of the prevailing architectures are summarized from a systematic perspective, coving different levels ranging from algorithm, architecture, to control and data flows, etc. Based on these analysis, this survey further highlights in-depth summarization and perspectives on MPEG-like coder architecture design. First, the design challenges with multiple target performance optimization are analyzed, and the possible solutions for design challenges are systematically summarized. Second, the rate-distortion-complexity constrained algorithm optimization for MPEG-like video encoder is discussed. Third, typical four-level hierarchical architecture model (SoC system, module, inter-connection, memory) is analyzed, and the pivotal memory architecture and inter-connection architecture are emphasized for analysis. Moreover, the algorithm and architecture design suggestions and preferences for the vital modules are discussed. Fourth, the composite performances of prevailing architectures are evaluated. The concerned target parameters including hardware logic cost, SRAM size, external memory bandwidth, throughput efficiency, power dissipation, and rate-distortion performance are taken as comparison factors. Finally, this paper provides explicit perspectives on future trends of video coder architecture design. The proposed paper can be taken as design reference for H.264/AVC coder hardware architecture, and offer further insight into algorithm and architecture optimization for the new emerging HEVC standard.