fractional-N PLL Research Articles

A CMOS high-speed pulse swallow frequency divider for .DELTA..SIGMA. fractional-N PLL's

A high-speed pulse-swallow frequency divider suitable for ΔΣ fractional-N synthesizers is proposed. The proposed structure employs the retiming scheme for the modulus control signal to extend the timing margin, thus remarkably increasing the maximum operating speed. Moreover, unlike the conventional structure, the modulus control signal is set and reset by a single triggering signal to eliminate the unwanted offset at the total division ratio. It simplifies the interface logic between the divider and the ΔΣ modulator in ΔΣ fractional-N PLL's. Simulation results show that the proposed divider provides over three times faster operating speed than the conventional one. The proposed divider has been successfully verified in CMOS RF ΔΣ fractional-N frequency synthesizers.

A 2-mm$^{2}$ 0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS

A software-defined radio (SDR) should theoretically receive any modulated frequency channel in the (un)licensed spectrum, and guarantee top performance with energy savings, while still being integrated in a digital CMOS technology. This paper demonstrates a practical 0.1-5 GHz front-end implementation for such an SDR concept, including receiver and local oscillator (LO), with only 2-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area occupation in a 45-nm CMOS process. This scalable radio uses shunt-shunt feedback LNAs, a passive mixer with enhanced out-of-band IIP3, and a fifth order low-area 0.5-20 MHz baseband filter. LO quadrature signals are generated from a dual-VCO 4-10 GHz fractional-N PLL. With noise figure between 2.3 dB and 6.5 dB, out-of-band IIP3 between -3 dBm and -10 dBm, and total power consumption between 59 and 115 mW from a 1.1-V supply voltage, the presented prototype favorably compares with state-of-the-art dedicated radios while enabling, for the first time, wideband reconfigurable performance and energy scalability.

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops

A finite-modulo fractional-N PLL utilizing a low-bit high-order DeltaSigma modulator is presented. A 4-bit fourth-order DeltaSigma modulator not only performs non-dithered 16-modulo fractional-N operation but also offers less spur generation with negligible quantization noise. Further spur reduction is achieved by charge compensation in the voltage domain and phase interpolation in the time domain, which significantly relaxes the dynamic range requirement of the charge pump compensation current. A 1.8-2.6 GHz fractional-N PLL is implemented in 0.18 mum CMOS. By employing high-order deterministic DeltaSigma modulation and hybrid spur compensation, the spur level of less than -55 dBc is achieved when the ratio of the bandwidth to minimum frequency resolution is set to 1/4. The prototype PLL consumes 35.3 mW in which only 2.7 mW is consumed by the digital modulator and compensation circuits.

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

A digital intensive PLL featuring a digital filter in parallel with an analog feed-forward path and a digital controlled oscillator (DCO) is presented. Digital loop filter replaces analog passive filter to reduce chip area and associated gate-leakage in advanced process. It also allows the PLL loop gain and DCO gain to be digitally calibrated to within 100 ppm within 50 mus. Such fine frequency resolution enables the PLL to accurately compensate for the loop parameter variation due to process, voltage and temperature (PVT). The analog feed-forward path is insensitive to quantization error of fractional-N divider and DCO nonlinearity. Direct modulating the DCO frequency and phase through the analog feed-forward path, and compensating the modulating signal digitally for the DCO gain variation are demonstrated. At 3.6 GHz all fractional spurs are under - 75 dBc. The phase noise at 400 kHz and 3 MHz are -115.6 dBc/Hz and -134.9 dBc/Hz, respectively. The chip is fabricated in a 0.13 mu m CMOS process, and occupies an active area of 0.85 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and draws 40 mA from a 1.5 V supply including all auxiliary circuitry.

Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-$N$ PLLs

This paper proposes a novel charge pump (CP) circuit and a gated-offset linearization technique to improve the performance of a delta-sigma (??) fractional-N PLL. The proposed CP circuit achieves good up/down current matching, while the proposed linearization method enables the PFD/CP system to operate at an improved linear region. The proposed techniques are demonstrated in the design of a 2.4-GHz ?? fractional-N PLL. The experimental results show these techniques considerably improve the in-band phase noise and fractional spurs. In addition, the proposed gated-offset CP topology further lowers the reference spurs by more than 8 dB over the conventional fixed-offset approach. This chip is implemented in the TSMC 0.18-?m CMOS process. The fully-integrated ?? fractional-N PLL dissipates 22 mW from a 1.8-V supply voltage.

Behavioral modeling and simulation of fractional-N frequency synthesizer

A set of behavioral voltage-domain verilogA/verilog models is proposed in the paper, based on mathematical models of building blocks and some simulation strategies. The models include nonlinear effects of building blocks and can accurately predict the dynamic or stable characteristic of the closed loop. A three-order ΣΔ fractional-N PLL based frequency synthesizer with a 1.9 GHz central output frequency is implemented with the presented way. Cadence SpectreVerilog simulation results show that the behavioral modeling can provide a great speed-up over the transistor-level simulation. Correspondingly, the phase noise, spurious tones and loop locked time can also be accurately predicted, so it is helpful to optimization design based on system-level.

A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme

In this work an all-digital phase detector for a fractional-N PLL is proposed and demonstrated. The phase detector consists of a single flip-flop, which acts as an oversampled 1 bit phase quantizer. A digital sampling scheme that enables FSK modulation rates much larger than the loop bandwidth is demonstrated, without compromising on the frequency accuracy of the output signal. A prototype 2.2 GHz fractional-N synthesizer incorporating the digital phase detector and sampling scheme is presented as a proof of concept. Although the loop bandwidth is only 142 kHz, an FSK modulation rate of 927.5 kbs is achieved. The 0.7 mm2 prototype is implemented in 0.13 mum CMOS consumes 14 mW from a 1.4 V supply.

Fast-Lock Hybrid PLL Combining Fractional-$N$ and Integer-$N$ Modes of Differing Bandwidths

We introduce a single-loop PLL that operates in a narrower-bandwidth, integer-N mode during phase lock and in a wider-bandwidth, fractional-N mode during transient. This hybrid PLL, as a generalization of the conventional variable-bandwidth PLL that shifts only its bandwidth, simultaneously achieves the fast-locking advantage of the fractional-N PLL and design simplicity of the integer-N PLL, and as such, brings benefits in certain important PLL applications. In addition, the frequency division mode switching, unique in the hybrid PLL, enables a new, more digital protocol to execute bandwidth switching. A CMOS IC prototype attests to the validity of the proposed approach.

Modeling and Simulation of Fractional-N PLL Frequency Synthesizer in Verilog-AMS

A Verilog-AMS model of a fractional-N frequency synthesizer is presented that is capable of predicting spurious tones as well as noise and jitter performance. The model is based on a voltage-domain behavioral simulation. Simulation efficiency is improved by merging the voltage controlled oscillator (VCO) and the frequency divider. Due to the benefits of Verilog-AMS, the ΔΣ modulator which is incorporated in the synthesizer is modeled in a fully digital way. This makes it accurate enough to evaluate how the performance of the frequency synthesizer is affected by cyclic behavior in the ΔΣ modulator. The spur-minimizing effect of an odd initial condition on the first accumulator of the ΔΣ modulator is verified. Sequence length control and its effect on the fractional-N frequency synthesizer are also discussed. The simulated results are in agreement with prior published data on fractional-N synthesizers and with new measurement results.

Comparison of Sigma-Delta Modulator for fractional-N PLL frequency synthesizer

This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM, which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Multistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed, which balances the requirements of tone-free and maximum operation frequency.

11 GHz CMOS ΣΔ frequency synthesiser

A fully integrated 11 GHz fractional-N PLL with a three-stage MASH ΣΔ modulator with DC dither in all stages is implemented in a standard 0.13 µm CMOS technology. The synthesiser generates no fractional spurs at frequency offsets outside the loop bandwidth and a small number of fractional spurs with the power not exceeding −44 dBc within the loop bandwidth at the carrier frequency of 11 GHz.

A Novel Architecture for Programmable Fractional-N PLL

In this paper, a novel architecture for programmable fractional-N PLL is proposed. Unlike the conventional fractional-N PLL, it does not need any input data word to meet step size requirement. It features programmability in step sizes. The ratio of the externally controlled counter values sets the step size and thus step size is not limited by fixed hardware. A flow chart is provided to understand the operation of the various counters used in the proposed architecture. A behavioral modeling approach is attempted to perform overall system simulation using Hspice. A 2.4 GHz fractional-N PLL prototype is demonstrated using 0.35 ?m CMOS process and test results are provided. It has step sizes of the values of integer multiples of 50 kHz. The main contributions include: (i) Novel architecture, and (ii) Prototype implementation, all for programmable fractional-N PLL. Unlike the most PLLs, the proposed PLL system is amenable to behavioral system simulation using Hspice.

A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-/spl mu/m CMOS

This paper presents a single-chip dual-band CMOS direct-conversion transceiver fully compliant with the IEEE 802.11a/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805 GHz (including the Japanese band), the fractional-N PLL based frequency synthesizer achieves an integrated (10 kHz-10 MHz) phase noise of 0.54/spl deg//1.1/spl deg/ for 2/5-GHz band. The transmitter error vector magnitude (EVM) is -36/-33 dB with an output power level higher than -3/-5dBm and the receiver sensitivity is -75/-74 dBm for 2/5-GHz band for 64QAM at 54 Mb/s.

Addition to “A Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation”

[1] I. Bietti, E. Ternporitil, G. Albasini, and R. Castello, “An UMTS sigma delta fractional synthesizer with 200 kHz bandwidth and 128 dBc/Hz at 1 MHz using spurs compensation and linearization techniques,” in Proc. IEEE Custom Integrated Circuits Conf., Sep. 2003, pp. 463–466. [2] S. Pamarti, L. Jansson, and I. Galton, “A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 49–62, Jan. 2004.

Programmable low-noise fast-settling fractional-N CMOS PLL with two control words for versatile applications

Frequency synthesisers are essential parts of various communication systems. The development of application versatile CMOS fractional-N synthesisers has been demanding. In the paper, a novel scheme for programmable fractional-N phase-locked loop based synthesisers is proposed. Two control words are used for achieving the programmability features. The relationships of step size and output frequency with reference frequency, input data and modulus division factors are described. A 2.4 GHz CMOS 12-bit ΣΔ fractional-N synthesiser has been implemented using 0.35 μm CMOS Chartered Semiconductor Manufacturing (CSM) process. Using the two input data words, its programmable features have been demonstrated. It has a phase noise of −110 dBc/Hz at 1 MHz offset and a settling time of less than 37 μs. It consumed 11 mA current while operated from a 3 V supply. Synthesiser operation and measurement results are provided.

A low phase noise C-band frequency synthesizer using a new fractional-N PLL with programmable fractionality

This paper presents a new fractional-N PLL that has an arbitrary denominator of the fractional division ratio as well as an arbitrary numerator and an integer part. This enables a reduction in the phase noise of frequency synthesizers for many applications with various channel-space frequencies. The circuit elements of this fractional-N PLL are fabricated in LSI's that operate up to 6.5 GHz. They have been successfully installed in a C-band frequency synthesizer with a low phase noise MMIC VCO.