fractional-N PLL Research Articles

A novel pulse swallow based frequency divider circuit for a phase-locked loops

A new and unique frequency divider circuit has been proposed for this work. In this paper, we have implemented a $$\varDelta \varSigma$$ΔΣ fractional-N PLL using a proposed pulse swallow based frequency divider and a programmable prescaler divider circuit. Advantages of the proposed pulse swallow based frequency divider circuit have been illustrated and its usefulness are described in details. This novel pulse swallow based frequency divider technique does not include any reset or reload signal for the swallow counter as it is normally triggered by the SR latch output signal in conventional pulse swallow based frequency divider circuit. Insertion of a variable delay element at the output of the program counter can be eliminated which is normally used to settle the problem of arrival of the falling edge of the swallow counter pulse. In addition, preset enable signal can be generated without any frequency dependent delay generation block and in few cases without selection of any frequency dependent RC network block. The residual phase noise output of the divider at 1 MHz offset frequency is $$-174.5$$-174.5 dBc/Hz for a carrier signal frequency of 4.7 GHz and power consumption is 9 mW from a 1.2 V power supply. The design of the fractional-N PLL has been carried out in 130 nm standard CMOS process. There is no zero division in the proposed frequency divider's swallow counter for any counting state due to the novel mathematical calculating algorithm for the pulse swallow divider circuit.

A fast and efficient constant loop bandwidth with proposed PFD and pulse swallow divider circuit in [formula omitted] fractional-N PLL frequency synthesizer

This work presents the design of a ΔΣ fractional-N PLL frequency synthesizer with a new loop bandwidth calibration and automatic frequency control (AFC) circuit, applicable for wide band RF communication system. This new and unique loop bandwidth calibration circuit has been implemented using logarithmic and anti-logarithmic (Base2) architecture. This architecture is an efficient design technique as well as faster operation in CMOS domain. The operating frequency range of the ΔΣ fractional-N PLL frequency synthesizer is from 2.158 to 5.133GHz. The variation of LC VCO gain (KVCO) is obvious due to wide band application and it varies from 30.65MHz/Volt to 368MHz/Volt for the frequency range of 2.158–5.133GHz. Constant loop bandwidth is maintained by controlling the charge pump current. Power consumption of the ΔΣ fractional-N PLL frequency synthesizer is 34mW from a 1.2Volt power supply and the work has been carried out in 0.13μm standard CMOS process. Also, this design includes an automatic frequency control unit for the LC VCO circuit which is coarsely tuned within 1.825μs for KVFC=10 for worst case condition and it completes the loop bandwidth (LBW) calibration within 7.84μs for KLBC=150 for worst case condition. The maximum locking time of the ΔΣ fractional-N PLL frequency synthesizer with loop bandwidth calibration and automatic frequency control circuit is 12.7μs for KVFC=10 and KLBC=150 for worst case condition. The ΔΣ fractional-N PLL is locked much faster than any work reported earlier using the proposed PFD, CP, proposed pulse swallow divider, efficient AFC circuit for LC VCO and a new loop BW calibration technique in transistor level simulation using Cadence SpectreRF. The main advantage of this loop bandwidth calibration technique is that the calibration time can be adjusted according to the PLL output frequency, loop bandwidth calibration accuracy and tuning frequency range of the LC VCO.

Fractional‐ N PLL with multi‐element fractional divider for noise reduction

A novel technique to suppress quantisation noise in a ΔΣ fractional- N phase-locked loop (PLL) using a fine-resolution multi-element fractional divider is presented. The proposed technique suppresses noise uniformly over the entire frequency range. It is mostly digital and is applicable for both analogue and digital PLLs. The proposed technique with an eight-element fractional divider can suppress the quantisation noise by 18 dB compared with a conventional fractional- N PLL.

A fast automatic frequency and amplitude control LC-VCO circuit with noise filtering technique for a fractional-N PLL frequency synthesizer

This work presents the design of an automatic frequency and amplitude control LC VCO circuit with noise filtering technique for fractional-N PLL frequency synthesizers. The LC VCO frequency of operation is from 2.158GHz to 5.133GHz. Phase noise of the LC VCO at 1MHz offset frequency is −123.0dBc/Hz and −116.8dBc/Hz for carrier signal frequency of 2.158GHz and 5.133GHz, respectively. The power consumption of the LC VCO without buffer circuit is 5.14mW from a 1.2V power supply and the fractional-N PLL has been implemented in 0.13μm standard CMOS process. A binary search fast frequency calibration process greatly reduces the overall locking time of the fractional-N PLL frequency synthesizers along with proposed PFD and a CP switching circuit and an efficient pulse swallow based fractional divider circuits, fractional bits are controlled by the HK-MASH 111 Digital Delta Sigma Modulator (DDSM). The fractional-N PLL is coarsely tuned within the maximum time of 1.825μs and the fractional-N PLL is locked within 4μs considering the worst case coarse tuning condition.

A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion

A 3.5 GHz digital fractional-N PLL in 65 nm CMOS technology is presented that achieves phase noise and spurious tone performance comparable to those of a high-performance analog PLL. It is enabled by a new second-order frequency-to-digital converter that uses a dual-mode ring oscillator and digital logic instead of a charge pump and ADC. It also incorporates a new technique to reduce excess phase noise that would otherwise be caused by component mismatches when the DCO input is near integer boundaries. The PLL's largest in-band fractional spur is -60 dBc, its worst-case reference spur is -81 dBc, and its phase noise is -93, -126, and -151 dBc/Hz at offsets of 100 kHz, 1 MHz, and 20 MHz, respectively. Its active area is 0.34 mm 2 and it dissipates 15.6 mW from a 1 V supply.

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

A fully-integrated reconfigurable dual-band (760–960 MHz and 2.4–2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by ×3.24 and ×1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by ×2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.

An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL

This paper presents a 1.9-GHz digital ΔΣ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in 0.11-μm CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging

A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC. This paper proposes constant-slope charging as a method to realize a DTC with intrinsically better integral non-linearity (INL) compared to the popular variable-slope method. The proposed DTC chip realized in 65 nm CMOS consists of a voltage-controlled variable-delay element (DTC-core) driven by a 10 bit digital-to-analog converter. Measurements with a 55 MHz crystal clock demonstrate a full-scale delay programmable from 19 ps to 189 ps with a resolution from 19 fs to 185 fs. As available oscilloscopes are not good enough to reliably measure such high timing resolution, a frequency-domain method has been developed that modulates a DTC edge and derives INL from spur strength. An INL of 0.17% at 189 ps full-scale delay and 0.34% at 19 ps are measured, representing 8-9 bit effective INL-limited resolution. Output rms jitter is better than 210 fs limited by the test setup, while the DTC consumes 1.8 mW.

A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter

This paper describes a fractional-N subsampling PLL in 28 nm CMOS. Fractional phase lock is made possible with almost no penalty in phase noise performance thanks to the use of a 10 bit, 0.55 ps/LSB digital-to-time converter (DTC) circuit operating on the sampling clock. The performance limitations of a practical DTC implementation are considered, and techniques for minimizing these limitations are presented. For example, background calibration guarantees appropriate DTC gain, reducing spurs. Operating at 10 GHz the system achieves −38 dBc of integrated phase noise (280 fs RMS jitter) when a worst case fractional spur of −43 dBc is present. In-band phase noise is at the level of −104 dBc/Hz. The class-B VCO can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9 V and 1.8 V supplies.

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and $\Delta \Sigma $ quantization noise suppression. By combining the phase detection and interpolation functions into XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65 nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with in-band phase noise floor of $-$ 104 dBc/Hz and 1.5 ps $_{\rm rms}$ integrated jitter. The clock multiplier achieves power efficiency of 2.4 mW/GHz and FoM of $-$ 225.8 dB.

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10 -9 . The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm $^{2}$ per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s.

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution. By using TA-TDC in place of a BBPD, the limit cycle behavior that plagues BB-PLLs is greatly suppressed by the TA-TDC, thus permitting wide PLL bandwidth. The proposed architecture is also less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL. Fabricated in 65 nm CMOS process, the prototype PLL achieves better than -106 dBc/Hz in-band noise and 3 MHz PLL bandwidth at 4.5 GHz output frequency using 50 MHz reference. The PLL consumes 3.7 mW and achieves better than 490 fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> integrated jitter. This translates to a FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J</sub> of -240.5 dB, which is the best among the reported fractional-N PLLs.

A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator

This paper describes the first 32 kHz low-power MEMS-based oscillator in production. The primary goal is to provide a small form-factor oscillator (1.5 × 0.8 mm 2 ) for use as a crystal replacement in space-constrained mobile devices. The oscillator generates an output frequency of 32.768 kHz and its binary divisors down to 1 Hz. The frequency stability over the industrial temperature range (-40 °C to 85 °C) is ±100 ppm as an oscillator (XO) or ±3 ppm with optional calibration as a temperature compensated oscillator (TCXO). Supply currents are 0.9 μA for the XO and 1.0 μA for the TCXO at supply voltages from 1.4 V to 4.5 V. The MEMS resonator is a capacitively-transduced tuning fork at 524 kHz. The circuitry is fabricated in 180 nm CMOS and includes low power sustaining circuit, fractional-N PLL, temperature sensor, digital control, and low swing driver.

The Implementation of In-Band FM Based on Fractional-N PLL

This paper studied the in-band frequency modulation technology based on fractional-N PLL, first elaborated the basic principle and transfer function analysis of FM PLL, and according to the fractional-N theory gives the realization principle and the concrete algorithm of the modulation signal frequency in the loop modulation loop bandwidth of PLL, gives the design of key circuit, and the result shows that the technology can realize the frequency of modulation signal low to the DC, and high precision modulation, good frequency stability.

A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO

This paper presents a low-power transceiver with a reconfigurable sliding-IF (intermediate frequency) architecture targeted for wireless body area networks hubs covering 400 MHz and 2.4 GHz bands. By using this architecture, a 1608-1988 MHz PLL synthesizer with only 21% tuning range can fully cover all the available bands around 400 MHz and 2.4 GHz as defined by IEEE 802.15.6 NB (narrow band) and ZigBee. The dual-band transceiver has been designed in 0.18 μm CMOS process. The design consists of a receiver with a wideband front-end and a reconfigurable amplifier-mixer, a transmitter with a reconfigurable two stage full quadrature mixer, a ΣΔ fractional-N PLL and some auxiliary circuits. The measurement result has demonstrated that the proposed transceiver can satisfy the dual-band requirements with comparable or even better performance in noise, receiver sensitivity and power consumption compared to previously-reported transceivers for only a single band.

A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL

This paper presents a 1-GHz ΔΣ fractional-N PLL with a noise-filtering scheme using a FIR-embedded phase interpolator. The proposed dual-referenced interpolation scheme compensates for systematic nonlinearity in circuit operation and increases immunity to mismatches in input seed phases. By multiple use of a dual-referenced interpolator, the phase interpolator realizes an embedded FIR filtering for the quantization noise from the ΔΣ modulator. The implemented PLL in 0.13- μm CMOS consumes 16.8 mW and shows a reduction of the phase noise by 34 dB. With 3.2-MHz-wide bandwidth, the proposed filtering technique achieves an in-band noise of -106 dBc at 100 kHz and an out-of-band noise of -107.5 dBc at 6 MHz.

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

A 6-bit time-to-digital converter that achieves mismatch free operation by using a single delay cell and sampling flip-flop is presented. The proposed TDC was integrated in a digital fractional-N PLL fabricated in a 32-nm digital SoC CMOS process for WiFi/WiMax radios. The TDC consumes 3 mW from a 1.05-V supply and occupies an area of 0.004 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A digital frequency-locked loop is used to track and correct for PVT variations in the TDC and no additional linearization or mismatch calibrations are required. The DPLL uses a 20-bit high dynamic range DAC to drive a VCO in order to effectively realize a DCO with 100-Hz frequency resolution. The 2.5-GHz WiFi band LO output is generated from a 40-MHz reference with an integrated phase noise of - 35 dBc (10 kHz to 10 MHz) while consuming 21 mW . The worst case spur in the LO output is below - 50 dBc without requiring TDC mismatch and linearity calibration.

A 2.8–3.2-GHz Fractional-$N$ Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO

A 2.8–3.2-GHz fractional- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$N$</tex> </formula> digital PLL, implemented in 0.18- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu \hbox{m}$</tex></formula> CMOS, is presented. The PLL architecture has the form of a classic delta-sigma fractional- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$N$</tex></formula> PLL. A PFD generates up and down pulses from the reference and divided-down digitally controlled oscillator (DCO) clock. The time-to-digital converter (TDC) converts the width of up pulses to digital words. The quantization noise introduced by a third-order delta-sigma modulator through the multi-modulus divider is canceled at the TDC output. A resistively interpolated ADC is employed to boost TDC resolution by a factor of five. A dither-less DCO with an inductively coupled fine-tuned varactor bank improves tuning step-size by a factor of 16.6, to 20 kHz. With a 52-MHz reference clock, a 3.2-GHz output clock, and a loop-bandwidth of 950 kHz, this prototype achieves 230-fs rms jitter, integrated from a 1-kHz to 40-MHz offset, while drawing 17 mW from a 1.8-V supply. The in-band phase noise floor is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{111.6 dBc/Hz}$</tex></formula> at a 500-kHz offset. The reference spur is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{75 dBc}$</tex></formula> and the worst-case fractional- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$N$</tex> </formula> spur, by sweeping the multiplication ratio near 61, is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{55 dBc}$</tex></formula> . An FOM of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{240.4 dB}$</tex></formula> is achieved, and this design occupies a core area of 0.62 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{mm}^{2}$</tex> </formula> .

A Study of Self-Dithering for ΔΣ Fractional-N PLL

The ΔΣ fractional-N phase-locked loops PLL are being investigated in order to realize a low fractional spurious signal characteristic. In this PLL, the ΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed, and as a result, the limit cycle oscillation increases the spurious signal power. Therefore, a method is required to suppress this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without an external dither generating circuit. The proposed circuit generates dither from the internal signals of the PLL. We simulated the output spectrum of the proposed circuit. The results showed that the proposed circuit suppressed limit cycle oscillation, and that the spurious level of the proposed circuit was almost equal to the spurious level without limit cycle oscillation.

위상차 전압 변환기를 이용한 Fractional-N 위상고정루프

본 논문에서는 기존의 fractional-N 위상고정루프의 가장 큰 문제점인 fractional 스퍼를 억제하기 위해 위상차-전압 변환기(Phase Difference-to-Voltage Converter : PDVC)를 도입하였다. PDVC는 위상주파수 검출기 출력 신호의 위상차에 따라 전하펌프의 전류량을 조절한다. 제안한 구조는 위상 주파수 검출기(phase frequency detector) 신호들의 위상차가 커지면 전하펌프(charge pump) 전류를 감소시켜 fractional 스퍼를 줄일 수 있는 구조이다. 회로는 1.8V <TEX>$0.18{\mu}m$</TEX> CMOS 공정의 파라미터를 이용하여 HSPICE로 시뮬레이션을 수행하고 회로의 동작을 검증하였다. In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V <TEX>$0.18{\mu}m$</TEX> CMOS process and proved by HSPICE simulation.