FPGA Tools Research Articles

EigenCircuit: Divergent Synthetic Benchmark Generation for Hardware Security Using PCA and Linear Programming

Benchmarks are the standards by which technologies can be evaluated and fairly compared. In the field of digital circuits, benchmarks were critical for the development of CAD and FPGA tools decades ago. Hardware security is an emerging field of research where new techniques of security and vulnerability of hardware designs are being proposed in higher volume each year. Using decade-old VLSI/CAD-oriented benchmarks for analyzing the techniques has many issues as these benchmarks were not developed for security research. Additionally, the rise of statistical analysis or machine learning (ML) to model vulnerabilities and solve security issues demands a very large set of samples for training purposes. Since the number of available VLSI/CAD benchmarks is limited, such volume can only be obtained through synthetic benchmark generation tools. To accommodate both of these needs, the first hardware security-oriented synthetic circuit benchmark generation framework is developed in this article. With the use of principal component analysis (PCA) and linear optimization tool, the benchmarks generated by the proposed framework are “divergent,” that is having maximum variation in structures from each other. By accommodating user inputs for desired features, the framework offers customization for generating richer and more challenging benchmarks for data-driven hardware security. With thorough experimentation, we demonstrate our framework’s scalability, the structural and functional variations in the generated benchmarks, and the advantage of structurally variant synthetic benchmarks in hardware security applications.

Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals

This work presents a soft-filtering digital signal processing architecture based on sigma-delta modulators and stochastic computing. A sigma-delta modulator converts the input high-resolution signal to a single-bit stream enabling filtering structures to be realized using stochastic computing’s negligible-area multipliers. Simulation in the spectral domain demonstrates the filter’s proper operation and its roll-off behavior, as well as the signal-to-noise ratio improvement using the sigma-delta modulator, compared to typical stochastic computing filter realizations. The proposed architecture’s hardware advantages are showcased with synthesis results for two FIR filters using FPGA and synopsys tools, while comparisons with standard stochastic computing-based hardware realizations, as well as with conventional binary ones, demonstrate its efficacy.

WITHDRAWN: Computer Aided Management System of Sports Horse Registration Based on Distributed Storage System and Deep Fusion Learning

Abstract The great success of Deep Learning (DL) in the past has prompted front line accomplishments in different fields, for example, picture acknowledgment and common language handling. One reason for this achievement is the expanded size of the DL model and the expansion of preparing information accessible. To improve the exhibition of continuous DL, it is necessary to improve the scalability of the DL system. This study conducted an extensive and in-depth survey of scalable DL challenges, technologies, and tools on distributed infrastructure. It is built into the infrastructure for DL for parallel DL training, multi-tenant resource scheduling and training, and model data management methods. The board and mentors commonly take a gander at details dependent on manual information and reports to consistently check player details. There is an absence of investigation and utilization of player details to improve players and organizations’ abilities and organizations by coaches. In this study, decision support in sports can be applied so that the correct approach to business intelligence methods can be applied to improve the ability of athletes and organizations to develop sports science and its management and coaching. The proposed system is an analysis based on the FPGA tool, and its performance is better than the existing system.

RETRACTED: Research on the coordinated development of tourism economy based on embedded dynamic data

Tourism is one of the most important and growing industries in the global economy. This sector plays an important role in promoting the national economy. Increased tourism streams can have positive and economic consequences for the country, especially in terms of Gross Domestic Product (GDP) and business openings. In South Asian nations, the travel industry is the driving force of monetary turn of events and GDP development. This examination inspected the effect of the travel industry on financial development and work. Radial Neural Network (RNN) technology and FPGA tools are used for data analysis. This shows the study, with major findings, including the positive and significant impact of tourism on economic growth and the long-term relationship between the employment and research variables. The study shows that lawmakers should focus on policies that emphasize tourism promotion, especially due to the country's huge potential. The impact of this latest policy study and recommendations for future studies is also mentioned.

RETRACTED: Research on programmable controller of construction machinery based on embedded system and cloud computing

In recent years, significant advances in sensor innovation have achieved considerable advances in the proficiency of development and the level of computerization of development hardware. The application of sensor technology to monitor such conditions, self-governing development, and the Internet of Things (IOT) has been generally concentrated in development apparatus. Above all else, this work primarily screens the innovation of oil contamination and holes, vibration and fumes gas checking, and describes construction machinery conditions, including monitoring. Second, this article examines and talks about movement, rotational movement, route/situating frameworks, and vision framework straight for independent development innovation. Third, the Internet of Things Technology will be explained, especially regarding research on general construction machinery, maintenance in the life cycle, construction management, and safety management. Proposed Divergence Data Control Technology (DDCT) is a work under IOT with FPGA tools. Finally, with the advancement of unwavering high quality, sensitive sensors, and huge information, the board of sensor data is portrayed as solving potential problems for future construction machinery.

RETRACTED: Agglomeration development strategy of telecom industry based on embedded system and data mining

Aggregation is driven by both the size of the concentration and the city itself in the industry (urbanization). Since the new company to follow the existing companies in the same industry continues to cluster in these areas, the localized economy will create a cluster to produce the same product. The crisis of power shortage in the telecommunications industry in the summer of the peak power consumption period reduces the power cost through load management measures based on Neural Network (NN) using FPGA tool. Field of Business Intelligence (BI) is, by performing the direct mining data in the database, applying the power of data mining in a number of the hands of the business line and analysts. Sample of the customer, install the collect energy consumption data that the digital power meter. Effective load management strategies have been proposed; the load management measures’ contents can be summarized to compare the measured data. Result join the show's load management strategy, the telecommunications industry, and are very satisfied. In the margin adjustment and Time of Use (ToU) period, customers of this industry can save a certain amount of electricity.

RETRACTED: Business big data analysis based on microprocessor system and mathematical modeling

Big data analysis requires examining large amounts of data. This is, so discover the hidden patterns, and give the insight to make decisions on the correct business. Companies, because it uses the power of data and technology be a more objective data-driven. Big data of human resources, faced with various problems from big data storage security problems. These issues have been discussed in the next four categories based on the Contextual Data Analyzing Technique (CDAT) using FPGA tool. Data were collected and finally to analysts that are eligible to determine the problems caused by direct analysis, on security issues, and to find the problem. Companies that big data is presented to improve the company's strategy, to the best of time, various opportunities to make the right decisions. Human resources are one of the substantive departments of any company that needs big data benefits in a different process. The main purpose is to describe the big human data analysis method to improve company performance. Also, the problem is, all of the human resources department is that it is facing using big data.

Design and Implementation of 64-bit Barrel Shifter with Reconfigurable SoC

In majority of embedded system-based applications, RISC Processors are popular. In these processors, barrel shifters are used for performing arithmetic and logical operations like multiplication, division, shift and rotation operations. The reason behind this will be a great advantage of speed. Because, a barrel shifter can perform shift and rotate operations within a single clock cycle where as in a normal shifter ‘n’ number of clock cycles are required for n-shift or rotate operations. As per the today’s need, in the design and development of 64-bit processors, 64-bit barrel shifters IPs are desired. Therefore, the RTL design of 64-bit barrel shifter, implementation and its verification process with an Artix 7 FPGA and front-end CAD tool is demonstrated in this paper. The main feature of the proposed work is power efficient design. It is implemented with 28nm technology and verified with 100MHz on board clock

Design and Optimization of a FPGA Area Efficient Present Cryptographic Architecture for IoT Node

Lightweight symmetric cyphers are crucial for securing constrained computing networks like the Internet of Things and wireless sensor networks. Traditional cryptographic algorithms are quite resource-intensive. IoT does not make use of these kinds of algorithms. Traditional cryptographic algorithms have to worry about the limited environment and the key size since they increase the complexity of the method. The data is hacked during the wireless transmission from one device to another. The LCS-PRESENT architecture suggested in this study is a mix of the LCS circuit and the PRESENT block. Utilisations of FPGA, including Lookup Tables (LUTs), flip-flops, slices, and frequency, are used in the assessment of the architecture's performance. Using a lookup table, we may construct the key module with less space requirements. By encrypting and decrypting an LCS-PRESENT block, the XILINX tool may be used to assess the security of a system. This study uses a hardware-level encryption technique with an 80-bit key for 64-bit input data. The primary actions of the PRESENT block are key rotation and key replacement. In order to encrypt a picture, it is necessary to switch keys, rotate keys, and generate a digital-based key for use in key rotation and replacement. It provides a lot of protection against threats, so your data is safer. In this study, we employ the Xilinx 14.2 ISE tool, the Verilog HDL programming language, and the FPGA tool to create the LCS-PRESENT architecture. This tool is used to evaluate the efficiency and precision of a building's design. Performance metrics for LUTs, flip-flops, and slices are compared to those of standard, cryptographic methods. Existing and prospective designs' FPGA performances are compared..

An Adaptive Low Power Coding Scheme for the NOC

Low power system design is important for system-on-chip design where communication takes place at higher data rate to realise the system functionality. Low power coding reduces energy by reducing self-switching activity or coupling switching activity. But under typical network-on-chip (NOC) system, we require a low power coding scheme to handle different kinds of data traffic from different IP core at different instant and different places in system-on-chip (SOC). As single low power coding scheme will not solve all application demands, a correlation analysis based adaptive data coding scheme is presented. Based on the classification of data traffic as low, moderate and highly correlated, different coding scheme is applied. The proposed system is simulated in labVIEW FPGA tool for the USRP RIO target. Based on comparative analysis of power consumption between the existing coding schemes and proposed adaptive scheme 25% energy saving is achieved at the worst case scenario.

FPGA-based Implementation of Maximum Power Point Tracking of Solar Cell

This article describes the FPGA based implementation of Maximum Power Point Tracking (MPPT) using Perturbation and Observation (P & O) algorithms for solar cell. This work has been organized in two parts. The complete Maximum Power Point Tracking (MPPT) system model was developed in MATLAB/Simulink environment for functionality verification in the first part. It has been observed from the results which show that maximum power is extracted at the load from PV panel. The second part is to design of P & O algorithm from VHDL code. The designed P & O algorithm was synthesized in Xilinx ISE 14.2 software with small commercial FPGA devices i.e. KINTEX-7 and VIRTEX-5. That designed algorithm was simulated using vector waveform file in FPGA tools. Also, the synthesized results were compared on the basis of area-performance-power obtained through summary of both KINTEX-7 and VIRTEX-5 Xilinx FPGA devices. This work is highly beneficial in real time implementation of algorithm for effective performance.

FPGA-based Implementation of Maximum Power Point Tracking of Solar Cell

This article describes the FPGA based implementation of Maximum Power Point Tracking (MPPT) using Perturbation and Observation (P & O) algorithms for solar cell. This work has been organized in two parts. The complete Maximum Power Point Tracking (MPPT) system model was developed in MATLAB/Simulink environment for functionality verification in the first part. It has been observed from the results which show that maximum power is extracted at the load from PV panel. The second part is to design of P & O algorithm from VHDL code. The designed P & O algorithm was synthesized in Xilinx ISE 14.2 software with small commercial FPGA devices i.e. KINTEX-7 and VIRTEX-5. That designed algorithm was simulated using vector waveform file in FPGA tools. Also, the synthesized results were compared on the basis of area-performance-power obtained through summary of both KINTEX-7 and VIRTEX-5 Xilinx FPGA devices. This work is highly beneficial in real time implementation of algorithm for effective performance.

Reconfigurable Filter Bank Multicarrier Modulation for Cognitive Radio Spectrum Sharing - A SDR Implementation

Background/Objectives: Cognitive radio is used as promising technologies for dynamic spectrum access and optimization of wireless resources. Under dynamic spectrum access to provide the ability of working any band of frequency based on need, the reconfigurable cognitive radio is designed. Methods/Statistical Analysis: Multicarrier modulation is the feasible method to share the spectrum without interference. OFDM is one of the efficient multicarrier techniques available for the system design. One of the problems in OFDM for spectral sharing is the side band leakage that will inject interference from secondary radio sub carrier to primary radio sub carrier. To avoid this, in this work a Filter Bank based Multi Carrier (FBMC) modulation is used. Findings: Few simulation works are reported for the interference free spectrum sharing by using FBMC. But this work analyzes the real time practical implementation of the interference free dynamic spectrum sharing. Reconfigurable is another important aspect of the implementation which is provided by the Kintex 7 FPGA implementation of the reconfigurable filter bank multicarrier modulation using NI USRP 2943R SDR platform. This FBMC based Transceiver is implemented by using fast Xilink IP cores of FFT and systolic array based FIR filter IP core. The transceiver is realized to produce output for every clock after a fixed latency 240 clocks or 6 microsecond for 40Mz clock rate. This performance is achieved using single clock loop architecture of LABVIEW FPGA tool and the parallel, pipelined architecture realization of IP cores and other building blocks. Applications/Improvements: Experimental study shows that the BER of primary user for the implemented system is better than the OFDM system by the factor of 10 -1 .

Active Moderate Power Flow Control of Hybrid Power Converter for Effective PV-Fuel Power Generation using FPGA Topology

The increasing demand of load on hybrid converter is requires a moderate power flow structure and circuit in present scenario. This paper initiates a moderate power flow structure of Cuk and SEPIC is implemented for photovoltaic and fuel cell power generation. The proposed moderate hybrid structure of Cuk and SEPIC converter applied to tolerate discontinue operation of PV and Fuel cell power generation. The proposed converter circuit is used to drawn power regularly from photovoltaic and fuel cell in every modes of operation and reaches maximum efficiency. The familiar method of P&O algorithm is implemented in digital form using FPGA tools. This digital MPPT control circuit provides high efficiency in photovoltaic power extraction. The proposed circuit configuration is analyses for low, medium and high power capacity of Photovoltaic cell. The analyses reports shows present configuration circuit is has high efficiency in medium to high power rating of PV and fuel cell power generation. Implementation of this topology exposed by digital form of FPGA controller and results are compared with simulation results.

Improvement of mechanisms of the processes synchronization in multiprocessor systems-on-chip

Mechanisms of automatic control in parallel computing and synchronization is developed and investigated. Developed mechanisms improved the standard FPGA tools from the leading manufacturers of FPGA and increased efficient of the processes synchronization in multiprocessor systems-on-chip.Reference 6, figures 6.

TCONMAP

Parameterised configurations are FPGA configuration bitstreams in which the bits are defined as functions of user-defined parameters. From a parameterised configuration, it is possible to quickly and efficiently derive specialised, regular configuration bitstreams by evaluating these functions. The specialised bitstreams have different properties and functionality depending on the chosen values of the parameters. The most important application of parameterised configurations is the generation of specialised configuration bitstreams for Dynamic Circuit Specialisation, a technique for optimising circuits at runtime using partial reconfiguration of the FPGA. Generating and using parameterised configurations requires a new FPGA tool flow. In this article, we present a new technology mapping algorithm for parameterised designs, called TCONMAP, that can be used to produce parameterised configurations in which both the configuration of the logic blocks and routing is a function of the parameters. In our experiments, we demonstrate that in using TCONMAP, the depth and area of the mapped circuit is close to the minimal depth and area attainable. Both Dynamic Circuit Specialisation and fine-grained modular reconfiguration are extracted by TCONMAP from the HDL description of the design requiring only simple parameter annotations.

A netlist-level fault-injection tool for FPGAs

A fault-injection tool can be very interesting in context to safety-critical applications, e.g., to test fault-detection and avoidance mechanisms or simply to stress an application and analyze its behavior when faults occur. In this work, a fault-injection tool is presented which can be used to instrument an FPGA design with fault-injection logic on netlist level during the implementation phase and to inject faults during runtime afterwards. The proposed approach can be smoothly integrated into an industrial FPGA tool flow, supports devices from multiple FPGA vendors and is highly configurable in order to fit to the number of available FPGA logic resources. Differences to related approaches which are applied on either HDL- and netlist-level as well as on the FPGA configuration bitstream are described. Finally, some results are presented to prove the applicability of the proposed solution.

FPGA를 위한 분석적 배치에서 사전 패킹, 조기 배치 고정 및 밀도 분석 다층화

Previous academic research on FPGA tools has relied on simple imaginary models for the targeting architecture. As the first step to overcome such restriction, the issues on analytic placement and legalization which are applied to commercial FPGAs have been brought up, and several techniques to remedy them are presented, and evaluated. First of all, the center of gravity of the placed cells may be far displaced from the center of the chip during analytic placement. A function is proposed to be added to the objective function for minimizing this displacement. And then, the density map is expanded into multiple layers to accurately calculate the density distribution for each of the cell types. Early fixation is also proposed for the memory blocks which can be placed at limited sites in small numbers. Since two flip-flops share control pins in a slice, a compatibility constraint is introduced during legalization. Pre-packing compatible flip-flops is proposed as a proactive step. The proposed techniques are implemented on the K-FPGA fabric evaluation framework in which commercial architectures can be precisely modeled, and modified for enhancement, and validated on twelve industrial strength examples. The placement results show that the proposed techniques have reduced the wire length by 22%, and the slice usage by 5% on average. This research is expected to be a development basis of the optimization CAD tools for new as well as the state-of-the-art FPGA architectures.

Low-cost dedicated hardware IP modules for background subtraction in embedded vision systems

This paper presents the design and implementation of dedicated hardware IP modules for background subtraction, which are suitable to be implemented in embedded vision systems and are efficient in terms of performance, resource consumption, and operational speed. To achieve this goal, a comprehensive experimental study of different algorithms has been carried out by evaluating a wide range of quality parameters. From the results of this analysis, five candidate algorithms were selected and implemented using a model-based design methodology supported by Matlab and Xilinx FPGA tools. Using only the internal block memory available in the FPGA, they provide adequate solutions for processing low-resolution images with CIF and QCIF formats.

Rapid evaluation of custom instruction selection approaches with FPGA estimation

The main aim of this article is to demonstrate that a fast and accurate FPGA estimation engine is indispensable in design flows for custom instruction (template) selection. The need for a FPGA estimation engine stems from the difficulty in predicting the FPGA performance measures of selected custom instructions. We will present a FPGA estimation technique that partitions the high-level representation of custom instructions into clusters based on the structural organization of the target FPGA, while taking into account general logic synthesis principles adopted by FPGA tools. In this work, we have evaluated a widely used graph covering algorithm with various heuristics for custom instruction selection. In addition, we present an algorithm called Refined Largest Fit First (RLFF) that relies on a graph covering heuristic to select non-overlapping superset templates, which typically incorporate frequently used basic templates. The initial solution is further refined by considering overlapping templates that were ignored previously to see if their introduction could lead to higher performance. While RLFF provides the most efficient cover compared to the ILP method and other graph covering heuristics, FPGA estimation results reveals that RLFF leads to the worst performance in certain applications. It is therefore a worthy proposition to equip design flows with accurate FPGA estimation in order to rapidly determine the most profitable custom instruction approach for a given application.