Abstract
In majority of embedded system-based applications, RISC Processors are popular. In these processors, barrel shifters are used for performing arithmetic and logical operations like multiplication, division, shift and rotation operations. The reason behind this will be a great advantage of speed. Because, a barrel shifter can perform shift and rotate operations within a single clock cycle where as in a normal shifter ‘n’ number of clock cycles are required for n-shift or rotate operations. As per the today’s need, in the design and development of 64-bit processors, 64-bit barrel shifters IPs are desired. Therefore, the RTL design of 64-bit barrel shifter, implementation and its verification process with an Artix 7 FPGA and front-end CAD tool is demonstrated in this paper. The main feature of the proposed work is power efficient design. It is implemented with 28nm technology and verified with 100MHz on board clock
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