FPGA Resources Research Articles

Low Error Efficient Approximate Adders for FPGAs

In this paper, we propose a methodology for designing low error efficient approximate adders for FPGAs. The proposed methodology utilizes FPGA resources efficiently to reduce the error of approximate adders. We propose two approximate adders for FPGAs using our methodology: low error and area efficient approximate adder (LEADx), and area and power efficient approximate adder (APEx). Both approximate adders are composed of an accurate and an approximate part. The approximate parts of these adders are designed in a systematic way to minimize the mean square error (MSE). LEADx has lower MSE than the approximate adders in the literature. The 32-bit LEADx with 16-bit approximation has 20% lower MSE than the approximate adder with the lowest MSE in the literature. The 16-bit APEx with 8-bit approximation has the same area, 60% lower MSE, and 4.5% less power consumption in Xilinx Virtex 7 FPGA than the smallest and lowest power consuming approximate adder in the literature. APEx has smaller area and lower power consumption than the other approximate adders in the literature. As a case study, the approximate adders are used in video encoding application. LEADx provided better quality than the other approximate adders for video encoding application. Therefore, our proposed approximate adders can be used for efficient FPGA implementations of error tolerant applications.

A High speed data link optimization for digitalized transfer to processing FPGA

State-of-the-art arrays of detectors, that require digital processing, may have a sizeable number of digitalized signal links. This is the case in several experimental nuclear physics instruments. Moreover, the data rate of the sampled signals, defined primary by the signal bandwidth of the individual detectors, may not exhaust the capabilities of a single FPGA transceiver input. The preprocessing is usually carried out in a modern FPGA with transceiver data rate capabilities over 10Gbps. Moreover, cost effective FPGA have a limited number of transceivers for given FPGA processing capabilities. The investigation of a cost-effective and efficient solution to the mismatch between both data rates, optimizing simultaneously the use of the FPGA resources, is the topic of the present work. We have developed a solution based on the Time Domain Multiplexing link aggregation, in the form of a Mezzanine board. This mezzanine combines four channels from an optical or copper input up to 2.5 Gbps to one up to 10Gbps, and serves them to the FPGA via the mezzanine connector. The board itself is controlled by a small FPGA by the Two Wire Interface (TWI) protocol as a standalone intelligent device, so minimum slow control is needed. The solution has been also developed for a motherboard housing a SoM module and FMC connector as an alternative implementation. An associated firmware has been developed to de-aggregate the data in the FPGA and recover the original sampled data, based on JESD204 communication protocol, inside the FPGA. The method has been validated and applications, beyond the development of the AGATA electronics, may be envisioned.

A Novel Multiplier-Less LMS Adaptive Filter Design Based on Offset Binary Coded Distributed Arithmetic

Multiply-Accumulate (MAC) operation is the backbone of Least Mean Squares (LMS) digital adaptive filters. Implementing LMS on hardware platform as a Fully Dedicated Architecture (FDA) multiplier becomes bottleneck for higher order filters, prompting high area, cost and power requirements and hence renders the design unsuited for practical implementation. In this paper, we have proposed a composite design that makes use of Distributed Arithmetic (DA) to replace the bottleneck multiplier with memory units that store Partial Products (PPs) to emulate multiplication. The depth of these memory units tends to exponentially grow as the filter order rises. To manage that, we have used Half Memory algorithm (HM) and Offset Binary Coding (OBC) to refine the structure of PPs such that the memory size is reduced at least by a factor of 4 for the same filter order. The proposed design improves system's Throughput, Critical Path Delay, Power Consumption and FPGA Resource Utilization. However, it introduces Latency in both the output and update segments of the LMS algorithm. To provide an option between resource utilization and latency, we have suggested a mechanism to halve the originally produced latency by the Parallel Processing of input bit steam w.r.t even and odd bits. Moreover, we have also proposed a method that reduces the latency of update module at the slight expense of other design attributes. The fundamental structure of the proposed design is flexible owing to the dynamic memory structure as well as the option to choose between latency and resource minimization. Simulations have been carried out in Xilinx Vivado and conclusions have been drawn by comparing both FDA and DA based designs. Results for a 16-tap filter indicate a remarkable improvement in Throughput, Area Utilization and Power Consumption by 18%, 5% and 3.5% respectively at the expense of 4× escalated latency. The Half Latency method allowed the latency to drop 2× but with slightly elevated power and area attributes.

Metis: An Integrated Morphing Engine CPU to Protect Against Side Channel Attacks

Power consumption and electromagnetic emissions analyses are well established attack avenues for secret values extraction in a large range of embedded devices. Countermeasures against these attacks are approached at different levels, from modified logic styles, to changes in the software implementations. In this work, we propose a microarchitectural modification to a compact RISC-V SoC, the OpenTitan open source silicon root of trust, providing a code morphing countermeasure against power and electromagnetic emissions side channel attacks. Our approach allows the countermeasure to be applied transparently, without the need for any software modification to the cryptographic primitive running on OpenTitan. Our microarchitecture integration of a morphing engine also allows us to provide transparent protection to memory operations. We validate our approach through measurements on an actual FPGA prototype on a Xilinx Artix-7. Our integrated morphing engine increases the FPGA resource consumption by less than 8%, plus the resources required by an RNG of choice, with respect to the original OpenTitan SoC. Our design shows a side channel attack resistance improvement of at least $250\times $ in the Measurements-To-Disclose metric with respect to the unprotected design. We benchmark the performance of our proposed architecture on all the ISO/IEC standard symmetric block ciphers, including, among the other AES, reducing the execution time overhead by $21\times $ to $141\times $ with respect to a continuously morphing software solution.

RETRACTED: Development of financial option pricing system based on fpga and machine learning

Abstract A machine learning and FPGA method, ready for deployment fortunately industrial environments. Investment decision-making process to conduct a comprehensive economic assessment of the need to ensure accurate and scientific. Examples of system dynamics as a tool of the artist as a stage show, and is associated with a local project to build the model. Model, mainly in order to simulate the development ability of the important projects in order to obtain the economic rationality, it is based on the actual project of the model. Quickly develop a program to reduce high-level description based on a map function correctly FPGA and machine learning implementation. This direct source code to achieve not only difficult to achieve the desired results, as well as a sequence of optimization could be useful to more efficient custom of resources of goal FPGA.

Improving performance and determinism of multitasking systems on the LEON architecture

Real-time systems are characterised by the fact that they have to meet a set of both functional and temporal requirements. Processor architectures have a significant impact on the predictability of software execution times and can add different sources of indeterminism depending on the features provided. The LEON processor family is the reference platform for space missions of the European Space Agency, with open-source implementations that are written in VHDL language. All versions of the LEON processors conform to the SPARC architecture Version 8. This architecture groups the general-purpose registers into windows to reduce memory transfer overhead in function calls. Unfortunately, this mechanism introduces indeterminism in software execution times at various levels. In this paper, we propose an extension to the original architecture that provides determinism for a configurable subset of tasks and interrupt service routines and eliminates the concurrency-related jitter, all this with a minimum cost in terms of FPGA resource utilisation. For the validation of the proposed solution, we have implemented the extension into the VHDL code of the LEON3 processor and modified the source code of the RTEMS operating system to make use of the new functionality.

HeteroYARN: A Heterogeneous FPGA-Accelerated Architecture Based on YARN

In recent years, the heterogeneous distributed platform integrating with FPGAs to accelerate computation tasks has been widely studied to deal with the deluge of data. However, most of current works suffer from poor universality and low resource utilization that run specific algorithms with the highly customized structure. Moreover, there are still many challenges, such as data curation, task scheduling, and resource management, which further limit the scalability of a CPU-FPGA distributed platform. In this paper, we present HeteroYARN, an FPGA-accelerated heterogeneous architecture based on YARN platform, which provides resource management and programming support for computing-intensive applications using FPGAs. In particular, the HeteroYARN abstracts FPGA accelerators as general resources and provides programming APIs to utilize those accelerators easily. Our HeteroYARN simplifies the request and usage of FPGA resources to enhance the efficiency of the heterogeneous framework while maintaining previous workflow unchanged. Experimental results using two representative algorithms, K-means and Naive Bayes classifier, which are accelerated by FPGAs, demonstrate the usability of the HeteroYARN framework and show performance speedup improvement by 7.5x (K-means) and 2.3x (Naive Bayes) respectively compared to conventional CPU-only applications provided by Mahout.

DIGITALLY PROGRAMMABLE MULTI-SCROLL CHAOS GENERATOR ON FPGA

Multi-scroll chaotic attractors exhibit higher unpredictability than double-scroll attractors. However, the more number of scrolls cost the more usage of sources. To overcome this problem, the attractor design should be simplified. This paper presents a systematic approach that enables to realize digital piece wise linear (PWL) function in nonlinear dynamical system and to obtain whole behaviors in only one model. The proposed design requires only number of scroll as input and can realize chaotic PWL signal with a fewer number of FPGA resources. In the implementation stage of the study, the discrete mathematical equations of the chaotic attractor is modelled in Xilinx System Generator (XSG) platform and realized by using Xilinx Kintex-7 KC705 Evaluation Board.

The digital beam forming technique in AgileDARN high-frequency radar

An all-digital agile dual auroral radar network (AgileDARN) was developed by the National Space Science Center, Chinese Academic of Sciences (NSSC, CAS). AgileDARN can achieve higher performance and greater flexibility based on highly digitized hardware and its distributed digital signal processing system. Multiple receiving beams can be created within the transmitting beam pattern better to determine the direction of arrival (DOA). In each beam, seven real-time azimuthal sub-beams are synthesized simultaneously with 16 main digital receiver channels. Each sub-beam detects the echo around the transmitting boresight with an angular separation of 0.46°. Comparing the echoes from different sub-beams, the azimuthal geolocation of the irregularities can be improved when their volume is smaller than the beamwidth. Furthermore, the Chebyshev window enables the control of the sidelobes and antenna pattern, effectively suppressing interference. To implement multi-beam forming, extra processing resources of the field-programmable gate array (FGPA) are required. This paper introduces the signal processing procedure and analyzes the requirements on the FPGA resources，and the technique is validated with meteor echoes received by the AgileDARN radar. The azimuthal geolocation of echoes increases by seven times compared with the single beamforming SuperDARN radar.

Bit-Vector-Based Hardware Accelerator for DNA Alignment Tools

Next generation sequencing technologies have noticeably improved in the last decade. Time and cost of whole genome sequencing are important challenges that must be reduced, opening unprecedented opportunities to various research and development areas. The alignment or mapping of small reads produced by sequencing machines to reference genomes of billions of nucleotides is a fundamental task in this sequencing process. It is computationally highly demanding and has become the bottleneck of the DNA analysis process. This paper proposes hardware acceleration based on FPGA of the Myers bit-parallelized algorithm, appropriately modified to be used in the extend stage of DNA alignment tools. The proposed design can be employed in conjunction with software functions, as it constitutes an extremely fast heterogeneous DNA alignment system. The implementation results show a speedup of up to [Formula: see text] relative to a sequential implementation only in software. In addition, due to the limited use of FPGA resources and the modular design, multiple modules can be used to completely populate the chip, further increasing the computing speed.

FOS

With FPGAs now being deployed in the cloud and at the edge, there is a need for scalable design methods that can incorporate the heterogeneity present in the hardware and software components of FPGA systems. Moreover, these FPGA systems need to be maintainable and adaptable to changing workloads while improving accessibility for the application developers. However, current FPGA systems fail to achieve modularity and support for multi-tenancy due to dependencies between system components and the lack of standardised abstraction layers. To solve this, we introduce a modular FPGA operating system – FOS, which adopts a modular FPGA development flow to allow each system component to be changed and be agnostic to the heterogeneity of EDA tool versions, hardware and software layers. Further, to dynamically maximise the utilisation transparently from the users, FOS employs resource-elastic scheduling to arbitrate the FPGA resources in both time and spatial domain for any type of accelerators. Our evaluation on different FPGA boards shows that FOS can provide performance improvements in both single-tenant and multi-tenant environments while substantially reducing the development time and, at the same time, improving flexibility.

Resource Partitioning and Application Scheduling with Module Merging on Dynamically and Partially Reconfigurable FPGAs

Dynamically partially reconfigurable (DPR) technology based on FPGA is applied extensively in the field of high-performance computing (HPC) because of its advantages in processing efficiency and power consumption. To make full use of the advantages of DPR in execution efficiency, we build a DPR system model that meets to the actual application requirements and the objective constraints. According to the consistency of reconfiguration order and dependencies, we propose two algorithms based on simulated annealing (SA). The algorithms partition FPGA resource to several regions and schedule tasks to the regions. In order to improve the performance of the algorithms, we exploit the module merging technology to improve the parallelism of task execution and design a new solution generation method to speed up the convergence speed. Experimental results show that the proposed algorithms have a lower time complexity than mixed-integer linear programming (MILP), iterative scheduler (IS) and Ant Colony Optimization (ACO). For applications with more tasks, the proposed algorithms show performance advantages in producing better partitioning and scheduling results in a shorter time.

An FPGA Accelerator for Real-Time Lossy Compression of Hyperspectral Images

Hyperspectral images offer great possibilities for remote studies, but can be difficult to manage due to their size. Compression helps with storage and transmission, and many efforts have been made towards standardizing compression algorithms, especially in the lossless and near-lossless domains. For long term storage, lossy compression is also of interest, but its complexity has kept it away from real-time performance. In this paper, JYPEC, a lossy hyperspectral compression algorithm that combines PCA and JPEG2000, is accelerated using an FPGA. A tier 1 coder (a key step and the most time-consuming in JPEG2000 compression) was implemented in a heavily pipelined fashion. Results showed a performance comparable to that of existing 0.18 μm CMOS implementations, all while keeping a small footprint on FPGA resources. This enabled the acceleration of the most complex step of JYPEC, bringing the total execution time below the real-time constraint.

High-Level Synthesis Design for Stencil Computations on FPGA with High Bandwidth Memory

Due to performance and energy requirements, FPGA-based accelerators have become a promising solution for high-performance computations. Meanwhile, with the help of high-level synthesis (HLS) compilers, FPGA can be programmed using common programming languages such as C, C++, or OpenCL, thereby improving design efficiency and portability. Stencil computations are significant kernels in various scientific applications. In this paper, we introduce an architecture design for implementing stencil kernels on state-of-the-art FPGA with high bandwidth memory (HBM). Traditional FPGAs are usually equipped with external memory, e.g., DDR3 or DDR4, which limits the design space exploration in the spatial domain of stencil kernels. Therefore, many previous studies mainly relied on exploiting parallelism in the temporal domain to eliminate the bandwidth limitations. In our approach, we scale-up the design performance by considering both the spatial and temporal parallelism of the stencil kernel equally. We also discuss the design portability among different HLS compilers. We use typical stencil kernels to evaluate our design on a Xilinx U280 FPGA board and compare the results with other existing studies. By adopting our method, developers can take broad parallelization strategies based on specific FPGA resources to improve performance.

Model of automated synthesis tool for hardware accelerators of convolutional neural networks for programmable logic devices

Currently, more and more tasks on image processing and analysis are being solved using convolutional neural networks. Neural networks implemented using high-level programming languages, libraries and frameworks cannot be used in real-time systems, for example, for processing streaming video in cars, due to the low speed and energy efficiency of such implementations. The application of specialized hardware accelerators of neural networks is necessary for these tasks. The design of such accelerators is a complex iterative process requiring highly specialized knowledge and qualification. This consideration makes the creation of automation tools for high-level synthesis of such computers a relevant issue. The purpose of this research is a tool development for the automated synthesis of neural network accelerators from a high-level specification for programmable logic devices (FPGAs), which reduces the development time. A description of networks is used as a high-level specification, which can be obtained using the TensorFlow framework. The several strategies have been researched for optimizing the structure of convolutional networks, methods for organizing the computational process and formats for representing data in neural networks and their effect on the characteristics of the resulting computer. It was shown that structure optimization of neural network fully connected layers on the example of solving the handwritten digit recognition problem from the MNIST set reduces the number of network parameters by 95 % with a loss of accuracy equal to 0.43 %, pipelining of calculations speeds up the calculation by 1.7 times, and parallelization of the computing process individual parts provides the acceleration by almost 20 times, although it requires 4-6 times more FPGA resources. Applying of fixed-point numbers instead of floating-point numbers in calculations reduces the used FPGA resources by 1.7–2.8 times. The analysis of the obtained results is carried out and a model of an automated synthesis tool is proposed, which performs the indicated optimizations in automatic mode in order to meet the requirements for speed and resources used in the implementation of neural network accelerators on FPGA.

P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA

The network-on-chip (NoC) has emerged as an efficient and scalable communication fabric for chip multiprocessors (CMPs) and multiprocessor system on chips (MPSoCs). The NoC architecture, the routers micro-architecture and links influence the overall performance of CMPs and MPSoCs significantly. We propose P-NoC: an FPGA-based parameterized framework for analyzing the performance of NoC architectures based on various design decision parameters in this paper. The mesh and a multi-local port mesh (ML-mesh) topologies have been considered for the study. By fine-tuning various NoC parameters and synthesizing on the FPGA, identify that the performance of NoC architectures are influenced by the configuration of router parameters and the interconnect. Experiments show that the flit width, buffer depth, virtual channels parameters have a significant impact on the FPGA resources. We analyze the performance of the NoCs on six traffic patterns viz., uniform, bit shuffle, random permutation, transpose, bit complement and nearest neighbor. Configuring the router and the interconnect parameters, the ML-mesh topology yields 75% lesser utilization of FPGA resources compared to the mesh. The ML-mesh topology shows an improvement of 33.2% in network latency under localized traffic pattern. The mesh and ML-mesh topologies have 0.53 $$\times$$ and 0.1 $$\times$$ higher saturation throughput under nearest neighbor traffic compared to uniform random traffic.

Optimizations for FPGA-Based Ultrasound Multiple-Access Spread Spectrum Ranging

Indoor localization based on ultrasound signals has been carried out by several research groups. Most of the techniques rely on a single ultrasound pulse ranging, where the Time of Flight between the ultrasound emitters and a receiver is computed. Ultrasound orthogonal modulation techniques have also been investigated and allow to compute the range between the receiver and multiple simultaneous emitters with increased accuracy. However, no comparative investigation on the possibilities of each of the modulation techniques, comprising Direct Sequence Spread Spectrum, Frequency Hopping Spread Spectrum, and Chirp Spread Spectrum, could be found. Also, common optimized demodulation and correlation techniques for FPGA ready implementations are not widely available. Moreover, the hardware requirements for capturing modulated ultrasound signals could not be found for all the techniques. In this work, the different modulation techniques are optimized and implemented on an FPGA. A dedicated custom ultrasound MEMS-based receiver hardware for broadband ultrasound signal capturing is developed. Several modulation parameters are developed and applied for optimized signal processing. The FPGA resource consumptions are evaluated for the implemented methods. All methods are compared against the regular pulse ranging method, in both single-access and multiple-access ranging mode. Results show that, on average, up to 8 ultrasound-modulated emitters with an orthogonal sequence of length 63 can be demodulated on a Zynq7020 FPGA. In most cases, ranging up to 8 m is demonstrated in both single- and multiple-access mode, with accuracies generally remaining at a centimeter level. The requirements and capabilities for each of the modulation schemes are highlighted in the conclusions.

Substream-Centric Maximum Matchings on FPGA

Developing high-performance and energy-efficient algorithms for maximum matchings is becoming increasingly important in social network analysis, computational sciences, scheduling, and others. In this work, we propose the first maximum matching algorithm designed for FPGAs; it is energy-efficient and has provable guarantees on accuracy, performance, and storage utilization. To achieve this, we forego popular graph processing paradigms, such as vertex-centric programming, that often entail large communication costs. Instead, we propose a substream-centric approach, in which the input stream of data is divided into substreams processed independently to enable more parallelism while lowering communication costs. We base our work on the theory of streaming graph algorithms and analyze 14 models and 28 algorithms. We use this analysis to provide theoretical underpinning that matches the physical constraints of FPGA platforms. Our algorithm delivers high performance (more than 4× speedup over tuned parallel CPU variants), low memory, high accuracy, and effective usage of FPGA resources. The substream-centric approach could easily be extended to other algorithms to offer low-power and high-performance graph processing on FPGAs.

Compressed Principal Component Regression (C–PCR) Algorithm and FPGA Validation

To address the hardware and/or software implementation issues of principal component regression (PCR), we propose a novel algorithm called compressed PCR (C–PCR). C–PCR projects the input data to a lower dimensional space first, and then applies the compressed data to a significantly smaller PCR engine. We show that C–PCR can lower the computational complexity of PCR with a factor of compression ratio (CR) squared, i.e., CR2. Moreover, the output signal of C–PCR follows that of PCR with a small error, which increases with CR, when the projections are random. Using datasets of prerecorded brain neurochemicals, we experimentally show that C–PCR can achieve CRs as high as ~ 10. As far as hardware implementation is concerned, the experimental results show that reduction rates of 32% to 45% in different FPGA resources can be achieved using C–PCR.

FPGA Realization of Hodgkin-Huxley Neuronal Model.

One of the appealing cases of the neuromorphic research area is the implementation of biological neural networks. The current study offers Multiplierless Hodgkin-Huxley Model (MHHM). This modified model may reproduce various spiking behaviors, like the biological HH neurons, with high accuracy. The presented modified model, in comparison to the original HH model, due to its exact similarity to the original model, has more top performances in the case of FPGA saving and more achievable frequency (speed-up). In this approach, the proposed model has a 69 % saving in FPGA resources and also the maximum frequency of 85 MHz that is more than other similar works. In this modification, all spiking behaviors of the original model have been generated with low error calculations. To validate the MHHM neuron, this proposed model has been implemented on digital hardware FPGA. This approach demonstrates that the original HH model and the proposed model have high similarity in terms of higher performance and digital hardware cost reduction.