FPGA Prototype Research Articles

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors

Modern multicore systems are migrating from homogeneous systems to heterogeneous systems with accelerator-based computing in order to overcome the barriers of performance and power walls. In this trend, FPGA-based accelerators are becoming increasingly attractive, due to their excellent flexibility and low design cost. In this paper, we propose the architectural support for efficient interfacing between FPGA-based multi-accelerators and chip-multiprocessors (CMPs) connected through the network-on-chip (NoC). Distributed packet receivers and hierarchical packet senders are designed to maintain scalability and reduce the critical path delay under a heavy task load. A dedicated accelerator chaining mechanism is also proposed to facilitate intra-FPGA data reuse among accelerators to circumvent prohibitive communication overhead between the FPGA and processors. In order to evaluate the proposed architecture, a complete system emulation with programmability support is performed using FPGA prototyping. Experimental results demonstrate that the proposed architecture has high-performance, and is light-weight and scalable in characteristics.

Application of Machine Learning Techniques in Post-Silicon Debugging and Bug Localization

As the size of hardware (HW) design increases significantly, a huge amount of data is generated during the design simulation, emulation or prototyping. Debugging large HW designs becomes a tedious, time consuming and a bottleneck task within the function verification activities. This paper proposes the utilization of machine learning techniques to automate the diagnosis of design trace dump as well as helping in bug localization during post-silicon validation. Our framework starts by signal selection algorithm that identifies which signals to monitor during design execution. Signal selection depends on signal types as well as their connectivity network. The design is then executed and the trace dump is saved for offline analysis. Big-Data processing technique, namely, Map-Reduce is used to overcome the challenge of processing huge trace dump resulted from design running on FPGA prototype. K-means Clustering method is applied to group trace segments that are very similar and to identify the ones with a rare occurrence during the design execution. Additionally, we propose a bug localization framework in which X-means clustering is used to group the passing regression tests in clusters such that buggy tests can be detected when they fail to be assigned to any of the trained clusters. Our experimental results demonstrate the feasibility of the proposed approach in guiding the debugging effort using a group of industrial HW designs and its ability to detect multiple design injected defects using mutation-based-testing method.

FPGA Prototype and Real Time Analysis of Multiuser Variable Rate CI-GO-OFDMA

The narrow-band-IoT and other higher standards require efficient multiple access schemes that allow more number of users using variable rates to achieve a low peak-to-average power ratio (PAPR) and resistance against deep fades. In this paper, a multicarrier scheme is proposed that supports multiuser with variable rates based on carrier interferometry (CI) codes, i.e., CI-group orthogonal–orthogonal frequency-division multiple access (CI-GO-OFDMA). The bit-error-rate performance of the proposed scheme is carried out on the third-generation partnership project standardized pedestrian channel. Furthermore, a new architecture is designed and an efficient methodology is developed for the proposed scheme, which is prototyped on the commercially available virtex5 FPGA device for real-time analysis. The PAPR performance for the proposed scheme in the MATLAB simulation as well as in the fixed point hardware is compared and found almost the same, which justifies its significance. The challenging issue lies in the real-time testing and analyzing the baseband CI-GO-OFDMA signal from the digital-to-analog converter on the spectrum analyzer and the mixed signal oscilloscope in the laboratory experimental setup. Measurements like the experimental error of the FPGA prototype, occupied bandwidth, main lobes channel power, and side lobes channel power are reported to study the behavior of the scheme in the real-time scenario.

Data Compression Device Based on Modified LZ4 Algorithm

Data compression is commonly used in NAND flash-based solid state drives (SSDs) to increase their storage performance and lifetime as it can reduce the amount of data written to and read from NAND flash memory. Software-based data compression reduces SSD performance significantly and, as such, hardware-based data compression designs are required. This paper studies the latest lossless data compression algorithm, i.e., the Lempel-Ziv (LZ)4 algorithm which is one of the fastest compression algorithms reported to date. A data compression FPGA prototype based on the LZ4 lossless compression algorithm is studied. The original LZ4 compression algorithm is modified for real-time hardware implementation. Two hardware architectures of the modified LZ4 algorithm (MLZ4) are proposed with both compressors and decompressors, which are implemented on an FPGA evaluation kit. The implementation results show that the proposed compressor architecture can achieve a high throughput of up to 1.92 Gb/s with a compression ratio of up to 2.05, which is higher than all previous LZ algorithm designs implemented on FPGAs. The compression device can be used in high-end SSDs to further increase their storage performance and lifetime.

Digital pulse-width modulator with spread-spectrum emission reduction

Pulse-width modulated power-stages are used in many power-electronic applications because of their high efficiency. They are known to be a root cause for electromagnetic emission problems if no countermeasures are taken. This work presents a digital pulse-width modulator with an emission reduction method based on spread-spectrum modulation techniques. The proposed method is analyzed in detail, and two possible digital implementations are discussed. The implementations are compared in terms of chip-area and power consumption. Finally, an application of the proposed digital pulse-width modulator in a digitally-controlled Class-D audio amplifier is presented to show the feasibility of the concept. Using an FPGA prototype, a measured emission reduction of up to 9.5 dB is achieved.

Тестирование производительности ПЛИС-прототипа встроенного контроллера Гигабитного Ethernet при работе с TCP

Тестирование производительности ПЛИС-прототипа встроенного контроллера Гигабитного Ethernet при работе с TCP

Inter-Technology Backscatter

We introduce inter-technology backscatter, a novel approach that transforms wireless transmissions from one technology to another, on the air. We show for the first time that Bluetooth transmissions can be used to create Wi-Fi and ZigBee-compatible signals using backscatter communication. Since Bluetooth, Wi-Fi and ZigBee radios are widely available, this enables a backscatter design that works using only commodity devices. We build an FPGA prototype that creates 2'11 Mbps Wi-Fi or Zigbee packets by backscattering Bluetooth transmissions. We use this to demonstrate previously infeasible applications including the first contact lens form-factor antenna prototype and implantable neural recording interface that communicate directly to commodity devices, such as smartphones, thus enabling the vision of Internet-connected implanted devices

A Secure Phase-Encrypted IEEE 802.15.4 Transceiver Design

With the proliferation of Internet of Things (IoT), the IEEE 802.15.4 physical layer is becoming increasingly popular due to its low power consumption. However, secure data communication over the network is a challenging issue because vulnerabilities in the existing security primitives lead to several attacks. The mitigation of these attacks separately adds significant computing burden on the legitimate node. In this paper, we propose a secure IEEE 802.15.4 transceiver design that mitigates multiple attacks simultaneously by using a physical layer encryption approach that reduces the computations at the upper layers. In addition to providing confidentiality and integrity services, the proposed transceiver provides sufficient complexity to various attacks, such as cryptanalysis and traffic analysis attacks. It also significantly improves the lifetime of the node in the presence of a ghost attacker by preventing the legitimate node from processing the bogus messages and hence combats against energy depletion attacks. The simulation results show that a high symbol error rate at the adversary can be achieved using the proposed transceiver without affecting the throughput at the legitimate node. In this paper, we also analyze the hardware complexity by developing an FPGA and ASIC prototype of the proposed transceiver.

Sancus 2.0

The Sancus security architecture for networked embedded devices was proposed in 2013 at the USENIX Security conference. It supports remote (even third-party) software installation on devices while maintaining strong security guarantees. More specifically, Sancus can remotely attest to a software provider that a specific software module is running uncompromised and can provide a secure communication channel between software modules and software providers. Software modules can securely maintain local state and can securely interact with other software modules that they choose to trust. Over the past three years, significant experience has been gained with applications of Sancus, and several extensions of the architecture have been investigated—both by the original designers as well as by independent researchers. Informed by these additional research results, this journal version of the Sancus paper describes an improved design and implementation, supporting additional security guarantees (such as confidential deployment) and a more efficient cryptographic core. We describe the design of Sancus 2.0 (without relying on any prior knowledge of Sancus) and develop and evaluate a prototype FPGA implementation. The prototype extends an MSP430 processor with hardware support for the memory access control and cryptographic functionality required to run Sancus. We report on our experience using Sancus in a variety of application scenarios and discuss some important avenues of ongoing and future work.

Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore Architectures

With computing systems becoming ubiquitous, numerous data sets of extremely large size are becoming available foranalysis. Often the data collected have complex, graph based structures, which makes them difficult to process with traditional tools. Moreover, the irregularities in the data sets, and in the analysis algorithms, hamper the scaling of performance in large distributedhigh-performance systems, optimized for locality exploitation and regular data structures. In this paper we present an approach tosystem design that enable efficient execution of applications with irregular memory patterns on a distributed, many-core architecture, based on off-the-shelf cores. We introduce a set of hardware and software components, which provide a distributed global address space, fine-grained synchronization and latency hiding of remote accesses with multithreading. An FPGA prototype has been implemented to explore the design with a set of typical irregular kernels. We finally present an analytical model that highlights the benefits of the approach and helps identifying the bottlenecks in the prototype. The experimental evaluation on graph basedapplications demonstrates the scalability of the architecture for different configurations of the whole system.

Efficient task spawning for shared memory and message passing in many-core architectures

Abstract Modern many-core systems consist of large number of processing cores and introduce more and more parallelism. The (PGAS) programming model is a popular approach for exploiting this parallelism of architectures while offering flexibility of both shared memory and message passing paradigms. On the architecture design front, (NoCs) have become an integral part of the communication infrastructure due to their good scalability. In order to exploit task level parallelism on modern many-core architectures, the applications spawn more and more tasks to the available computing resources. The applications require less communication and synchronization delays for better performance. However, the distributed nature of NoCs poses a challenge to keep data communication and synchronization latency within the desired bound and hence results in higher task spawning overhead. We proposed an approach based on hardware-assisted task spawning on many-core systems [1]. In the current article, we present an extended version of our work for hardware-managed task spawning, keeping in view the communication requirements of both shared memory and message passing programming models. The proposed hardware support, integrated into the network interface architecture, reduces the synchronization overhead for task spawning. The software is offloaded from task spawning which results in an increase in the overall performance. The simulation results highlight that the proposed task spawning approach improves the overall performance up to 40% in comparison to an existing state-of-the-art approach [2]. To underline the applicability, we implemented an FPGA prototype to investigate real world applications. The investigations show that the proposed concept offers a low overhead in terms of implementation area cost on FPGA and ASIC platforms.

Emulation of an ASIC power and temperature monitoring system (eTPMon) for FPGA prototyping

Hardware monitoring information can be used during system runtime to increase system lifetime and reliability. Examples of such monitoring information are power, temperature, and the aging status of processors. They provide the system with relevant information about the current hardware health. Such information is especially crucial in resource-aware computing concepts that introduce self-organizing behavior to deal with large MPSoCs (Multi-Processor Systems-on-Chip): For resource-aware computing, resources are allocated according to the current requirements. To find suitable resource-application pairs and achieve system targets like optimizing the utilization, current hardware status must be considered during resource allocation.To evaluate and optimize resource allocation strategies during the design phase, FPGA prototyping is often required before its implementation in ASIC. The evolution of power, temperature and aging differ between ASIC implementation and FPGA prototype. The FPGA prototype should react on sensor data characterized from the target ASIC design instead of FPGA’s hardware status.This paper describes the design of an emulated ASIC Temperature and Power Monitoring system (eTPMon) for FPGA-based prototyping. The emulation approach for power monitors is based on an instruction-level energy model. For emulating temperature monitors, a thermal RC model is used.eTPMon can supply MPSoC prototypes with the hardware status information (power and temperature of the cores) needed for efficient load distribution, achieving resource-aware computing targets. Based on the eTPMon data, different operating strategies and control targets were evaluated for a 2-tile resource-aware MPSoC system. Values provided by eTPMon are usable for extracting information about the aging of processors, which can be used for increasing the system lifetime.

Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD

A novel multi-ASIP and network-on-chip (NoC) based flexible architecture for parallel iterative demapping with turbo decoding using signal space diversity (TBICM-ID-SSD) is presented in this brief. The proposed heterogeneous multi-ASIP architecture uses multiple instances of two types of application-specific instruction-set processor (ASIP): one dedicated for turbo decoding and the second for demodulation, besides butterfly-topology-based NoCs. This architecture presents novel and outstanding levels of flexibility and scalability in the design of advanced iterative receivers. It supports modulation schemes from BPSK to 256-QAM for any mapping style and supports 8 state single and double binary turbo codes used in 3GPP-LTE, DVB-RCS, and WiMAX. FPGA prototyping results are presented, and the extra hardware cost required to enable turbo demodulation is evaluated.

A microcontroller multicore in FPGAs: detailed architecture and case studies of embedded critical applications

This paper presents the concept and preliminary tests in FPGA of architecture for a flexible multicore microcontroller. It is aimed at intermediate complexity embedded applications. A previous exact characterisation of the microcontroller model and its target applications is a costly-time task, and depends mostly on the engineers' and programmers' experiences. The proposed architecture can aid the development of new applications, since it allows the selection of hardware components useful to the project during the development of the application. We have designed a prototype in FPGA and it is working with seven CPUs. We have used two applications (PID controllers and AES security algorithm), and our results allow to validate the idea and utility of multicore microcontrollers.

A microcontroller multicore in FPGAs: detailed architecture and case studies of embedded critical applications

This paper presents the concept and preliminary tests in FPGA of architecture for a flexible multicore microcontroller. It is aimed at intermediate complexity embedded applications. A previous exact characterisation of the microcontroller model and its target applications is a costly-time task, and depends mostly on the engineers' and programmers' experiences. The proposed architecture can aid the development of new applications, since it allows the selection of hardware components useful to the project during the development of the application. We have designed a prototype in FPGA and it is working with seven CPUs. We have used two applications (PID controllers and AES security algorithm), and our results allow to validate the idea and utility of multicore microcontrollers.

A VLSI architecture of CORDIC-based popular windows and its FPGA prototype

Popular window technique such as Hamming, Hanning, Blackman, Blackman-Harris and flat top windows are an obvious choice before fast-Fourier-transform (FFT) in the domain of signal processing, communication system and image processing to minimise the undesirable phenomenon, i.e., spectral leakage and picket fence effect arise due to direct truncation by rectangular window. As the window characteristics depends upon the type of the function and length of window used, hence, this is necessary to choose a particular window function and window length depending upon the applications. In other hand, real-time implementation of window function demands efficient and flexible very-large-scale-integration (VLSI) architecture. Hence, this paper presents a new hardware efficient coordinate-rotation-digital-computer (CORDIC)-based VLSI architecture which is capable of reconfigurability to choose a window function among aforesaid popular window functions and window length ranging from 8 to 32 K (215), depending upon the application. Further, this proposed architecture is prototyped on FPGA for real-time validation and implementation results have been highlighted along with error analysis.

A VLSI architecture of CORDIC-based popular windows and its FPGA prototype

A VLSI architecture of CORDIC-based popular windows and its FPGA prototype

Efficient Security Monitoring with the Core Debug Interface in an Embedded Processor

For decades, various concepts in security monitoring have been proposed. In principle, they all in common in regard to the monitoring of the execution behavior of a program (e.g., control-flow or dataflow) running on the machine to find symptoms of attacks. Among the proposed monitoring schemes, software-based ones are known for their adaptability on the commercial products, but there have been concerns that they may suffer from nonnegligible runtime overhead. On the other hand, hardware-based solutions are recognized for their high performance. However, most of them have an inherent problem in that they usually mandate drastic changes to the internal processor architecture. More recent ones have strived to minimize such modifications by employing external hardware security monitors in the system. However, these approaches intrinsically suffer from the overhead caused by communication between the host and the external monitor. Our solution also relies on external hardware for security monitoring, but unlike the others, ours tackles the communication overhead by using the core debug interface (CDI), which is readily available in most commercial processors for debugging. We build our system simply by plugging our monitoring hardware into the processor via CDI, precluding the need for altering the processor internals. To validate the effectiveness of our approach, we implement two well-known monitoring techniques on our proposed framework: dynamic information flow tracking and branch regulation. The experimental results on our FPGA prototype show that our external hardware monitors efficiently perform monitoring tasks with negligible performance overhead, mainly with thanks to the support of CDI, which helps us reduce communication costs substantially.

FPGA Prototyping of Single-Polarization 112-Gb/s Transceiver for Optical Multilevel Signaling With Intensity and Delay Detection

As the proof-of-concept of a next-generation 100-Gb/s/channel high-speed optical transceiver for short- to mid-range applications, we develop a first full-rate and fully-functional FPGA-based single-polarization 16APSK/16QAM transceiver prototype using optical delay- and intensity-detection. Almost all the major transceiver functions, such as multilevel modulation/demodulation, timing recovery, framing functions with FEC, and linear equalizers are implemented into eight FPGAs, and the feasibility of the proposed transceiver with small circuit size and low power consumption is confirmed. Various compensation functions previously reported for the performance improvement of the delay-detection-based multilevel signaling, such as Rx-side phase noise, chromatic dispersion canceling circuits, compensation of unbalance of balanced photodetectors, symbol decision with non-Euclidian metric, etc., are also implemented in the real-time transceiver for the first time. In this paper, its basic concept, FPGA implementation, real-time signal demodulation, and BER performances are shown and four-channel WDM (448 Gb/s) field trial over 18.2-km SMF is also demonstrated.

낮은 복잡도의 Deeply Embedded 중앙처리장치 및 시스템온칩 구현

Abstract This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embeddedsystems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, externalmemory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASICfront-end gate netlist level using a 0.18μm digital CMOS technology with 1.8V supply, resulting in a gate count ofmerely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and appliedto deeply embedded IoT applications.