Artix-7 FPGA Research Articles

Unsupervised deep learning framework for temperature-compensated damage assessment using ultrasonic guided waves on edge device

Fueled by the rapid development of machine learning (ML) and greater access to cloud computing and graphics processing units, various deep learning based models have been proposed for improving performance of ultrasonic guided wave structural health monitoring (GW-SHM) systems, especially to counter complexity and heterogeneity in data due to varying environmental factors (e.g., temperature) and types of damages. Such models typically comprise of millions of trainable parameters, and therefore add to cost of deployment due to requirements of cloud connectivity and processing, thus limiting the scale of deployment of GW-SHM. In this work, we propose an alternative solution that leverages TinyML framework for development of light-weight ML models that could be directly deployed on embedded edge devices. The utility of our solution is illustrated by presenting an unsupervised learning framework for damage detection in honeycomb composite sandwich structure with disbond and delamination type of damages, validated using data generated by finite element simulations and experiments performed at various temperatures in the range 0–90 °C. We demonstrate a fully-integrated solution using a Xilinx Artix-7 FPGA for data acquisition and control, and edge-inference of damage. Despite the limited number of features, the lightweight model shows reasonably high accuracy, thereby enabling detection of small size defects with improved sensitivity on an edge device for online GW-SHM.

High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator

Unpredictable true random numbers are required in security technology fields such as information encryption, key generation, mask generation for anti-side-channel analysis, algorithm initialization, and so on. At present, the true random number generator (TRNG) is not enough to provide fast random bits by low-speed bits generation. Therefore, it is necessary to design a faster TRNG. This work presents an ultra-compact TRNG with high throughput based on a novel extendable dual-ring oscillator (DRO). Owing to multiple bits output per cycle in DRO can be used to obtain the original random sequence, the proposed DRO achieves a maximum resource utilization to build a more efficient TRNG, compared with the conventional TRNG system based on ring oscillator (RO), which only has a single output and needs to build multiple groups of ring oscillators. TRNG based on the 2-bit DRO and its 8-bit derivative structure has been verified on Xilinx Artix-7 and Kintex-7 FPGA under the automatic layout and routing and has achieved a throughput of 550 Mbps and 1,100 Mbps, respectively. Moreover, in terms of throughput performance over operating frequency, hardware consumption, and entropy, the proposed scheme has obvious advantages. Finally, the generated sequences show good randomness in the test of NIST SP800-22 and Dieharder test suite and pass the entropy estimation test kit NIST SP800-90B and AIS-31.

Modified restoring array-based power efficient approximate square root circuit and its application

In this paper, the authors present an investigation into the benefits of approximate computing in energy-efficient error-resilient applications. It proposes an approximate square root (SQR) circuit based on the modified restoring array square root (MRAS) architecture. The MRAS design incorporates strategic elimination, optimization, and simplification of restoring subtractor cells (SC) within a conventional restoring array SQR circuit. As a result, the proposed MRAS circuit efficiently computes the square root of a 2n-bit unsigned integer, offering a 27 percent reduction in area, 13 percent faster computation, and 50 percent lower power consumption compared to the exact SQR design. To introduce approximation, configurable SCs are integrated into the MRAS circuit, enabling dual operation modes for both accuracy and approximation. This feature allows the proposed approximate modified restoring array SQR (AMRAS) design to cater to both error-resilient and error-sensitive applications. The evaluation involves a thorough analysis of accuracy and design metrics for 16-bit unsigned exact, state-of-the-art, and proposed square rooters. The designs are implemented on Artix7 FPGA using Verilog-HDL and simulated in the Xilinx Vivado simulator. The results demonstrate that the proposed AMRAS achieves a good trade-off between accuracy and hardware, presenting an impressive 80 percent reduction in power consumption and a 36 percent faster computation. Additionally, the paper showcases the practical application of the proposed AMRAS square rooters in the Sobel edge detection for image processing.

Machine learning attacks resistant strong PUF design utilizing response obfuscates challenge with lower hardware overhead

Physical unclonable function (PUF) is a hardware security primitive with significant application potential. However, strong PUF is vulnerable to machine learning attacks based on modeling attacks. Although various resistance techniques have been proposed, strong PUF suffers from deficiencies in its resistance to machine learning attacks, hardware overhead, and reliability. This study proposes a highly reliable and secure lightweight PUF that complicates the original challenge using an internal response. Specifically, the internal response is used to determine the odd/even bit flip or left/right cyclic shift of the original challenge to achieve preliminary obfuscation, and byte substitution that exploits an S-box is performed on the preliminary obfuscated challenge to achieve deep nonlinear obfuscation. Experimental results on a Xilinx Artix-7 FPGA show that the proposed PUF is not only highly resistant to machine learning (ML) attacks but also has a low hardware overhead. An arbiter PUF(APUF), which uses the proposed obfuscated scheme with a 64-bit challenge length, was evaluated by three advanced machine learning algorithms with up to 600,000 challenge–response-pairs (CRPs) in the dataset, and the observed prediction accuracy was less than 56 %. Moreover, the PUF is unique, reliable, and has a significantly lower hardware overhead than other prior anti-attack PUFs.

Phased array antenna controlled by FPGA-ARM Cortex-M Processor

This paper discusses the architecture of an adaptive transmitting antenna array that allows highly flexible beamsteering. Antenna arrays are used in many digital signal processing applications due to their ability to locate signal sources. The Direction of Arrival (DOA) estimation is a key task of array signal processing, with the Taguchi method and Multiple Signal Classification (MUSIC). Although various algorithms have been developed for DOA estimation, their high complexity prevents their use in real-time applications. In this paper, we design and develop an implementation using Field Programmable Gate Array (FPGA Artix-7), which is the most widely used ARM processor in embedded systems. The antenna array is digitally controlled with the phases synthesized by the Taguchi method.

Algorithm-Hardware Co-Design of Split-Radix Discrete Galois Transformation for KyberKEM

KyberKEM is one of the final round key encapsulation mechanisms in the NIST post-quantum cryptography competition. Number theoretic transform (NTT), as the computing bottleneck of KyberKEM, has been widely studied. Discrete Galois Transformation (DGT) is a variant of NTT that reduces transform length into half but requires more multiplication operations than the latest NTT algorithm in theoretical analysis. This paper proposes the split-radix DGT, a novel DGT variant utilizing the split-radix method, to reduce the computing complexity without compromising the transform length. Specifically, for length-128 polynomial, the split-radix DGT algorithm saves at least 10% multiplication operations compared with the latest NTT algorithm in theoretical analysis. Furthermore, we proposed a unified split-radix DGT processor with the dedicated stream permutation network for KyberKEM and implemented it on the Xilinx Artix-7 FPGA. The processor achieves at least 49.4% faster transformation and 65.3% faster component-wise multiplication, with at most 87% and 32% LUT-NTT area-time product and LUT-CWM area-time product, compared with the state-of-the-art polynomial multipliers in KyberKEM with the same BFU setting on similar platforms. Lastly, we designed a highly efficient KyberKEM architecture using the proposed split-radix DGT processor. The implementation results on Artix-7 FPGA show significant performance improvements over the state-of-the-art KyberKEM designs.

FOM-CDS PUF: A Novel Configurable Dual State Strong PUF Based on Feedback Obfuscation Mechanism against Modeling Attacks

The configurable Ring oscillator Physical unclonable function (CRO PUF) is the newly proposed strong PUF based on classic RO PUF, which can generate exponential Challenge-Response Pairs (CRPs) and has good uniqueness and reliability. However, existing proposals have low hardware utilization and vulnerability to modeling attacks. In this paper, we propose a Novel Configurable Dual State (CDS) PUF with lower overhead and higher resistance to modeling attacks. This structure can be flexibly transformed into RO PUF and TERO PUF in the same topology according to the parity of the Hamming Weight (HW) of the challenge, which can achieve 100% utilization of the inverters and improve the efficiency of hardware utilization. A feedback obfuscation mechanism (FOM) is also proposed, which uses the stable count value of the ring oscillator in the PUF as the updated mask to confuse and hide the original challenge, significantly improving the effect of resisting modeling attacks. The proposed FOM-CDS PUF is analyzed by building a mathematical model and finally implemented on Xilinx Artix-7 FPGA, the test results show that the FOM-CDS PUF can effectively resist several popular modeling attack methods and the prediction accuracy is below 60%. Meanwhile it shows that the FOM-CDS PUF has good performance with uniformity, Bit Error Rate at different temperatures, Bit Error Rate at different voltages and uniqueness of 53.68%, 7.91%, 5.64% and 50.33% respectively.

Modeling-Attack-Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability

This article presents an obfuscated-interconnection physical unclonable function (OIPUF) to resist modeling attacks. By introducing nonlinear operations through exploiting the random interconnections of delay stages, the proposed OIPUF can theoretically improve the PUF security while consuming the same hardware resources as the conventional XOR Arbiter PUF (XOR APUF). We further propose the metastability-detection (MD) arbiter to effectively improve the PUF reliability. Implemented on Xilinx Artix-7 FPGA, both the proposed (64,4)-and (64,8)-OIPUF demonstrate a good reliability and uniformity, with the proposed (64,8)-OIPUF showing a better uniqueness and strict avalanche criterion (SAC) performance. Measurement results also show that the proposed MD arbiter can reduce the bit error rate (BER) of the (64,4)-and (64,8)-OIPUF by.68 and.48 at up to 100.C, respectively. Evaluated using the Logistic Regression (LR), Artificial Neural Network (ANN), and Covariance Matrix Adaptation-Evolution Strategy (CMAES) machine learning (ML) algorithms, the proposed (64,4)-and (64,8)-OIPUF can achieve a worst case prediction accuracy of 61.47% and 50.59% with up to 10M CRPs as training set, respectively, demonstrating a significant improvement over similar prior arts.

A Digital Controller for Reactivity Monitoring and Power Control

This paper introduces a controller unit for reactivity monitoring and automatic power control that was designed and constructed for the 500 kW Dalat Nuclear Research Reactor (DNRR). For power control and reactivity calculations, frequency signals from neutron measurement channels of starting and working ranges of the reactor are used. Two abovementioned independent functions were combined in an Artix-7 FPGA board for determining reactivity values by solving the point reactor kinetics equations with six delayed neutron groups and for stabilizing the reactor power at preset levels by determining the unbalance voltage signal to control the automatic control rod. With real-time calculations, the newly developed controller can monitor the reactor reactivity and control the reactor power online. The developed controller unit’s reactivity measuring and power stabilizing capabilities were assessed using the DNRR in normal operation and assumed emergency conditions and compared with those of the preexisting imported BNO-102R1 module of the DNRR control and protection system, known as ASUZ-14R. The results of the experiments show that the produced FPGA-based unit and the BNO-102R1 unit have the same technical characteristics and features, with the disparities being less than 5% and 1%, respectively, in reactivity measurement and power stabilization. The experimental data of reactivity measurements by the FPGA-based unit and the calculation results were also compared and found that the relative deviations between those are also less than 10%. The developed controller unit is capable of carrying out a variety of training and operational experiments on the DNRR.

Oil and Vinegar: Modern Parameters and Implementations

Two multivariate digital signature schemes, Rainbow and GeMSS, made it into the third round of the NIST PQC competition. However, neither made its way to being a standard due to devastating attacks (in one case by Beullens, the other by Tao, Petzoldt, and Ding). How should multivariate cryptography recover from this blow? We propose that, rather than trying to fix Rainbow and HFEv- by introducing countermeasures, the better approach is to return to the classical Oil and Vinegar scheme. We show that, if parametrized appropriately, Oil and Vinegar still provides competitive performance compared to the new NIST standards by most measures (except for key size). At NIST security level 1, this results in either 128-byte signatures with 44 kB public keys or 96-byte signatures with 67 kB public keys. We revamp the state-of-the-art of Oil and Vinegar implementations for the Intel/AMD AVX2, the Arm Cortex-M4 microprocessor, the Xilinx Artix-7 FPGA, and the Armv8-A microarchitecture with the Neon vector instructions set.

Fault-tolerant reversible logic gate-based RO-PUF design

Physically Unclonable Function (PUF) is an emerging modern approach to the security concerns of the physical systems which require the protection of sensitive data. PUF generates unique, reliable, and secure responses which can be utilized for cryptographic applications. In this paper, a fault-tolerant reversible logic gate-based RO PUF is proposed. We utilized a fault-tolerant reversible logic Double Feynman Gate in place of conventional inverters to design the ring oscillators (RO). The proposed RO PUF designs implemented and evaluated on the Basys-3 Artix-7 FPGA board. The PUF parameters such as uniqueness, reliability, and uniformity were analyzed based on the experimental results. The empirical results show that the proposed RO PUF has uniqueness and reliability of 0.49 and 85.95%, respectively. The inter-chip and intra-chip uniqueness for the proposed design is 23% and 25.5%, respectively higher than the conventional RO PUF design. This fault-tolerant reversible logic gate-based RO PUF design shows better uniqueness, reliability, and uniformity than other considered PUF designs.

An Encryption Application and FPGA Realization of a Fractional Memristive Chaotic System

The work in this paper extends a memristive chaotic system with transcendental nonlinearities to the fractional-order domain. The extended system’s chaotic properties were validated through bifurcation analysis and spectral entropy. The presented system was employed in the substitution stage of an image encryption algorithm, including a generalized Arnold map for the permutation. The encryption scheme demonstrated its efficiency through statistical tests, key sensitivity analysis and resistance to brute force and differential attacks. The fractional-order memristive system includes a reconfigurable coordinate rotation digital computer (CORDIC) and Grünwald–Letnikov (GL) architectures, which are essential for trigonometric and hyperbolic functions and fractional-order operator implementations, respectively. The proposed system was implemented on the Artix-7 FPGA board, achieving a throughput of 0.396 Gbit/s.

IMPLEMENTATION FPGA BASED IMPLEMENTATION OF 128-BIT AES ALGORITHM USING VHDL

In current world of computations, data encryption is of prominent importance. Many algorithms were developed for data encryption and decryption to prevent hacking. The Advanced Encryption Standard (AES) is one of the data encryption techniques. Two famous kinds of hardware implementation techniques are pipelining and loop-unrolling techniques. In pipelining, registers are inserted between each combinational processing element so that each input data block can be processed simultaneously in each processing element. In this work, a pipelined implementation of AES encryption algorithm is developed. The number of rounds of AES-128 encryption is 10 and an architecture implementing this cipher is called fully pipelined, when all data blocks of 10 rounds can be processed simultaneously. In the loop-unrolling technique one or multiple rounds of the algorithm are processed in the same clock cycle. Here only one round of the algorithm is implemented as a combinational processing element and a data register is also used to store the result obtained in the previous clock cycle. In this work, a128-bit AES is implemented and for each round of AES encryption, a different sub-key is used as the round key, which is produced by the key schedule algorithm based on the loop-unrolled technique, to produce the required sub-key for each round is done. The no of I/O, Slices in the proposed work are 386, 229 respectively with Spartan6 fpga with a minimum period of 5.813ns,maximum Frequency of 172.031MHz, minimum input arrival time before clock of 4.823ns,maximum output required time after clock of 5.588ns, throughput of 2.2Gbps. The no of I/O, Slices are 387, 264 respectively with Artix7 fpga with a minimum period of 3.397ns, maximum Frequency of 294.366MHz, minimum input arrival time before clock of 1.649ns, maximum output required time after clock of 1.669ns, throughput of 3.77Gbps.

A Novel Design of Hilbert Huang Based All Digital Phase Locked Loop Using FPGA

Many applications for digital processing are steadily increasing in radio frequency signal processing from analog to digital. ADPLL plays a vital role in digital signal processing. Several ADPLL models were introduced in the past. However, in those models, the power dissipation gets increased due to the delay in the lock state. Due to the generated digital noise, the system leads the output signal with inherent phase noise and does not undergo the frequency division process. Therefore, a novel Hilbert-Huang based All Digital Phase Locked Loop (HH-ADPLL) was proposed to make the ADPLL into the locked state. The input reference signal is initially entered in the Hilbert-Huang transform to extract the analytic component and generate the up and down signals. By eliminating the higher frequency part from these signals, the up/down counter produces borrow and carry signals. The carry and borrow signals are fed into the increment decrement counter to produce the output signal. At last, input and output signal matching is carried out in the phase detector module, and ADPLL enters a locked state. The presented HH-ADPLL is implemented in Artix-7 FPGA, and the efficiency is validated in terms of stability, phase error, power dissipation, combinational delay, and performance improvement computed.

FPGA Implementation of Enhanced Montgomery Modular for Fast Multiplication

This Paper proposed an enhanced Montgomery and efficient implementation of Modular Multiplication. Cryptographyoprocess is usedufor providingphigh informationmsecurity when a data is transferredmfrom transmitter to receiver. Various using methods like RSA, ECC, the Digital Signature Algorithm. The propose Montgomery algorithm usin RSA algorithim of cryptography is implemented in two different input both the inputs are 8 bit input. Coding have been done in Verilog language and the results are simulated on Vivado Software. For physical testing, we have used an FPGA NESYS 4 DDR hardware board that have Artix-7 FPGA chip on it produced by digilent company. The propose method shows good results in term of the number of slice flip flop, LUTs, and number of IOBs and power consumption. The proposed method shows better results as compare to other previous methods in term of different result parameters.

Design of RISC Processor with IEEE754 Standard Floating-Point Instruction Set in FPGA using VHDL for Digital Signal Processing Applications

The design of RISC processors, which are the key of digital signal processing applications, are increasing in reconfigurable hardware. FPGAs are suitable reconfigurable hardware for RISC processor design, with advantages such as parallel processing and low power consumption. In this study, the design of the 32-bit RISC processor in a FPGA is presented. The designed RISC processor contains IEEE754 standard floating-point number processing unit, which is executed in a one clock cycle. The verification of the processor is performed for the Zynq-7000 SoC Artix-7 FPGA chip in the Xilinx Vivado tool. Classification of an artificial neural network using the iris dataset is carried out in this designed RISC processor. In order to compare the performance, the same artificial neural network is executed in real time within the dual-core ARM Cortex-A9 processor in the operating system of the Zynq-7000 SoC. The results show that the RISC processor designed in the FPGA executes at 20x less clock cycles and 3x higher speed compared to the ARM processor.

Stabilizing Techniques for Secure On-chip Key Generation Based on RO-PUF

Based on intrinsic physical characteristics of devices, Physically Unclonable Functions (PUFs) provide the high reliability while maintaining the sufficient uniqueness. However, in the practical implementation based on PUFs, the extracted bit-string normally exhibits the unavoidable small fluctuation. Hence, PUFs can be used for the application of chip identification, but not suitable for the application that strictly requires an exact generated number. In this work, we propose several techniques to stabilize the generated value based on the existing Ring Oscillator (RO)-PUF circuit so that the stable unique number can be directly used for high-profile hardware security applications. In detail, we design a specialized on-chip key generation circuit that repeatedly samples the RO frequency values for statistical analysis and dynamically phases out the unstable bits, resulting in a unique and stable output bit-string. The experiments are conducted for the actual data measured from Xilinx Artix-7 FPGA devices. The generated key is proven to be relatively stable and can be readily used for the emerging security applications.

SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident angles

This paper provides an experimental study of the single-event upset (SEU) susceptibility against thermal neutron radiation of a 28-nm bulk Commercial-Off-The-Shelf (COTS) Xilinx Artix-7 FPGA under different angles of incidence. Experimental results indicating SEUs on configuration RAM (CRAM) cells, Flip-Flops (FFs), and Block RAMs (BRAMs) are presented and discussed. Shapes of multiple events (ranging from 2 to 12-bit) are also analyzed, and their dependency on the incident angle of the particle beam against the device's surface. Possible shapes of 128 and 384-bit multiple events are also investigated, revealing a trend to follow word lines. The results of the front incident angle are compared with 14.2-MeV neutrons, demonstrating a considerable difference in the device's sensitivity against both irradiation sources. Finally, a modeling tool called MUSCA-SEP3 is used to predict the device's sensitivity under the same environmental conditions. The obtained experimental results will show a good agreement with the predicted ones in a very accurate way.

RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference

Hyperdimensional (HD) computing is a lightweight machine learning method widely used in Internet of Things applications for classification tasks. Although many hardware accelerators are proposed to improve the performance of HD, they suffer from low flexibility that makes them not practical in most real-life scenarios. To improve the flexibility, an open-source instruction set architecture (ISA) called RISC-V has been employed and extended for a specific application such as machine learning. This article aims to improve the efficiency and flexibility of HD computing for resource-constrained applications. To this end, we extend a RISC-V core (RI5CY) for HD computing called RISC-HD. First, to reduce the computational overhead at the HD inference phase, we introduce a pruning method to remove the ineffectual dimensions. The proposed pruning method can reduce the dimension from 10k to 1k with negligible accuracy loss. Second, an ISA extension for RI5CY is proposed to compute the HD inference efficiently. Experimental results indicate that RISC-HD adds <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.42\times $ </tex-math></inline-formula> area overhead to the RI5CY core; however, it consumes only 2932 slices on the Artix-7 FPGA, which is suitable for resource-constrained devices. Additionally, RISC-HD improves the total clock cycle by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.48\times $ </tex-math></inline-formula> compared to the RI5CY core and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.17\times $ </tex-math></inline-formula> compared to ARM Cortex-M4 in the ISOLET data set. Moreover, RISC-HD achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.22\times $ </tex-math></inline-formula> energy efficiency compared to the RI5CY core.

A 2-GHz Two-Tone Direct Digital Frequency Synthesizer

We present a 2-GHz 16-bit direct digital synthesizer (DDS) implemented and verified on a Xilinx Artix-7 FPGA, Nexys-4 DDR development board. The lookup-table based DDS is implemented with the help of multiplexers in a tree structure. The proposed technique can operate at a high clock frequency of 250 MHz and has no truncation error. The proposed DDS is also capable of producing two tones separated by a frequency resolution of 1/1024 times the clock frequency. Further, the tones can be backed off in approximately one dB step from full scale to −96 dB. The back-off is implemented without performing any real multiplication thereby increasing the throughput. 16 such parallel DDS slices are implemented to produce very high-frequency digital sinusoids. The design uses 3095 LUTs, 3465 flip flops, and 18 Block-RAMs for producing two tone output at 2GHz for a given back-off.