Fourier Transform Processor Research Articles

External Data Systems Enable Enhanced (and Sustainable) Fourier Transform Mass Spectrometry Imaging for Legacy Hybrid Linear Ion Trap-Orbitrap Platforms.

Legacy Fourier transform (FT) mass spectrometers provide robust platforms for bioanalytical mass spectrometry (MS) yet lack the most modern performance capabilities. For many laboratories, the routine investment in next generation instrumentation is cost prohibitive. Field-based upgrades provide a direct path to extend the usable lifespan of MS platforms which may be considered antiquated based on performance specifications at the time of manufacture. Here we demonstrate and evaluate the performance of a hybrid linear ion trap (LTQ)-Orbitrap mass spectrometer that has been enhanced via an external high-performance data acquisition and processing system to provide true absorption mode FT processing during an experimental acquisition. For the application to mass spectrometry imaging, several performance metrics have been improved including mass resolving power, mass accuracy, and dynamic range to provide an FTMS system comparable to current platforms. We also demonstrate, perhaps, the unexpected ability of these legacy platforms to detect usable time-domain signals up to 5 s in duration to achieve a mass resolving power 8× higher than the original platform specification.

A novel hybrid fast Fourier transform processor in 5G+ and bio medical applications

To address the growing demand for real-time and high-performance signal processing, Field-Programmable Gate Array (FPGA) technology provides an influential platform for implementing Fast Fourier Transform (FFT) algorithms. The existing topologies of FFT processors encounters challenges related to high power consumption, limiting their viability for energy-efficient applications. In this research work, a hybrid radix encoder with two-stage operand trimming logarithmic appropriate multiplier and optimized truncated Kogge-stone adder based 2048-point, 4096-point FFT processor for FPGA implementation is designed by focusing on high throughput with minimal consumption of power. This processor is engineered to handle FFTs ranging from 16 to 4096 points catering to both biomedical applications and upcoming 5G technology. The proposed/introduced framework attains a high throughput (78.036 Gbps), and maximum signal to noise ratio (30 dB), low power consumption (26.49 mW), minimum delay (0.12 ns), minimum area (547 μm2), bit error rate (0.1) and minimum execution time (0.223 ms) than the traditional approaches.

Design of high-efficiency complex multiplier for fault-tolerant computation

In this paper, two improved structures and a truncation strategy with compensation for complex multiplication are proposed. Simulation in 28-nm CMOS for hardware performance is provided. Compared to the general complex multiplier, the two accurately improved structures realize 18.58% and 20.80% power consumption reduction, respectively. The truncation strategy with compensation reduces power consumption by 46.8% and controls Mean Relative Error Distance (MRED) at 0.54%. To verify the practicability of the proposed architecture, our designs are applied to the Fast Fourier Transform (FFT) processor to comprehensively evaluate the error characteristics and circuit performance.

Design and Performance Analysis of Short Time Fourier Transform Processor

Abstract: Time-frequency domain characterization of signals have always been focused on variants of Short time Fourier transform (STFT). The selection of transform kernel plays an important role in preserving the signal support which provides a cross-term free time-frequency distribution. Time-Bandwidth product has been taken as a measure of signal support preservation criteria thereby developing an optimal kernel for STFT based on linear canonical decomposition. In the development of kernel , Fractional Fourier Transform (FrFT) is used which provides noise free frequency domain representation .With the help of developed transform kernel , the magnitude-wise shift invariance property is verified and timefrequency content is analyzed by plotting spectrogram. Keywords: STFT, FrFT, kernel, Time-Bandwidth product, spectrogram.

Efficient Cached 64 Point FFT Processor Using Floating Point Arithmetic for OFDM Application

Presently Fourth generation and other wireless systems are focused area for the research and development in the communication field. Fast Fourier Transform (FFT) & Inverse FFT (IFFT) are required for Orthogonal frequency division multiplexing in the integral part of modulation/demodulation modules that occupies more area and power. This paper presents low power and area efficient Cached memory for Fast Fourier Transform (FFT) processor using floating point arithmetic for OFDM application. To store computational permutations each butterfly unit needs one memory. So if considering higher radix of FFT processor, memory requirement increases, it yields to more power consumption and more density occupancy. In this proposed cached 64 point radix 2^6 SDF architecture for reducing the arithmetic hardware complexity of complex multipliers and complex adders present in butterfly structure to obtain low power and less memory requirement. The proposed system is synthesized by using CADENCE RTL COMPLIER and is implemented in ENCOUNTER RTL TO GDSII SYSTEM” using 90nm CMOS technology with a supply voltage of 1V. Synthesis results shows that the proposed design is efficient in terms of gate count, area and power consumption.

Universal Filtered Multicarrier Receiver Complexity Reduction to Orthogonal Frequency Division Multiplexing Receiver

The Universal Filtered Multicarrier (UFMC) waveform technology is one of the promising waveforms for 5G and beyond 5G networks. Owing 2N-point Fast Fourier Transform (FFT) processor at the UFMC receiver, the computational and implementation complexity is two times more than the conventional Orthogonal Frequency Division Multiplexing (OFDM) receiver system. In this paper, we proposed a simplified UFMC receiver structure to reduce computational complexity as well as hardware requirements. The received UFMC symbol simplified exactly to its equivalent after performing 2N-point FFT and decimation operations. In which, the mathematical model of the frequency-domain UFMC signal is rederived after processing through 2N-point FFT and decimator, and the simplified signal is generated with an N-point FFT. Accordingly, the 2N-point FFT processor and decimator are replaced with a single N-point FFT processor. This approach reduces the 50% computational complexity at the FFT processor level hence the hardware and processing time. The computational complexity of the proposed receiver model is approximately equivalent to the OFDM receiver. Additionally, analyzed the mathematical model for the simplified UFMC receiver and the comparative performance of the UFMC system with the conventional model.

Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications

There are several methods to accomplish Fast Fourier Transform and Inverse Fast Fourier Transform processor for multiple inputs multiple output-orthogonal frequency division multiplexing applications. It requires high performance and low power implementation methodologies for reducing the hardware complexity and cost. In conventional fixed point arithmetic calculation is complex to utilize because the dynamic range of computations must be limited in order to overcome overflow and under flow problems. This paper presents floating point arithmetic optimization technique to implement radix-2 butterfly structures for the reduction of complex multipliers presented. Implementations of 32 bit floating point multiplier and floating point adder are presented by using single precision and compare the synthesis results with conventional system. In order to reduce the error we used floating point arithmetic for the butterfly structure. Energy efficient multiplier based on modified booth algorithm is used in radix-2 butterflies. By adopting this architecture the FFT/IFFT implementation using Xilinx FPGA Vertex-7 will improve the 25% logic utilization and the reduction in space utilization. Using arithmetic reduction the power delay product for radix 2 butterfly is reduced by 2.5% compared to normal implementation.

An FPGA-Based Four-Channel 128k-Point FFT Processor Suitable for Spaceborne SAR

Spaceborne synthetic aperture radar (SAR) plays an important role in many fields of national defense and the national economy, and the Fast Fourier Transform (FFT) processor is an important part of the spaceborne real-time SAR imaging system. How to meet the increasing demand for ultra-large-scale data processing and to reduce the scale of the hardware platform while ensuring real-time processing is a major problem for real-time processing of on-orbit SAR. To solve this problem, in this study, we propose a 128k-point fixed-point FFT processor based on Field-Programmable Gate Array (FPGA) with a four-channel Single-path Delay Feedback (SDF) structure. First, we combine the radix-23 and mixed-radix algorithms to propose a four-channel processor structure, to achieve high efficiency hardware resources and high real-time performance. Secondly, we adopt the SDF structure combined with the radix-23 algorithm to achieve efficient use of storage resources. Third, we propose a word length adjustment strategy to ensure the accuracy of calculations. The experimental results show that the relative error between the processor and the MATLAB calculation result is maintained at about 10−4, which has good calculation accuracy.

Area-Efficient Short-Time Fourier Transform Processor for Time–Frequency Analysis of Non-Stationary Signals

In this paper, we propose an area-efficient short-time Fourier transform (STFT) processor that can perform time–frequency analysis of non-stationary signals in real time, which is essential for voice or radar-signal processing systems. STFT processors consist of a windowing module and a fast Fourier transform processor. The length of the window function is related to the time–frequency resolution, and the required window length varies depending on the application. In addition, the window function needs to overlap the input data samples to minimize the data loss in the window boundary, and overlap ratios of 25%, 50%, and 75% are generally used. Therefore, the STFT processor should ideally support a variable window length and overlap ratio and be implemented with an efficient hardware architecture for real-time time–frequency analysis. The proposed STFT processor is based on the radix-4 multi-path delay commutator (R4MDC) pipeline architecture and supports a variable length of 16, 64, 256, and 1024 and overlap ratios of 25%, 50%, and 75%. Moreover, the proposed STFT processor can be implemented with very low complexity by having a relatively lower number of delay elements, which are the ones that increase complexity in the most STFT processors. The proposed STFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using a standard cell library in a 65 nm CMOS process. The proposed STFT processor results in logic gates of 197,970, which is 63% less than that of the conventional radix-2 single-path delay feedback (R2SDF) based STFT processor.

Reconfigurable Superconducting FFT Processor Using Bit-Slice Block Share Processing Unit

We have proposed a reconfigurable high speed and very economical Rapid Single Flux Quantum (RSFQ) superconducting logic design based on the Fast Fourier Transform (FFT) Processor. We have designed a 256 – point FFT processor with the help of a bit-slicing block sharing unit. RSFQ is one of the superconducting device logics comprises of Josephson Junction. The computation complexity of this superconducting FFT is less when the number of points increased. We have proposed three different designs depending on the split radix FFT, the bit-serial radix 2 FFT, and the mixed radix FFT algorithms. The proposed design will slice the 256 – point FFT into eight 32 – point FFT each and each 32 – point FFT is divided into eight 4 – point FFT each for the reduction in hardware cost. For complex multiplication, the computation complexity of our design will be less than N/2 Log2 N for the radix 2 algorithm based on the Block share processing Unit (BSPU) and further, it is reduced for split radix & mixed radix algorithms based on BSPU based RSFQ logic. Due to this, the speed of the processor is improvised compared to general FFT algorithm based semiconductor technology. we have computed and calculated the latency at 10 GHz for our designs. The main aim of this proposed design is to reduce the complex computation time and better performance of the processor with less hardware cost. This proposed design can furthermore continue to several N2 – point by using synchronous clock tree.

The Architectural Optimizations of a Low-Complexity and Low-Latency FFT Processor for MIMO-OFDM Communication Systems

Fast Fourier Transform (FFT) processor is a paramount signal processing component in MIMO-OFDM wireless communication systems. Furthermore, novel applications introduced in 5G incur much more rigorous requirements for FFT designs including complexity, latency, and re-configurability. This paper presents the VLSI architecture design and circuit implementation of a FFT processor that is jointly optimized for low-latency, low-complexity, and configurability. Specifically, the proposed architecture processes two data streams concurrently and supports power-of-two FFT sizes from 64 to 2048 symbols. Moreover, a novel data-processing sequence is presented so that data streams are processed in a time-multiplexing manner and an efficient hardware-sharing architecture can be designed. In addition, a highly efficient I/O reorder mechanism is proposed so that the memory elements are shared between processing stages and the efficiency for utilizing memory components is enhanced. Based on the architectural optimizations, two FFT processors are realized. The ultra-low latency design achieves a latency of 4 μs with 41% area reduction compared to the comparable designs. On the other hand, the ultra-low complexity structure achieves a latency of 25 μs with 24% area reduction compared to the state-of-the-art implementations.

Design and Analysis of Fast Fourier Transform Processors with Various Number Systems

본 논문에서는 고속 푸리에 변환(Fast Fourier Transform; FFT) 프로세서를 설계하고 수 체계(number system) 및 워드 길이(word length)가 FFT 프로세서의 성능 및 비용에 미치는 영향을 분석한다. 수 체계와 FFT의 워드 길이는 FFT 프로세서의 성능에 중요한 요소이다. 따라서 이러한 요소는 FFT 프로세서 설계 시 신중하게 결정되어야 한다. 본 논문에서는 고정 소수점, 블록 부동 소수점 및 부동 소수점 수 체계를 기반으로 64, 256 및 1024 길이의 radix-4 FFT 프로세서를 0.18-μm CMOS 라이브러리를 사용하여 설계하였다. 그리고 수 체계 및 워드 길이의 변화에 따른 FFT 프로세서의 성능 및 비용에 대해 논의한다. 실험 결과, 7-bit 지수 및 18-bit 가수가 부동소수점 FFT 프로세서를 위한 비용 및 성능에 효율적인 워드길이라는 것을 발견하였다.

A Novel Design and Implementation of FBMC Transceiver for Low Power Applications

The complex structure of the Filter Bank Multicarrier (FBMC) communication system is the main drawback affecting the performance of the system and causes a high-power consumption. The complexity arises from using a polyphase filter bank, which consists of fast Fourier Transform/ Inverse Fast Fourier Transform (FFT/IFFT) processors and a filter bank of Finite Impulse Response (FIR) filters. This paper presents the analysis and the implementation of a new design model for FBMC transceiver in which the polyphase filter is removed completely in both transmitter and receiver and uses instead of it, a multi-level cascaded structure of FIR subfilters. The coefficients of each subfilter selected using an optimization algorithm to minimize the amplitude of sidelobes compared to the amplitude of the main lobe in the frequency response of the subfilter. The proposed design reduces the number of multiplications compared to the conventional design by 65%. The field-programmable gate array (FPGA) implementation results indicate that the proposed architecture saves 24% of resources of the FPGA board, works faster, and saves 27% of power consumption compared to conventional FBMC transceiver.

A Novel Design and Implementation of FBMC Transceiver for Low Power Applications

The complex structure of the Filter Bank Multicarrier (FBMC) communication system is the main drawback affecting the performance of the system and causes a high-power consumption. The complexity arises from using a polyphase filter bank, which consists of fast Fourier Transform/ Inverse Fast Fourier Transform (FFT/IFFT) processors and a filter bank of Finite Impulse Response (FIR) filters. This paper presents the analysis and the implementation of a new design model for FBMC transceiver in which the polyphase filter is removed completely in both transmitter and receiver and uses instead of it, a multi-level cascaded structure of FIR subfilters. The coefficients of each subfilter selected using an optimization algorithm to minimize the amplitude of sidelobes compared to the amplitude of the main lobe in the frequency response of the subfilter. The proposed design reduces the number of multiplications compared to the conventional design by 65%. The field-programmable gate array (FPGA) implementation results indicate that the proposed architecture saves 24% of resources of the FPGA board, works faster, and saves 27% of power consumption compared to conventional FBMC transceiver.

An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor

Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency () among the existing FFT processors in the current literature.

A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

This paper presents a high throughput size-configurable floating point (FP) Fast Fourier Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback (MDF) functions suitable for applications in the real-time radar imaging system. With regard to floating-point FFT design, to acquire a high throughput with restricted area and power consumptions poses as a greater challenge due to some higher degrees of complexity involved in realizing of FP operations than those fixed-point counterparts. To address the related issues, a novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2k-point FFT. To this aid, the parallel-processing twiddle factor generator and the dual addition-and-rounding fused FP arithmetic units are optimized to meet the high accuracy demand in computation and the low power budget in implementation. The proposed FP FFT processor has been designed in silicon based on SMIC's 28 nm CMOS technology with the active area of 1.39 mm2. The prototype design delivers a throughput of 4 GSample/s at 500 MHz, at a peak power consumption of 84.2 mW. Thus, the proposed design approach achieves a significant improvement in power efficiency approximately by 14 times on average over some other FP FFT processors previously reported.

A CAD approach for suppression of power supply noise and performance analysis of some multi-core processors in pre-layout stage

In modern system-on-chip, the number of transistors has grown exponentially. This requires an efficient electrical power distribution network for proper functioning of the chip. Voltages at different nodes with respect to the desired level may vary which correspond to generation of supply noise. This paper deals with the estimation and allocation of decoupling capacitance for reduction of supply noise at the pre-layout level. Usually, decoupling capacitors are placed near the noisy functional modules, which acts as local charge storing devices and effectively reduce the transients. In this work, analysis of various sources of supply noises has been performed. Depending on the amount of supply noise, the decoupling capacitance has been estimated and allocated with minimum increment in power consumption and propagation delay. We have considered 512-points, 1-k point, 2-k point and 4-k point Fast Fourier Transform processors and International Test Conference 1999 (b14 and b17) benchmark circuits as our test circuits. This work reports up to 51.9% reduction of peak supply noise at the cost of 0.48 and 1.44% increase in power consumption and delay respectively. This estimation and subsequent allocation of decoupling capacitances will help for more accurate design and implementation at the layout stage.

Design and Implementation of Fast Fourier Transform (FFT) using VHDL Code

The Discrete Fourier Transform (DFT) can be implemented very fast using Fast Fourier Transform (FFT). It is one of the finest operation in the area of digital signal and image processing. FFT is a luxurious operation in terms of MAC. To achieve FFT calculation with a many points and with maximum number of samples the MACs requirement could not be matched by efficient hardware’s like DSP. A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM) and WLAN, unlike being stored in the traditional ROM. The twiddle factors in our pipelined FFT processor can be accessed directly. In this paper, we present the implementation of fast algorithms for the DFT for evaluating their performance. The performance of this algorithm by implementing them on the Xillinx 9.2i Spartan 3E FPGAs by developing our own FFT processor architecture.

Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.

A Shared Multiplier for Effectual Area of 1024 Point Fast Fourier Transform Processor

A Shared Multiplier for Effectual Area of 1024 Point Fast Fourier Transform Processor