Four-quadrant Analog Multiplier Research Articles

InGaZnO Thin-Film-Transistor-Based Four-Quadrant High-Gain Analog Multiplier on Glass

This letter presents a novel high-gain four-quadrant analog multiplier using only n-type enhancement indium-gallium-zinc-oxide thin-film-transistors. The proposed circuit improves the gain by using an active load with positive feedback. A Gilbert cell with a diode-connected load is also presented for comparison purposes. Both circuits were fabricated on glass at low temperature (200°C) and were successfully characterized at room temperature under normal ambient conditions, with a power supply of 15 V and 4-pF capacitive load. The novel circuit has shown a gain improvement of 7.2 dB over the Gilbert cell with the diode-connected load. Static linearity response, total harmonic distortion, frequency response, and power consumption are reported. This circuit is an important signal processing building block in large-area sensing and readout systems, specially if data communication is involved.

A Novel Low Power and Low Voltage Bulk-Input Four-Quadrant Analog Multiplier in Voltage Mode

This paper presents a new CMOS four-quadrant low voltage and low power analog multiplier circuit in voltage mode. In the proposed analog multiplier, transistors are biased in weak inversion by driving them at bulk terminals. The proposed design has fully differential ended output. Input signal ranges are ±40mV and all transistors have the equal sizes. Simulation results have been presented by HSPICE simulator in 0.18μm standard CMOS technology to confirm the operation of the circuit. The results show that the proposed analog multiplier has several advantages in comparison with other analog multipliers.

Design of a high-linear, high-precision analog multiplier, free from body effect

In this paper, a new CMOS four-quadrant analog multiplier circuit is proposed, based on a pair of dual- translinear loops. The signicant features of the circuit are its high accuracy and high linearity as well as its body effect-free operation, owing to the fact that the circuit relies on a new dual-translinear topology. In addition, harmonic distortions are precisely discussed due to their conceivable mismatches, including transconductance and threshold voltage of the transistors. HSPICE postlayout simulation results are presented to verify the validity of the theoretical analysis, where under a supply voltage of 2.8 V, the bandwidth of the proposed multiplier is 137 MHz, and the corresponding maximum linearity error remains as low as 1.12%. Moreover, the power dissipation of the proposed circuit is found to be 521 W. The presented multiplier is expected to be useful in the design of various analog signal processing applications such as modulators and frequency doublers, as illustrated in this paper.

A New Highly Accurate CMOS Current-Mode Four-Quadrant Multiplier

A new CMOS current-mode four-quadrant analog multiplier is presented. The design is based on the square-difference approach using short-channel MOSFETs operating in saturation region and a rectifier. The squaring circuit used is free of error due to carrier mobility reduction and hence an accurate multiplier is achieved. Tanner T-spice is used to confirm the functionality of the proposed design using 0.18μm TCMS CMOS process technology. Simulation results shows that the relative error is 1.8% and –3dB frequency is 230MHz.

CMOS design of a low power and high precision four-quadrant analog multiplier

In this paper, a novel current-mode Four-quadrant analog multiplier is proposed. The newly designed current squarer circuits and one current mirror which all operate in low supply voltage (2V) are the basic building blocks in realization of the mathematical equations. The multiplier circuit is designed by using 0.35μm standard CMOS technology and to validate the circuit performance, the proposed multiplier has been simulated in HSPICE simulator. The simulation results demonstrate a linearity error of 0.17%, a THD of 0.16% in 1MHz, a −3dB bandwidth of 485MHz and a maximum power consumption of 0.232mW while the static power consumption is 0.111mW.

A four-quadrant analog multiplier under a single power supply voltage

An analog multiplier driven by a single supply voltage is proposed. Some improvements are introduced so as to get a higher performance. The proposed analog multiplier can work precisely in four quadrants with a very small THD. An added OTA keeps the linearity error of the circuit smaller than 1%. The presented multiplier is designed on the 0.6 μm BCD process and the simulation results by HSPICE shows a perfect performance. It can be used in any system that requires a high performance analog multiplier.

A Four-Quadrant Analog Multiplier Based on CMOS Source Coupled Pair

A novel structure for CMOS four-quadrant analog multiplier is presented. The multiplier is based on the square law of MOSFET. To enlarge the input impedance and improve the linearity, CMOS source coupled pair was employed. Also active attenuator was used to enhance the input range. Compared with the traditional multipliers based on Gilbert cell, the proposed circuit features high linearity, high input range. Circuit simulation using HSPICE with 0.5μm CMOS technology shows that under ±2.5V supply the proposed multiplier provides linear range of more than 50% of the voltage supply, THD is 0.3% at 100kHz and 0.8% at 1MHz, -3dB bandwidth is 2.5MHz, and the power consumption is 5mW.

FOUR QUADRANT ANALOG MULTIPLIER USING DUAL-CURRENT-CONTROLLED CURRENT DIFFERENCING BUFFERED AMPLIFIER

A novel four quadrant analog multiplier (FQAM) is presented using the recently proposed active building block (ABB), namely the dual-current-controlled current differencing buffered amplifier (DCC-CDBA). The inputs to the circuit are two bipolar current signals and current and voltage outputs are available as multiplication of the input signals. The use of DCC-CDBA in four quadrant multiplier design is attractive, since the circuit structure is very simple and uses reduced number of components, viz. only one DCC-CDBA, which is constructed using two second-generation current controlled conveyors (CCCIIs). The circuit operation is current-tunable and ideally temperature insensitive. The workability of the circuit is verified using PSPICE simulations.

Four-quadrant analogue multiplier using operational amplifier

A method to realise a four-quadrant analogue multiplier using general-purpose operational amplifiers (opamps) as only the active elements is described in this article. The realisation method is based on the quarter-square technique, which utilises the inherent square-law characteristic of class AB output stage of the opamp. The multiplier can be achieved from the proposed structure with using either bipolar or complementary metal-oxide-semiconductor (CMOS) opamps. The operation principle of the proposed multiplier has been confirmed by PSPICE analogue simulation program. Simulation results reveal that the principle of proposed scheme provides an adequate performance for a four-quadrant analogue multiplier. Experimental implementations of the proposed multiplier using bipolar and CMOS opamps are performed to verify the circuit performances. Measured results of the experimental proposed schemes based on the use of bipolar and CMOS opamps with supply voltage ±2.4 V show the worst-case relative errors of 0.32% and 0.47%, and the total harmonic distortions of 0.47% and 0.98%, respectively.

Four quadrant FGMOS analog multiplier

A novel four-quadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only six FGMOS transistors. The main features of this remarkably simple multiplier circuit configuration are the large input signal range equal to 100% of the supply voltage, nonlinearity of 0.0081%, bandwidth of 1.4--1.5 Ghz and THD of maximum 2.67% (while the inputs are at their maximum values).

Design of a CMOS low-power and low-voltage four-quadrant analog multiplier

A New CMOS four-quadrant analog multiplier is presented in this paper. The proposed multiplier is suitable for low supply-voltage operation and its power consumption is also very low. The proposed circuit has been simulated with the HSPICE and simulation results are given to confirm the feasibility of the proposed analog multiplier. According to the simulation results, under the supply voltage of 1.5 V, the input range of the proposed multiplier can be 120 mV and the corresponding maximum linearity error is less than 3.2%. Moreover, the power dissipation of the proposed circuit is only 6.7 μW. The proposed circuit is expected to be useful in analog signal processing applications.

Voltage-mode threshold-independent analogue multiplier

In this article, a new threshold-independent four-quadrant analogue multiplier is designed and developed. It is based on the square-law of the MOS transistor in the saturation region and quarter-square algebraic identity. The circuit structure uses voltage summing and voltage-mode squaring stages. By applying the reference voltage to the voltage summing stage, the threshold-independent multiplication function can be achieved. On the basis of the voltage-mode circuit structure, the proposed multiplier produces an output signal in voltage form without resistors. The performances of the proposed circuit have been simulated with PSPICE. Simulation results show that the multiplier has a wide band capability, where a −3dB bandwidth of 160 MHz is achieved. The circuit has 0.75% linearity error and 0.47% total harmonic distortion under the maximum input voltage of 500 mV at both multiplier inputs. The power consumption is about 0.5 mW with a ±1.5 V power supply voltage. To verify the performances of the proposed multiplier, experimental results with discrete transistor arrays are obtained. The results will be useful in analogue signal processing applications.

New building block: multiplication-mode current conveyor

A new building block called the multiplication-mode current conveyor (MMCC) is proposed here. The structure consists of a differential voltage current conveyor (DVCC) and a folded Gilbert cell without any other auxiliary circuits. Based on the MMCC, a four-quadrant analogue multiplier is designed in TSMC 0.35 mum CMOS 2P4M processes with power supply plusmn 1.65 V. HSPICE post-layout simulation results show that the maximum DC operating range is plusmn 200 mV, the loading range is from 1 to 10 kOmega, the bandwidth is about 90 MHz, the total harmonic distortion (THD) is 0.85 , the power consumption is 1.08 mW and the chip area without pads is 0.48 times 0.36 mm 2 . The new square summer and analogue divider applications employing MMCCs are also presented.

A new high speed and low power four-quadrant CMOS analog multiplier in current mode

In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3 V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 μ m standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.1%, a THD of 0.97% in 1 MHz, a - 3 dB bandwidth of 41.8 MHz and a maximum power consumption of 0.34 mW.

Four-quadrant analog multiplier based on CMOS inverters

In the article a new implementation of four-quadrant analog multiplier in CMOS technology is proposed. The circuit is based exclusively on CMOS inverters (or similar two-transistor blocks) and operates using quarter square technique. The outstanding feature of the circuit is an extreme suitability for low voltage operation and full compatibility with digital CMOS, since there are only two transistors stacked-up between supply rails. Thus the supplying voltage of this circuit class is the lowest possible one for any particular CMOS technology. The operation principle based on symbolic analysis with simple square model has been fully confirmed by simulations with BSIM3v3 models provided by different silicon foundries and verified experimentally using one of them.

Four-Quadrant-Input Linear Transconductor Employing Source and Sink Currents Pair for Analog Multiplier

A four-quadrant-input linear transconductor generating a product or a product sum current is proposed. The proposed circuit eliminates the influence of channel length modulation and expands a dynamic input voltage range. As an application of the proposed circuit, the four-quadrant analog multiplier is designed. The four-quadrant analog multiplier consists of the proposed circuit, an input circuit and a class AB current buffer. HSPICE simulation results with 0.35 μm n-well single CMOS process parameter are shown in order to evaluate the proposed circuit.

Compact low-voltage CMOS four-quadrant analogue multiplier

A compact architecture for a four-quadrant analogue multiplier circuit is presented. The circuit is formed by connecting common source amplifiers with a pair of differential flipped voltage followers. This results in a novel cancellation of the nonlinear terms in the sub-currents, leading to the desired four-quadrant analogue multiplier. The circuit combines low complexity with low-voltage operation and low static power consumption. Simulated results using a 0.35 µm CMOS process are provided.

Experimental Results of an Analog VLSI Multiplier/Synapse /Transconductance Circuit

AbstractThe author presents a fabricated analog VLSI circuit that can be used as a four-quadrant analog multiplier with high linearity on both terms of multiplication and wide range on one of them. These characteristics make the circuit useful for the implementation of a transconductance. This circuit can be used for general purpose in analog signal processing, but the circuit is suitable for synapse analog VLSI implementation of artificial neural networks because of its small silicon area and its low power consumption. The theoretical idea and the simulation using Hspice have been presented in a previous article; that work is improved upon, fabricated, and tested in this article. Experimental results are presented.

Experimental Results of an Analog VLSI Multiplier/Synapse/Transconductance Circuit

The author presents a fabricated analog VLSI circuit that can be used as a four-quadrant analog multiplier with high linearity on both terms of multiplication and wide range on one of them. These characteristics make the circuit useful for the implementation of a transconductance. This circuit can be used for general purpose in analog signal processing, but the circuit is suitable for synapse analog VLSI implementation of artificial neural networks because of its small silicon area and its low power consumption. The theoretical idea and the simulation using Hspice have been presented in a previous article; that work is improved upon, fabricated, and tested in this article. Experimental results are presented.

A low-voltage, versatile CMOS four-quadrant analogue multiplier

This paper describes a four-quadrant analogue multiplier circuit using a low-voltage power supply. It comprises two voltage/current adders and a basic multiplier. Its major advantages over other low-voltage multipliers are that it can operate on either a single power supply or two power supplies, and that its output can be the product of two signal currents, the product of two signal voltages, or the product of a signal current and a signal voltage. Second-order effects were analysed and the simulated results revealed that: (1) for a two-power supply voltage of 2 V, the total harmonic distortion is about 1%, whereas the input voltage is 0.4 VP–P, the power dissipation is about 0.4 mW and the −3 dB bandwidth is more than 55 MHz; (2) for a single-power supply voltage of 2 V, the total harmonic distortion is about 1%, whereas the input voltage is 0.4 VP–P, the power dissipation is about 0.2 mW and the −3 dB bandwidth is more than 55 MHz. Experimental results are provided to confirm the operation of the circuit.